From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A65BFC433EF for ; Thu, 4 Nov 2021 08:35:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 890CB611C3 for ; Thu, 4 Nov 2021 08:35:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230451AbhKDIhz (ORCPT ); Thu, 4 Nov 2021 04:37:55 -0400 Received: from mail.kernel.org ([198.145.29.99]:52968 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230410AbhKDIht (ORCPT ); Thu, 4 Nov 2021 04:37:49 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id C5E7D611CB; Thu, 4 Nov 2021 08:35:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1636014911; bh=+UAkRrFFch22X7642iIOQo7roal4lSmXVN1jw2B0LFA=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=nlKmrxIcvLo9iKreFITSTsmfNMw9MhZtS/doOEhrynLCh+2S37qiw+DIAvBohsiA+ eWJypCbEbb1MKAJ062CqvAWWAw/SGjKjXif9Za0uKL+p+mAMraHDbqkH1tiHqTniG6 Tcr4xm5h6661oLizgg1SS8L7eNRaE0rEvJUwERwE= Date: Thu, 4 Nov 2021 09:34:58 +0100 From: Greg KH To: Florian Fainelli Cc: linux-kernel@vger.kernel.org, stable@vger.kernel.org, Sasha Levin , Arnd Bergmann , Thomas Bogendoerfer , Stefan Agner , Mike Rapoport , Vineet Gupta , Russell King , Ralf Baechle , Paul Burton , James Hogan , Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , Palmer Dabbelt , Albert Ou , "open list:SYNOPSYS ARC ARCHITECTURE" , "moderated list:ARM PORT" , "open list:MIPS" , "open list:LINUX FOR POWERPC (32-BIT AND 64-BIT)" , "open list:RISC-V ARCHITECTURE" , "open list:GENERIC INCLUDE/ASM HEADER FILES" Subject: Re: [PATCH stable 4.19 1/1] arch: pgtable: define MAX_POSSIBLE_PHYSMEM_BITS where needed Message-ID: References: <20211103205656.374678-1-f.fainelli@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211103205656.374678-1-f.fainelli@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-arch@vger.kernel.org On Wed, Nov 03, 2021 at 01:56:56PM -0700, Florian Fainelli wrote: > From: Arnd Bergmann > > [ Upstream commit cef397038167ac15d085914493d6c86385773709 ] > > Stefan Agner reported a bug when using zsram on 32-bit Arm machines > with RAM above the 4GB address boundary: > > Unable to handle kernel NULL pointer dereference at virtual address 00000000 > pgd = a27bd01c > [00000000] *pgd=236a0003, *pmd=1ffa64003 > Internal error: Oops: 207 [#1] SMP ARM > Modules linked in: mdio_bcm_unimac(+) brcmfmac cfg80211 brcmutil raspberrypi_hwmon hci_uart crc32_arm_ce bcm2711_thermal phy_generic genet > CPU: 0 PID: 123 Comm: mkfs.ext4 Not tainted 5.9.6 #1 > Hardware name: BCM2711 > PC is at zs_map_object+0x94/0x338 > LR is at zram_bvec_rw.constprop.0+0x330/0xa64 > pc : [] lr : [] psr: 60000013 > sp : e376bbe0 ip : 00000000 fp : c1e2921c > r10: 00000002 r9 : c1dda730 r8 : 00000000 > r7 : e8ff7a00 r6 : 00000000 r5 : 02f9ffa0 r4 : e3710000 > r3 : 000fdffe r2 : c1e0ce80 r1 : ebf979a0 r0 : 00000000 > Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user > Control: 30c5383d Table: 235c2a80 DAC: fffffffd > Process mkfs.ext4 (pid: 123, stack limit = 0x495a22e6) > Stack: (0xe376bbe0 to 0xe376c000) > > As it turns out, zsram needs to know the maximum memory size, which > is defined in MAX_PHYSMEM_BITS when CONFIG_SPARSEMEM is set, or in > MAX_POSSIBLE_PHYSMEM_BITS on the x86 architecture. > > The same problem will be hit on all 32-bit architectures that have a > physical address space larger than 4GB and happen to not enable sparsemem > and include asm/sparsemem.h from asm/pgtable.h. > > After the initial discussion, I suggested just always defining > MAX_POSSIBLE_PHYSMEM_BITS whenever CONFIG_PHYS_ADDR_T_64BIT is > set, or provoking a build error otherwise. This addresses all > configurations that can currently have this runtime bug, but > leaves all other configurations unchanged. > > I looked up the possible number of bits in source code and > datasheets, here is what I found: > > - on ARC, CONFIG_ARC_HAS_PAE40 controls whether 32 or 40 bits are used > - on ARM, CONFIG_LPAE enables 40 bit addressing, without it we never > support more than 32 bits, even though supersections in theory allow > up to 40 bits as well. > - on MIPS, some MIPS32r1 or later chips support 36 bits, and MIPS32r5 > XPA supports up to 60 bits in theory, but 40 bits are more than > anyone will ever ship > - On PowerPC, there are three different implementations of 36 bit > addressing, but 32-bit is used without CONFIG_PTE_64BIT > - On RISC-V, the normal page table format can support 34 bit > addressing. There is no highmem support on RISC-V, so anything > above 2GB is unused, but it might be useful to eventually support > CONFIG_ZRAM for high pages. > > Fixes: 61989a80fb3a ("staging: zsmalloc: zsmalloc memory allocation library") > Fixes: 02390b87a945 ("mm/zsmalloc: Prepare to variable MAX_PHYSMEM_BITS") > Acked-by: Thomas Bogendoerfer > Reviewed-by: Stefan Agner > Tested-by: Stefan Agner > Acked-by: Mike Rapoport > Link: https://lore.kernel.org/linux-mm/bdfa44bf1c570b05d6c70898e2bbb0acf234ecdf.1604762181.git.stefan@agner.ch/ > Signed-off-by: Arnd Bergmann > Signed-off-by: Sasha Levin > [florian: patch arch/powerpc/include/asm/pte-common.h for 4.19.y] > Signed-off-by: Florian Fainelli All now queued up, thanks. greg k-h