From: Bagas Sanjaya <bagasdotme@gmail.com>
To: Huacai Chen <chenhuacai@loongson.cn>
Cc: Arnd Bergmann <arnd@arndb.de>, Andy Lutomirski <luto@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Peter Zijlstra <peterz@infradead.org>,
Andrew Morton <akpm@linux-foundation.org>,
David Airlie <airlied@linux.ie>, Jonathan Corbet <corbet@lwn.net>,
Linus Torvalds <torvalds@linux-foundation.org>,
linux-arch@vger.kernel.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, Xuefeng Li <lixuefeng@loongson.cn>,
Yanteng Si <siyanteng@loongson.cn>,
Huacai Chen <chenhuacai@gmail.com>, Guo Ren <guoren@kernel.org>,
Xuerui Wang <kernel@xen0n.name>,
Jiaxun Yang <jiaxun.yang@flygoat.com>
Subject: Re: [PATCH V9 01/24] Documentation: LoongArch: Add basic documentations
Date: Sun, 1 May 2022 14:48:52 +0700 [thread overview]
Message-ID: <Ym47ZAuwEA9as98h@debian.me> (raw)
In-Reply-To: <20220430090518.3127980-2-chenhuacai@loongson.cn>
On Sat, Apr 30, 2022 at 05:04:55PM +0800, Huacai Chen wrote:
> +Instruction names (Mnemonics)
> +-----------------------------
> +
> +We only list the instruction names here, for details please read the references.
> +
> +Arithmetic Operation Instructions::
> +
> + ADD.W SUB.W ADDI.W ADD.D SUB.D ADDI.D
> + SLT SLTU SLTI SLTUI
> + AND OR NOR XOR ANDN ORN ANDI ORI XORI
> + MUL.W MULH.W MULH.WU DIV.W DIV.WU MOD.W MOD.WU
> + MUL.D MULH.D MULH.DU DIV.D DIV.DU MOD.D MOD.DU
> + PCADDI PCADDU12I PCADDU18I
> + LU12I.W LU32I.D LU52I.D ADDU16I.D
> +
> +Bit-shift Instructions::
> +
> + SLL.W SRL.W SRA.W ROTR.W SLLI.W SRLI.W SRAI.W ROTRI.W
> + SLL.D SRL.D SRA.D ROTR.D SLLI.D SRLI.D SRAI.D ROTRI.D
> +
> +Bit-manipulation Instructions::
> +
> + EXT.W.B EXT.W.H CLO.W CLO.D SLZ.W CLZ.D CTO.W CTO.D CTZ.W CTZ.D
> + BYTEPICK.W BYTEPICK.D BSTRINS.W BSTRINS.D BSTRPICK.W BSTRPICK.D
> + REVB.2H REVB.4H REVB.2W REVB.D REVH.2W REVH.D BITREV.4B BITREV.8B BITREV.W BITREV.D
> + MASKEQZ MASKNEZ
> +
> +Branch Instructions::
> +
> + BEQ BNE BLT BGE BLTU BGEU BEQZ BNEZ B BL JIRL
> +
> +Load/Store Instructions::
> +
> + LD.B LD.BU LD.H LD.HU LD.W LD.WU LD.D ST.B ST.H ST.W ST.D
> + LDX.B LDX.BU LDX.H LDX.HU LDX.W LDX.WU LDX.D STX.B STX.H STX.W STX.D
> + LDPTR.W LDPTR.D STPTR.W STPTR.D
> + PRELD PRELDX
> +
> +Atomic Operation Instructions::
> +
> + LL.W SC.W LL.D SC.D
> + AMSWAP.W AMSWAP.D AMADD.W AMADD.D AMAND.W AMAND.D AMOR.W AMOR.D AMXOR.W AMXOR.D
> + AMMAX.W AMMAX.D AMMIN.W AMMIN.D
> +
> +Barrier Instructions::
> +
> + IBAR DBAR
> +
> +Special Instructions::
> +
> + SYSCALL BREAK CPUCFG NOP IDLE ERTN DBCL RDTIMEL.W RDTIMEH.W RDTIME.D ASRTLE.D ASRTGT.D
> +
> +Privileged Instructions::
> +
> + CSRRD CSRWR CSRXCHG
> + IOCSRRD.B IOCSRRD.H IOCSRRD.W IOCSRRD.D IOCSRWR.B IOCSRWR.H IOCSRWR.W IOCSRWR.D
> + CACOP TLBP(TLBSRCH) TLBRD TLBWR TLBFILL TLBCLR TLBFLUSH INVTLB LDDIR LDPTE
> +
Since these above are list of instruction categories, it's better to use
enumerated lists. Also, make use of ReST labels to link to References
sections, like this:
-- >8 --
diff --git a/Documentation/loongarch/introduction.rst b/Documentation/loongarch/introduction.rst
index 420c0d2ebcfbe7..2d83283ecf28b9 100644
--- a/Documentation/loongarch/introduction.rst
+++ b/Documentation/loongarch/introduction.rst
@@ -194,60 +194,61 @@ can see I21L/I21H and I26L/I26H here.
Instruction names (Mnemonics)
-----------------------------
-We only list the instruction names here, for details please read the references.
+We only list the instruction names here, for details please read the
+:ref:`references <loongarch-references>`.
-Arithmetic Operation Instructions::
+1. Arithmetic Operation Instructions::
- ADD.W SUB.W ADDI.W ADD.D SUB.D ADDI.D
- SLT SLTU SLTI SLTUI
- AND OR NOR XOR ANDN ORN ANDI ORI XORI
- MUL.W MULH.W MULH.WU DIV.W DIV.WU MOD.W MOD.WU
- MUL.D MULH.D MULH.DU DIV.D DIV.DU MOD.D MOD.DU
- PCADDI PCADDU12I PCADDU18I
- LU12I.W LU32I.D LU52I.D ADDU16I.D
+ ADD.W SUB.W ADDI.W ADD.D SUB.D ADDI.D
+ SLT SLTU SLTI SLTUI
+ AND OR NOR XOR ANDN ORN ANDI ORI XORI
+ MUL.W MULH.W MULH.WU DIV.W DIV.WU MOD.W MOD.WU
+ MUL.D MULH.D MULH.DU DIV.D DIV.DU MOD.D MOD.DU
+ PCADDI PCADDU12I PCADDU18I
+ LU12I.W LU32I.D LU52I.D ADDU16I.D
-Bit-shift Instructions::
+2. Bit-shift Instructions::
- SLL.W SRL.W SRA.W ROTR.W SLLI.W SRLI.W SRAI.W ROTRI.W
- SLL.D SRL.D SRA.D ROTR.D SLLI.D SRLI.D SRAI.D ROTRI.D
+ SLL.W SRL.W SRA.W ROTR.W SLLI.W SRLI.W SRAI.W ROTRI.W
+ SLL.D SRL.D SRA.D ROTR.D SLLI.D SRLI.D SRAI.D ROTRI.D
-Bit-manipulation Instructions::
+3. Bit-manipulation Instructions::
- EXT.W.B EXT.W.H CLO.W CLO.D SLZ.W CLZ.D CTO.W CTO.D CTZ.W CTZ.D
- BYTEPICK.W BYTEPICK.D BSTRINS.W BSTRINS.D BSTRPICK.W BSTRPICK.D
- REVB.2H REVB.4H REVB.2W REVB.D REVH.2W REVH.D BITREV.4B BITREV.8B BITREV.W BITREV.D
- MASKEQZ MASKNEZ
+ EXT.W.B EXT.W.H CLO.W CLO.D SLZ.W CLZ.D CTO.W CTO.D CTZ.W CTZ.D
+ BYTEPICK.W BYTEPICK.D BSTRINS.W BSTRINS.D BSTRPICK.W BSTRPICK.D
+ REVB.2H REVB.4H REVB.2W REVB.D REVH.2W REVH.D BITREV.4B BITREV.8B BITREV.W BITREV.D
+ MASKEQZ MASKNEZ
-Branch Instructions::
+4. Branch Instructions::
- BEQ BNE BLT BGE BLTU BGEU BEQZ BNEZ B BL JIRL
+ BEQ BNE BLT BGE BLTU BGEU BEQZ BNEZ B BL JIRL
-Load/Store Instructions::
+5. Load/Store Instructions::
- LD.B LD.BU LD.H LD.HU LD.W LD.WU LD.D ST.B ST.H ST.W ST.D
- LDX.B LDX.BU LDX.H LDX.HU LDX.W LDX.WU LDX.D STX.B STX.H STX.W STX.D
- LDPTR.W LDPTR.D STPTR.W STPTR.D
- PRELD PRELDX
+ LD.B LD.BU LD.H LD.HU LD.W LD.WU LD.D ST.B ST.H ST.W ST.D
+ LDX.B LDX.BU LDX.H LDX.HU LDX.W LDX.WU LDX.D STX.B STX.H STX.W STX.D
+ LDPTR.W LDPTR.D STPTR.W STPTR.D
+ PRELD PRELDX
-Atomic Operation Instructions::
+6. Atomic Operation Instructions::
- LL.W SC.W LL.D SC.D
- AMSWAP.W AMSWAP.D AMADD.W AMADD.D AMAND.W AMAND.D AMOR.W AMOR.D AMXOR.W AMXOR.D
- AMMAX.W AMMAX.D AMMIN.W AMMIN.D
+ LL.W SC.W LL.D SC.D
+ AMSWAP.W AMSWAP.D AMADD.W AMADD.D AMAND.W AMAND.D AMOR.W AMOR.D AMXOR.W AMXOR.D
+ AMMAX.W AMMAX.D AMMIN.W AMMIN.D
-Barrier Instructions::
+7. Barrier Instructions::
- IBAR DBAR
+ IBAR DBAR
-Special Instructions::
+8. Special Instructions::
- SYSCALL BREAK CPUCFG NOP IDLE ERTN DBCL RDTIMEL.W RDTIMEH.W RDTIME.D ASRTLE.D ASRTGT.D
+ SYSCALL BREAK CPUCFG NOP IDLE ERTN DBCL RDTIMEL.W RDTIMEH.W RDTIME.D ASRTLE.D ASRTGT.D
-Privileged Instructions::
+9. Privileged Instructions::
- CSRRD CSRWR CSRXCHG
- IOCSRRD.B IOCSRRD.H IOCSRRD.W IOCSRRD.D IOCSRWR.B IOCSRWR.H IOCSRWR.W IOCSRWR.D
- CACOP TLBP(TLBSRCH) TLBRD TLBWR TLBFILL TLBCLR TLBFLUSH INVTLB LDDIR LDPTE
+ CSRRD CSRWR CSRXCHG
+ IOCSRRD.B IOCSRRD.H IOCSRRD.W IOCSRRD.D IOCSRWR.B IOCSRWR.H IOCSRWR.W IOCSRWR.D
+ CACOP TLBP(TLBSRCH) TLBRD TLBWR TLBFILL TLBCLR TLBFLUSH INVTLB LDDIR LDPTE
Virtual Memory
==============
@@ -315,6 +316,8 @@ MIPS, while New Loongson is based on LoongArch. Take Loongson-3 as an example:
Loongson-3A1000/3B1500/3A2000/3A3000/3A4000 are MIPS-compatible, while Loongson-
3A5000 (and future revisions) are all based on LoongArch.
+.. _loongarch-references:
+
References
==========
> +
> + +---------------------------------------------+
> + |:: |
> + | |
> + | +-----+ +---------+ +-------+ |
> + | | IPI | --> | CPUINTC | <-- | Timer | |
> + | +-----+ +---------+ +-------+ |
> + | ^ |
> + | | |
> + | +---------+ +-------+ |
> + | | LIOINTC | <-- | UARTs | |
> + | +---------+ +-------+ |
> + | ^ |
> + | | |
> + | +-----------+ |
> + | | HTVECINTC | |
> + | +-----------+ |
> + | ^ ^ |
> + | | | |
> + | +---------+ +---------+ |
> + | | PCH-PIC | | PCH-MSI | |
> + | +---------+ +---------+ |
> + | ^ ^ ^ |
> + | | | | |
> + | +---------+ +---------+ +---------+ |
> + | | PCH-LPC | | Devices | | Devices | |
> + | +---------+ +---------+ +---------+ |
> + | ^ |
> + | | |
> + | +---------+ |
> + | | Devices | |
> + | +---------+ |
> + | |
> + | |
> + +---------------------------------------------+
> +
...
> +
> + +--------------------------------------------------------+
> + |:: |
> + | |
> + | +-----+ +---------+ +-------+ |
> + | | IPI | --> | CPUINTC | <-- | Timer | |
> + | +-----+ +---------+ +-------+ |
> + | ^ ^ |
> + | | | |
> + | +---------+ +---------+ +-------+ |
> + | | EIOINTC | | LIOINTC | <-- | UARTs | |
> + | +---------+ +---------+ +-------+ |
> + | ^ ^ |
> + | | | |
> + | +---------+ +---------+ |
> + | | PCH-PIC | | PCH-MSI | |
> + | +---------+ +---------+ |
> + | ^ ^ ^ |
> + | | | | |
> + | +---------+ +---------+ +---------+ |
> + | | PCH-LPC | | Devices | | Devices | |
> + | +---------+ +---------+ +---------+ |
> + | ^ |
> + | | |
> + | +---------+ |
> + | | Devices | |
> + | +---------+ |
> + | |
> + | |
> + +--------------------------------------------------------+
> +
I think just literal blocks is enough for the diagrams above.
--
An old man doll... just what I always wanted! - Clara
next prev parent reply other threads:[~2022-05-01 7:49 UTC|newest]
Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-30 9:04 [PATCH V9 00/22] arch: Add basic LoongArch support Huacai Chen
2022-04-30 9:04 ` [PATCH V9 01/24] Documentation: LoongArch: Add basic documentations Huacai Chen
2022-05-01 7:48 ` Bagas Sanjaya [this message]
2022-05-01 8:55 ` Huacai Chen
2022-05-01 9:32 ` WANG Xuerui
2022-05-01 10:17 ` Huacai Chen
2022-04-30 9:04 ` [PATCH V9 02/24] Documentation/zh_CN: Add basic LoongArch documentations Huacai Chen
2022-05-01 9:38 ` WANG Xuerui
2022-04-30 9:04 ` [PATCH V9 03/24] LoongArch: Add elf-related definitions Huacai Chen
2022-05-01 9:41 ` WANG Xuerui
2022-05-01 14:27 ` Huacai Chen
2022-04-30 9:04 ` [PATCH V9 04/24] LoongArch: Add writecombine support for drm Huacai Chen
2022-04-30 9:04 ` [PATCH V9 05/24] LoongArch: Add build infrastructure Huacai Chen
2022-05-01 10:09 ` WANG Xuerui
2022-05-01 12:41 ` Huacai Chen
2022-05-01 15:43 ` Xi Ruoyao
2022-04-30 9:05 ` [PATCH V9 06/24] LoongArch: Add CPU definition headers Huacai Chen
2022-05-01 11:05 ` WANG Xuerui
2022-04-30 9:05 ` [PATCH V9 07/24] LoongArch: Add atomic/locking headers Huacai Chen
2022-05-01 11:16 ` WANG Xuerui
2022-05-01 13:16 ` Huacai Chen
2022-04-30 9:05 ` [PATCH V9 08/24] LoongArch: Add other common headers Huacai Chen
2022-05-01 11:39 ` WANG Xuerui
2022-05-01 14:26 ` Huacai Chen
2022-04-30 9:05 ` [PATCH V9 09/24] LoongArch: Add boot and setup routines Huacai Chen
2022-04-30 9:05 ` [PATCH V9 10/24] LoongArch: Add exception/interrupt handling Huacai Chen
2022-05-01 16:27 ` Xi Ruoyao
2022-05-01 17:08 ` Xi Ruoyao
2022-05-02 0:01 ` Huacai Chen
2022-04-30 9:05 ` [PATCH V9 11/24] LoongArch: Add process management Huacai Chen
2022-04-30 9:05 ` [PATCH V9 12/24] LoongArch: Add memory management Huacai Chen
2022-04-30 9:05 ` [PATCH V9 13/24] LoongArch: Add system call support Huacai Chen
2022-04-30 9:44 ` Arnd Bergmann
2022-04-30 10:05 ` Huacai Chen
2022-04-30 10:34 ` Arnd Bergmann
2022-05-07 12:11 ` Christian Brauner
2022-05-09 10:00 ` Christian Brauner
2022-05-11 7:11 ` Arnd Bergmann
2022-05-11 21:12 ` [musl] " Rich Felker
2022-05-12 7:21 ` Arnd Bergmann
2022-05-12 12:11 ` Rich Felker
2022-05-11 16:17 ` Florian Weimer
2022-04-30 9:05 ` [PATCH V9 14/24] LoongArch: Add signal handling support Huacai Chen
2022-04-30 9:05 ` [PATCH V9 15/24] LoongArch: Add elf and module support Huacai Chen
2022-04-30 9:05 ` [PATCH V9 16/24] LoongArch: Add misc common routines Huacai Chen
2022-04-30 9:50 ` Arnd Bergmann
2022-04-30 10:00 ` Huacai Chen
2022-04-30 10:41 ` Arnd Bergmann
2022-04-30 13:22 ` Palmer Dabbelt
2022-05-01 5:12 ` Huacai Chen
2022-04-30 9:05 ` [PATCH V9 17/24] LoongArch: Add some library functions Huacai Chen
2022-05-01 10:55 ` Guo Ren
2022-05-01 12:18 ` Huacai Chen
2022-04-30 9:05 ` [PATCH V9 18/24] LoongArch: Add PCI controller support Huacai Chen
2022-04-30 9:05 ` [PATCH V9 19/24] LoongArch: Add VDSO and VSYSCALL support Huacai Chen
2022-04-30 9:05 ` [PATCH V9 20/24] LoongArch: Add efistub booting support Huacai Chen
2022-04-30 9:56 ` Arnd Bergmann
2022-04-30 10:02 ` Huacai Chen
2022-05-03 7:23 ` Ard Biesheuvel
2022-05-05 9:59 ` Huacai Chen
2022-05-06 8:14 ` Ard Biesheuvel
2022-05-06 11:26 ` WANG Xuerui
2022-05-06 11:41 ` Arnd Bergmann
2022-05-06 13:20 ` Huacai Chen
2022-05-13 19:32 ` Arnd Bergmann
2022-05-14 2:27 ` Huacai Chen
2022-04-30 9:05 ` [PATCH V9 21/24] LoongArch: Add zboot (compressed kernel) support Huacai Chen
2022-04-30 10:07 ` Arnd Bergmann
2022-05-01 5:22 ` Huacai Chen
2022-05-01 6:35 ` Russell King (Oracle)
2022-05-01 8:46 ` Huacai Chen
2022-05-01 11:28 ` Russell King (Oracle)
2022-05-01 8:33 ` Arnd Bergmann
2022-05-01 23:36 ` Ard Biesheuvel
2022-04-30 9:05 ` [PATCH V9 22/24] LoongArch: Add multi-processor (SMP) support Huacai Chen
2022-04-30 9:05 ` [PATCH V9 23/24] LoongArch: Add Non-Uniform Memory Access (NUMA) support Huacai Chen
2022-04-30 9:05 ` [PATCH V9 24/24] LoongArch: Add Loongson-3 default config file Huacai Chen
2022-05-01 8:19 ` [PATCH V9 00/22] arch: Add basic LoongArch support Bagas Sanjaya
2022-05-01 8:55 ` Huacai Chen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=Ym47ZAuwEA9as98h@debian.me \
--to=bagasdotme@gmail.com \
--cc=airlied@linux.ie \
--cc=akpm@linux-foundation.org \
--cc=arnd@arndb.de \
--cc=chenhuacai@gmail.com \
--cc=chenhuacai@loongson.cn \
--cc=corbet@lwn.net \
--cc=guoren@kernel.org \
--cc=jiaxun.yang@flygoat.com \
--cc=kernel@xen0n.name \
--cc=linux-arch@vger.kernel.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=lixuefeng@loongson.cn \
--cc=luto@kernel.org \
--cc=peterz@infradead.org \
--cc=siyanteng@loongson.cn \
--cc=tglx@linutronix.de \
--cc=torvalds@linux-foundation.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).