Re: Cache maintenance for non-coherent DMA in arch_sync_dma_for_device()

[Catalin Marinas <catalin.marinas@arm.com>]

On Mon, Jun 06, 2022 at 04:35:07PM +0100, Russell King wrote:
> On Mon, Jun 06, 2022 at 04:21:50PM +0100, Will Deacon wrote:
> > Finally, on arm(64), the DMA mapping code tries to deal with buffers
> > that are not cacheline aligned by issuing clean-and-invalidate
> > operations for the overlapping portions at each end of the buffer. I
> > don't think this makes a tonne of sense, as inevitably one of the
> > writers (either the CPU or the DMA) is going to win and somebody is
> > going to run into silent data loss. Having the caller receive
> > DMA_MAPPING_ERROR in this case would probably be better.
> 
> Sadly unavoidable - people really like passing unaligned buffers to the
> DMA API, sometimes those buffers contain information that needs to be
> preserved. I really wish it wasn't that way, because it would make life
> a lot better, but it's what we've had to deal with over the years with
> the likes of the SCSI subsystem (and e.g. it's sense buffer that was
> embedded non-cacheline aligned into other structures that had to be
> DMA'd to.)

As Will said, you either corrupt the DMA buffer or the kernel data
sharing the cache line, you can't really win. Current behaviour favours
the kernel data and somehow hopes that there won't be any write to the
cache line by the CPU before the DMA transfer completes. If this hope
holds, the fix to clean (instead of invalidate) in __dma_map_area()
should be sufficient, no need for boundary checks and alignment.

-- 
Catalin