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[116.206.12.38]) by smtp.gmail.com with ESMTPSA id r12-20020a17090b050c00b001e0c1044ceasm3937393pjz.43.2022.06.02.18.45.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 18:45:21 -0700 (PDT) Date: Fri, 3 Jun 2022 08:45:18 +0700 From: Bagas Sanjaya To: Huacai Chen Cc: Arnd Bergmann , Andy Lutomirski , Thomas Gleixner , Peter Zijlstra , Andrew Morton , David Airlie , Jonathan Corbet , Linus Torvalds , linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Xuefeng Li , Yanteng Si , Huacai Chen , Guo Ren , Xuerui Wang , Jiaxun Yang , Stephen Rothwell , WANG Xuerui Subject: Re: [PATCH V14 03/24] Documentation: LoongArch: Add basic documentations Message-ID: References: <20220602115141.3962749-1-chenhuacai@loongson.cn> <20220602115141.3962749-4-chenhuacai@loongson.cn> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20220602115141.3962749-4-chenhuacai@loongson.cn> Precedence: bulk List-ID: X-Mailing-List: linux-arch@vger.kernel.org On Thu, Jun 02, 2022 at 07:51:20PM +0800, Huacai Chen wrote: > +Legacy IRQ model > +================ > + > +In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go > +to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices > +interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go > +to LIOINTC, and then CPUINTC. > + > + +---------------------------------------------+ > + |:: | > + | | > + | +-----+ +---------+ +-------+ | > + | | IPI | --> | CPUINTC | <-- | Timer | | > + | +-----+ +---------+ +-------+ | > + | ^ | > + | | | > + | +---------+ +-------+ | > + | | LIOINTC | <-- | UARTs | | > + | +---------+ +-------+ | > + | ^ | > + | | | > + | +-----------+ | > + | | HTVECINTC | | > + | +-----------+ | > + | ^ ^ | > + | | | | > + | +---------+ +---------+ | > + | | PCH-PIC | | PCH-MSI | | > + | +---------+ +---------+ | > + | ^ ^ ^ | > + | | | | | > + | +---------+ +---------+ +---------+ | > + | | PCH-LPC | | Devices | | Devices | | > + | +---------+ +---------+ +---------+ | > + | ^ | > + | | | > + | +---------+ | > + | | Devices | | > + | +---------+ | > + | | > + | | > + +---------------------------------------------+ > + > +Extended IRQ model > +================== > + > +In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go > +to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices > +interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to > +to CPUINTC directly. > + > + +--------------------------------------------------------+ > + |:: | > + | | > + | +-----+ +---------+ +-------+ | > + | | IPI | --> | CPUINTC | <-- | Timer | | > + | +-----+ +---------+ +-------+ | > + | ^ ^ | > + | | | | > + | +---------+ +---------+ +-------+ | > + | | EIOINTC | | LIOINTC | <-- | UARTs | | > + | +---------+ +---------+ +-------+ | > + | ^ ^ | > + | | | | > + | +---------+ +---------+ | > + | | PCH-PIC | | PCH-MSI | | > + | +---------+ +---------+ | > + | ^ ^ ^ | > + | | | | | > + | +---------+ +---------+ +---------+ | > + | | PCH-LPC | | Devices | | Devices | | > + | +---------+ +---------+ +---------+ | > + | ^ | > + | | | > + | +---------+ | > + | | Devices | | > + | +---------+ | > + | | > + | | > + +--------------------------------------------------------+ > + I think for consistency with other diagrams in Documentation/, just use literal code block, like: diff --git a/Documentation/loongarch/irq-chip-model.rst b/Documentation/loongarch/irq-chip-model.rst index 35c962991283ff..3cfd528021de05 100644 --- a/Documentation/loongarch/irq-chip-model.rst +++ b/Documentation/loongarch/irq-chip-model.rst @@ -24,40 +24,38 @@ to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go to LIOINTC, and then CPUINTC. - +---------------------------------------------+ - |:: | - | | - | +-----+ +---------+ +-------+ | - | | IPI | --> | CPUINTC | <-- | Timer | | - | +-----+ +---------+ +-------+ | - | ^ | - | | | - | +---------+ +-------+ | - | | LIOINTC | <-- | UARTs | | - | +---------+ +-------+ | - | ^ | - | | | - | +-----------+ | - | | HTVECINTC | | - | +-----------+ | - | ^ ^ | - | | | | - | +---------+ +---------+ | - | | PCH-PIC | | PCH-MSI | | - | +---------+ +---------+ | - | ^ ^ ^ | - | | | | | - | +---------+ +---------+ +---------+ | - | | PCH-LPC | | Devices | | Devices | | - | +---------+ +---------+ +---------+ | - | ^ | - | | | - | +---------+ | - | | Devices | | - | +---------+ | - | | - | | - +---------------------------------------------+ + :: + + +-----+ +---------+ +-------+ + | IPI | --> | CPUINTC | <-- | Timer | + +-----+ +---------+ +-------+ + ^ + | + +---------+ +-------+ + | LIOINTC | <-- | UARTs | + +---------+ +-------+ + ^ + | + +-----------+ + | HTVECINTC | + +-----------+ + ^ ^ + | | + +---------+ +---------+ + | PCH-PIC | | PCH-MSI | + +---------+ +---------+ + ^ ^ ^ + | | | + +---------+ +---------+ +---------+ + | PCH-LPC | | Devices | | Devices | + +---------+ +---------+ +---------+ + ^ + | + +---------+ + | Devices | + +---------+ + + Extended IRQ model ================== @@ -67,35 +65,33 @@ to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to to CPUINTC directly. - +--------------------------------------------------------+ - |:: | - | | - | +-----+ +---------+ +-------+ | - | | IPI | --> | CPUINTC | <-- | Timer | | - | +-----+ +---------+ +-------+ | - | ^ ^ | - | | | | - | +---------+ +---------+ +-------+ | - | | EIOINTC | | LIOINTC | <-- | UARTs | | - | +---------+ +---------+ +-------+ | - | ^ ^ | - | | | | - | +---------+ +---------+ | - | | PCH-PIC | | PCH-MSI | | - | +---------+ +---------+ | - | ^ ^ ^ | - | | | | | - | +---------+ +---------+ +---------+ | - | | PCH-LPC | | Devices | | Devices | | - | +---------+ +---------+ +---------+ | - | ^ | - | | | - | +---------+ | - | | Devices | | - | +---------+ | - | | - | | - +--------------------------------------------------------+ + :: + + +-----+ +---------+ +-------+ + | IPI | --> | CPUINTC | <-- | Timer | + +-----+ +---------+ +-------+ + ^ ^ + | | + +---------+ +---------+ +-------+ + | EIOINTC | | LIOINTC | <-- | UARTs | + +---------+ +---------+ +-------+ + ^ ^ + | | + +---------+ +---------+ + | PCH-PIC | | PCH-MSI | + +---------+ +---------+ + ^ ^ ^ + | | | + +---------+ +---------+ +---------+ + | PCH-LPC | | Devices | | Devices | + +---------+ +---------+ +---------+ + ^ + | + +---------+ + | Devices | + +---------+ + + ACPI-related definitions ======================== Otherwise, htmldocs builds successfully without any new warnings related to this patch series. Tested-by: Bagas Sanjaya -- An old man doll... just what I always wanted! - Clara