From: Deepak Gupta <debug@rivosinc.com>
To: "Radim Krčmář" <rkrcmar@ventanamicro.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
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Subject: Re: [PATCH v12 05/28] riscv: usercfi state for task and save/restore of CSR_SSP on trap entry/exit
Date: Thu, 24 Apr 2025 10:56:34 -0700 [thread overview]
Message-ID: <aAp7Un415hNqtshd@debug.ba.rivosinc.com> (raw)
In-Reply-To: <D9EUJBQ5OHN0.2KUJHGXK262TR@ventanamicro.com>
On Thu, Apr 24, 2025 at 01:52:43PM +0200, Radim Krčmář wrote:
>2025-04-23T17:00:29-07:00, Deepak Gupta <debug@rivosinc.com>:
>> On Thu, Apr 10, 2025 at 01:04:39PM +0200, Radim Krčmář wrote:
>>>2025-03-14T14:39:24-07:00, Deepak Gupta <debug@rivosinc.com>:
>>>> diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/thread_info.h
>>>> @@ -62,6 +62,9 @@ struct thread_info {
>>>> long user_sp; /* User stack pointer */
>>>> int cpu;
>>>> unsigned long syscall_work; /* SYSCALL_WORK_ flags */
>>>> +#ifdef CONFIG_RISCV_USER_CFI
>>>> + struct cfi_status user_cfi_state;
>>>> +#endif
>>>
>>>I don't think it makes sense to put all the data in thread_info.
>>>kernel_ssp and user_ssp is more than enough and the rest can comfortably
>>>live elsewhere in task_struct.
>>>
>>>thread_info is supposed to be as small as possible -- just spanning
>>>multiple cache-lines could be noticeable.
>>
>> I can change it to only include only `user_ssp`, base and size.
>
>No need for base and size either -- we don't touch that in the common
>exception code.
got it.
>
>> But before we go there, see below:
>>
>> $ pahole -C thread_info kbuild/vmlinux
>> struct thread_info {
>> long unsigned int flags; /* 0 8 */
>> int preempt_count; /* 8 4 */
>>
>> /* XXX 4 bytes hole, try to pack */
>>
>> long int kernel_sp; /* 16 8 */
>> long int user_sp; /* 24 8 */
>> int cpu; /* 32 4 */
>>
>> /* XXX 4 bytes hole, try to pack */
>>
>> long unsigned int syscall_work; /* 40 8 */
>> struct cfi_status user_cfi_state; /* 48 32 */
>> /* --- cacheline 1 boundary (64 bytes) was 16 bytes ago --- */
>> long unsigned int a0; /* 80 8 */
>> long unsigned int a1; /* 88 8 */
>> long unsigned int a2; /* 96 8 */
>>
>> /* size: 104, cachelines: 2, members: 10 */
>> /* sum members: 96, holes: 2, sum holes: 8 */
>> /* last cacheline: 40 bytes */
>> };
>>
>> If we were to remove entire `cfi_status`, it would still be 72 bytes (88 bytes
>> if shadow call stack were enabled) and already spans across two cachelines.
>
>It has only 64 bytes of data without shadow call stack, but it wasted 8
>bytes on the holes.
>a2 is somewhat an outlier that is not used most exception paths and
>excluding it makes everything fit nicely even now.
But we can't exclude shadow call stack. It'll lead to increased size if that
config is selected. A solution has to work for all the cases and not half
hearted effort.
>
>> if shadow call stack were enabled) and already spans across two cachelines. I
>> did see the comment above that it should fit inside a cacheline. Although I
>> assumed its stale comment given that it already spans across cacheline and I
>> didn't see any special mention in commit messages of changes which grew this
>> structure above one cacheline. So I assumed this was a stale comment.
>>
>> On the other hand, whenever enable/lock bits are checked, there is a high
>> likelyhood that user_ssp and other fields are going to be accessed and
>> thus it actually might be helpful to have it all in one cacheline during
>> runtime.
>
>Yes, although accessing enable/lock bits will be relatively rare.
>It seems better to have the overhead during thread setup, rather than on
>every trap.
>
>> So I am not sure if its helpful sticking to the comment which already is stale.
>
>We could fix the holes and also use sp instead of a0 in the
>new_vmalloc_check, so everything would fit better.
>
>We are really close to fitting into a single cache-line, so I'd prefer
>if shadow stack only filled thread_info with data that is used very
>often in the exception handling code.
I don't get what's the big deal if it results in two cachelines. We can
(re)organize data structure in a way the most frequently accessed members are
together in a single cacheline. We just need to find those members.
In the hot path of exception handling, I see accesses to pt_regs on stack as
well. These are definitley different cacheline than thread_info.
I understand the argument of one member field crossing into two cachelines can
have undesired perf effects. I do not understand reasoning that thread_info
exactly has to fit inside one cacheline.
If this was always supposed to fit in a single cacheline, clearly this
invariant isn't/wasn't maintained as changes trickled in. I would like to see
what maintainers have to say or someone who did data analysis on this.
>
>I think we could do without user_sp in thread_info as well, so there are
>other packing options.
Sure, probably somewhere in task_struct. But fact of the matter is that it has
to be saved/restore during exception entry/exit. But then load/store to
task_struct is essentially a different cachline. Not sure what we will achieve
here?
>
>Btw. could ssp be added to pt_regs?
I had that earlier. It breaks user abi. And it was a no go.
>
>Thanks.
next prev parent reply other threads:[~2025-04-24 17:56 UTC|newest]
Thread overview: 83+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-14 21:39 [PATCH v12 00/28] riscv control-flow integrity for usermode Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 01/28] mm: VM_SHADOW_STACK definition for riscv Deepak Gupta
2025-04-07 15:45 ` Alexandre Ghiti
2025-03-14 21:39 ` [PATCH v12 02/28] dt-bindings: riscv: zicfilp and zicfiss in dt-bindings (extensions.yaml) Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 03/28] riscv: zicfiss / zicfilp enumeration Deepak Gupta
2025-04-07 15:48 ` Alexandre Ghiti
2025-04-09 14:43 ` Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 04/28] riscv: zicfiss / zicfilp extension csr and bit definitions Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 05/28] riscv: usercfi state for task and save/restore of CSR_SSP on trap entry/exit Deepak Gupta
2025-04-08 8:05 ` Alexandre Ghiti
2025-04-10 11:04 ` Radim Krčmář
2025-04-24 0:00 ` Deepak Gupta
2025-04-24 11:52 ` Radim Krčmář
2025-04-24 17:56 ` Deepak Gupta [this message]
2025-04-25 11:27 ` Radim Krčmář
2025-04-24 0:23 ` Deepak Gupta
2025-04-24 12:16 ` Radim Krčmář
2025-04-24 18:03 ` Deepak Gupta
2025-04-25 11:32 ` Radim Krčmář
2025-03-14 21:39 ` [PATCH v12 06/28] riscv/mm : ensure PROT_WRITE leads to VM_READ | VM_WRITE Deepak Gupta
2025-04-08 10:39 ` Alexandre Ghiti
2025-04-10 10:03 ` Radim Krčmář
2025-04-24 0:45 ` Deepak Gupta
2025-04-24 12:23 ` Radim Krčmář
2025-04-24 12:43 ` Arnd Bergmann
2025-03-14 21:39 ` [PATCH v12 07/28] riscv mm: manufacture shadow stack pte Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 08/28] riscv mmu: teach pte_mkwrite to manufacture shadow stack PTEs Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 09/28] riscv mmu: write protect and shadow stack Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 10/28] riscv/mm: Implement map_shadow_stack() syscall Deepak Gupta
2025-04-07 4:50 ` Zong Li
2025-04-09 14:19 ` Deepak Gupta
2025-04-10 9:56 ` Radim Krčmář
2025-04-24 3:16 ` Deepak Gupta
2025-04-24 12:51 ` Radim Krčmář
2025-03-14 21:39 ` [PATCH v12 11/28] riscv/shstk: If needed allocate a new shadow stack on clone Deepak Gupta
2025-04-08 10:51 ` Alexandre Ghiti
2025-04-09 14:31 ` Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 12/28] riscv: Implements arch agnostic shadow stack prctls Deepak Gupta
2025-03-17 1:29 ` Zong Li
2025-04-10 9:45 ` Radim Krčmář
2025-04-24 4:44 ` Deepak Gupta
2025-04-24 13:36 ` Radim Krčmář
2025-04-24 18:16 ` Deepak Gupta
2025-04-25 11:42 ` Radim Krčmář
2025-04-25 16:39 ` Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 13/28] prctl: arch-agnostic prctl for indirect branch tracking Deepak Gupta
2025-03-17 1:29 ` Zong Li
2025-04-09 8:03 ` Alexandre Ghiti
2025-04-09 14:26 ` Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 14/28] riscv: Implements arch agnostic indirect branch tracking prctls Deepak Gupta
2025-03-17 1:29 ` Zong Li
2025-03-14 21:39 ` [PATCH v12 15/28] riscv/traps: Introduce software check exception Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 16/28] riscv: signal: abstract header saving for setup_sigcontext Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 17/28] riscv/signal: save and restore of shadow stack for signal Deepak Gupta
2025-04-10 8:49 ` Radim Krčmář
2025-03-14 21:39 ` [PATCH v12 18/28] riscv/kernel: update __show_regs to print shadow stack register Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 19/28] riscv/ptrace: riscv cfi status and state via ptrace and in core files Deepak Gupta
2025-03-20 22:24 ` Radim Krčmář
2025-03-20 23:09 ` Deepak Gupta
2025-03-21 7:22 ` Radim Krčmář
2025-03-14 21:39 ` [PATCH v12 20/28] riscv/hwprobe: zicfilp / zicfiss enumeration in hwprobe Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 21/28] riscv: Add Firmware Feature SBI extensions definitions Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 22/28] riscv: enable kernel access to shadow stack memory via FWFT sbi call Deepak Gupta
2025-03-20 22:10 ` Radim Krčmář
2025-03-20 22:42 ` Deepak Gupta
2025-03-21 7:35 ` Radim Krčmář
2025-03-14 21:39 ` [PATCH v12 23/28] riscv: kernel command line option to opt out of user cfi Deepak Gupta
2025-03-20 21:35 ` Radim Krčmář
2025-03-20 22:31 ` Deepak Gupta
2025-03-21 7:31 ` Radim Krčmář
2025-03-14 21:39 ` [PATCH v12 24/28] arch/riscv: compile vdso with landing pad Deepak Gupta
2025-04-08 12:45 ` Alexandre Ghiti
2025-04-09 14:28 ` Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 25/28] riscv: create a config for shadow stack and landing pad instr support Deepak Gupta
2025-03-20 21:25 ` Radim Krčmář
2025-03-20 22:29 ` Deepak Gupta
2025-03-21 7:51 ` Radim Krčmář
2025-03-14 21:39 ` [PATCH v12 26/28] riscv: Documentation for landing pad / indirect branch tracking Deepak Gupta
2025-04-08 8:36 ` Alexandre Ghiti
2025-03-14 21:39 ` [PATCH v12 27/28] riscv: Documentation for shadow stack on riscv Deepak Gupta
2025-04-08 8:48 ` Alexandre Ghiti
2025-04-10 5:24 ` Deepak Gupta
2025-03-14 21:39 ` [PATCH v12 28/28] kselftest/riscv: kselftest for user mode cfi Deepak Gupta
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