From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D748A2FDC5D; Wed, 29 Oct 2025 14:49:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761749347; cv=none; b=jzGBiDs4CJYsnGmHG0a9eMBjO+vAg9A8tfI8Rb7WDw1lVuVBj/XAZ2U3eBazDglORs8Cs2iSowBISCyy60prMdfVRLz/a02p4Lm5oEgLlN+Ozn1DuVIA03T7CwR+eFRKAEU3swZily9tJQfSjR3SmAq6kO8QFioWGeS2u7cAHf0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761749347; c=relaxed/simple; bh=HxTqJgI/0X/CEmspyZav8h3FXPWX3qB1qsKFzsoN4as=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=JYu099VPX9kg+ssE1FryC8Ij4MEKVQ3MMQKmk2jZMqQQk+18WfXRWH2y/XrUbpbvEf6N0FFYtwcbnPLFdBw9QuCqD4cU+WTrS5fai+uzxA6EUoq55GrNLvZkSvleVWQawSJyG1wQk+CsHB6GSQWfMqgm7+VL1Kf6Z2bIwfg0n38= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tlja5Mq4; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tlja5Mq4" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CA588C4CEF7; Wed, 29 Oct 2025 14:49:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761749346; bh=HxTqJgI/0X/CEmspyZav8h3FXPWX3qB1qsKFzsoN4as=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=tlja5Mq4eRWp697QA/xQ+7a9KJbcnrMdob9cxsXt9OIQA755+bFzbNzRv16bZ4K7i B9LDftZXKO7gStpMqGdXCVrWsVQ+ROKQ4K+QvkxPz38VTj++u90ce6yRHNCsPSi5pD v/JhE3LMKbYoWFWsQEzSVXb3Hm7XB2z8+8xOj7ZC7Xvnlx4rEDqU8ejlyTgLe/T9R2 3vUJArOhgOLb46RZqe+pCWQx7olKyL6EJb+OqaocNuhbMh3d/KGFm/ek9z7wlrO99H rF7V3yVMeDSwqgzEw1be+gsJR70/J/KwRrqpNcrj62az9WVQF5F5bIT1qWPQ84EK24 yw1IH2IxbPQpw== Date: Wed, 29 Oct 2025 15:49:03 +0100 From: Frederic Weisbecker To: Valentin Schneider Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org, rcu@vger.kernel.org, x86@kernel.org, linux-arm-kernel@lists.infradead.org, loongarch@lists.linux.dev, linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org, linux-trace-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Andy Lutomirski , Peter Zijlstra , Arnaldo Carvalho de Melo , Josh Poimboeuf , Paolo Bonzini , Arnd Bergmann , "Paul E. McKenney" , Jason Baron , Steven Rostedt , Ard Biesheuvel , Sami Tolvanen , "David S. Miller" , Neeraj Upadhyay , Joel Fernandes , Josh Triplett , Boqun Feng , Uladzislau Rezki , Mathieu Desnoyers , Mel Gorman , Andrew Morton , Masahiro Yamada , Han Shen , Rik van Riel , Jann Horn , Dan Carpenter , Oleg Nesterov , Juri Lelli , Clark Williams , Yair Podemsky , Marcelo Tosatti , Daniel Wagner , Petr Tesarik Subject: Re: [RFC PATCH v6 27/29] x86/mm/pti: Implement a TLB flush immediately after a switch to kernel CR3 Message-ID: References: <20251010153839.151763-1-vschneid@redhat.com> <20251010153839.151763-28-vschneid@redhat.com> Precedence: bulk X-Mailing-List: linux-arch@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Le Wed, Oct 29, 2025 at 03:13:59PM +0100, Valentin Schneider a écrit : > On 29/10/25 11:31, Frederic Weisbecker wrote: > > Le Wed, Oct 29, 2025 at 11:16:23AM +0100, Valentin Schneider a écrit : > >> On 28/10/25 16:59, Frederic Weisbecker wrote: > >> > Le Fri, Oct 10, 2025 at 05:38:37PM +0200, Valentin Schneider a écrit : > >> >> @@ -171,8 +172,27 @@ For 32-bit we have the following conventions - kernel is built with > >> >> andq $(~PTI_USER_PGTABLE_AND_PCID_MASK), \reg > >> >> .endm > >> >> > >> >> -.macro COALESCE_TLBI > >> >> +.macro COALESCE_TLBI scratch_reg:req > >> >> #ifdef CONFIG_COALESCE_TLBI > >> >> + /* No point in doing this for housekeeping CPUs */ > >> >> + movslq PER_CPU_VAR(cpu_number), \scratch_reg > >> >> + bt \scratch_reg, tick_nohz_full_mask(%rip) > >> >> + jnc .Lend_tlbi_\@ > >> > > >> > I assume it's not possible to have a static call/branch to > >> > take care of all this ? > >> > > >> > >> I think technically yes, but that would have to be a per-cpu patchable > >> location, which would mean something like each CPU having its own copy of > >> that text page... Unless there's some existing way to statically optimize > >> > >> if (cpumask_test_cpu(smp_processor_id(), mask)) > >> > >> where @mask is a boot-time constant (i.e. the nohz_full mask). > > > > Or just check housekeeping_overriden static key before everything. This one is > > enabled only if either nohz_full, isolcpus or cpuset isolated partition (well, > > it's on the way for the last one) are running, but those are all niche, which > > means you spare 99.999% kernel usecases. > > > > Oh right, if NOHZ_FULL is actually in use. > > Yeah that housekeeping key could do since, at least for the cmdline > approach, it's set during start_kernel(). I need to have a think about the > runtime cpuset case. You can ignore the runtime thing and simply check the static key before reading the housekeeping mask. For now nohz_full is only enabled by cmdline. > Given we have ALTERNATIVE's in there I assume something like a > boot-time-driven static key could do, but I haven't found out yet if and > how that can be shoved in an ASM file. Right, I thought I had seen static keys in ASM already but I can't find it anymore. arch/x86/include/asm/jump_label.h is full of reusable magic though. Thanks. -- Frederic Weisbecker SUSE Labs