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[103.168.172.200]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8c0970f5fe5sm2390443685a.26.2025.12.29.04.27.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Dec 2025 04:27:11 -0800 (PST) Received: from phl-compute-02.internal (phl-compute-02.internal [10.202.2.42]) by mailfauth.phl.internal (Postfix) with ESMTP id AD04DF4006C; Mon, 29 Dec 2025 07:27:10 -0500 (EST) Received: from phl-frontend-04 ([10.202.2.163]) by phl-compute-02.internal (MEProxy); Mon, 29 Dec 2025 07:27:10 -0500 X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeefgedrtddtgdejjedugecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpuffrtefokffrpgfnqfghnecuuegr ihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjug hrpeffhffvvefukfhfgggtuggjsehttdertddttddvnecuhfhrohhmpeeuohhquhhnucfh vghnghcuoegsohhquhhnrdhfvghnghesghhmrghilhdrtghomheqnecuggftrfgrthhtvg hrnhephedugfduffffteeutddvheeuveelvdfhleelieevtdeguefhgeeuveeiudffiedv necuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrhhomhepsghoqh hunhdomhgvshhmthhprghuthhhphgvrhhsohhnrghlihhthidqieelvdeghedtieegqddu jeejkeehheehvddqsghoqhhunhdrfhgvnhhgpeepghhmrghilhdrtghomhesfhhigihmvg drnhgrmhgvpdhnsggprhgtphhtthhopedufedpmhhouggvpehsmhhtphhouhhtpdhrtghp thhtohepfhhujhhithgrrdhtohhmohhnohhrihesghhmrghilhdrtghomhdprhgtphhtth hopehojhgvuggrsehkvghrnhgvlhdrohhrghdprhgtphhtthhopegrrdhhihhnuggsohhr gheskhgvrhhnvghlrdhorhhgpdhrtghpthhtoheprghlihgtvghrhihhlhesghhoohhglh gvrdgtohhmpdhrtghpthhtohepsghjohhrnhefpghghhesphhrohhtohhnmhgrihhlrdgt ohhmpdhrtghpthhtohepuggrkhhrsehkvghrnhgvlhdrohhrghdprhgtphhtthhopehgrg hrhiesghgrrhihghhuohdrnhgvthdprhgtphhtthhopehlohhsshhinheskhgvrhhnvghl rdhorhhgpdhrtghpthhtohepthhmghhrohhsshesuhhmihgthhdrvgguuh X-ME-Proxy: Feedback-ID: iad51458e:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 29 Dec 2025 07:27:09 -0500 (EST) Date: Mon, 29 Dec 2025 20:27:01 +0800 From: Boqun Feng To: FUJITA Tomonori Cc: ojeda@kernel.org, a.hindborg@kernel.org, aliceryhl@google.com, bjorn3_gh@protonmail.com, dakr@kernel.org, gary@garyguo.net, lossin@kernel.org, tmgross@umich.edu, acourbot@nvidia.com, rust-for-linux@vger.kernel.org, linux-arch@vger.kernel.org Subject: Re: [PATCH v1 3/3] rust: sync: atomic: Add i8/i16 xchg and cmpxchg support Message-ID: References: <20251228120546.1602275-1-fujita.tomonori@gmail.com> <20251228120546.1602275-4-fujita.tomonori@gmail.com> Precedence: bulk X-Mailing-List: linux-arch@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251228120546.1602275-4-fujita.tomonori@gmail.com> On Sun, Dec 28, 2025 at 09:05:46PM +0900, FUJITA Tomonori wrote: > Add atomic xchg and cmpxchg operation support for i8 and i16 types > with tests. > I think we also needs the following, otherwise architectures may accidentally enable Rust but don't have the correct atomic implementation for i8 and i16. diff --git a/rust/kernel/sync/atomic/predefine.rs b/rust/kernel/sync/atomic/predefine.rs index 248d26555ccf..a4e5bbd45eb2 100644 --- a/rust/kernel/sync/atomic/predefine.rs +++ b/rust/kernel/sync/atomic/predefine.rs @@ -5,14 +5,22 @@ use crate::static_assert; use core::mem::{align_of, size_of}; +// The current helpers of load/store uses `{WRITE,READ}_ONCE()` hence the atomicity is only +// guaranteed against read-modify-write operations if the architecture supports native atomic RmW. +// // SAFETY: `i8` has the same size and alignment with itself, and is round-trip transmutable to // itself. +#[cfg(CONFIG_ARCH_SUPPORTS_ATOMIC_RMW)] unsafe impl super::AtomicType for i8 { type Repr = i8; } +// The current helpers of load/store uses `{WRITE,READ}_ONCE()` hence the atomicity is only +// guaranteed against read-modify-write operations if the architecture supports native atomic RmW. +// // SAFETY: `i16` has the same size and alignment with itself, and is round-trip transmutable to // itself. +#[cfg(CONFIG_ARCH_SUPPORTS_ATOMIC_RMW)] unsafe impl super::AtomicType for i16 { type Repr = i16; } I can fold it into your patch if that works. Regards, Boqun > Signed-off-by: FUJITA Tomonori > --- > rust/kernel/sync/atomic/internal.rs | 2 +- > rust/kernel/sync/atomic/predefine.rs | 4 ++-- > 2 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/rust/kernel/sync/atomic/internal.rs b/rust/kernel/sync/atomic/internal.rs > index 1b2a7933bc14..55a80e22a7a0 100644 > --- a/rust/kernel/sync/atomic/internal.rs > +++ b/rust/kernel/sync/atomic/internal.rs > @@ -274,7 +274,7 @@ fn set[release](a: &AtomicRepr, v: Self) { > ); > > declare_and_impl_atomic_methods!( > - [ i32 => atomic, i64 => atomic64 ] > + [ i8 => atomic_i8, i16 => atomic_i16, i32 => atomic, i64 => atomic64 ] > /// Exchange and compare-and-exchange atomic operations > pub trait AtomicExchangeOps { > /// Atomic exchange. > diff --git a/rust/kernel/sync/atomic/predefine.rs b/rust/kernel/sync/atomic/predefine.rs > index 51e9df0cf56e..248d26555ccf 100644 > --- a/rust/kernel/sync/atomic/predefine.rs > +++ b/rust/kernel/sync/atomic/predefine.rs > @@ -149,7 +149,7 @@ fn atomic_acquire_release_tests() { > > #[test] > fn atomic_xchg_tests() { > - for_each_type!(42 in [i32, i64, u32, u64, isize, usize] |v| { > + for_each_type!(42 in [i8, i16, i32, i64, u32, u64, isize, usize] |v| { > let x = Atomic::new(v); > > let old = v; > @@ -162,7 +162,7 @@ fn atomic_xchg_tests() { > > #[test] > fn atomic_cmpxchg_tests() { > - for_each_type!(42 in [i32, i64, u32, u64, isize, usize] |v| { > + for_each_type!(42 in [i8, i16, i32, i64, u32, u64, isize, usize] |v| { > let x = Atomic::new(v); > > let old = v; > -- > 2.43.0 >