Re: [PATCH V4] riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup

Guo Ren
2026-04-13T08:17:02Z

On Mon, Apr 13, 2026 at 2:18 PM Arnd Bergmann <arnd@arndb.de> wrote:
>
> On Sun, Apr 12, 2026, at 16:31, guoren@kernel.org wrote:
> > arch/riscv/Kconfig.errata | 17 ++++++++++
> > arch/riscv/errata/thead/errata.c | 20 ++++++++++++
> > arch/riscv/include/asm/errata_list_vendors.h | 3 +-
> > arch/riscv/include/asm/rwonce.h | 34 ++++++++++++++++++++
> > include/asm-generic/rwonce.h | 2 ++
>
> For asm-generic:
>
> Acked-by: Arnd Bergmann <arnd@arndb.de>
>
> > +static bool errata_probe_write_once(unsigned int stage,
> > + unsigned long arch_id, unsigned long impid)
> > +{
> > + if (!IS_ENABLED(CONFIG_ERRATA_THEAD_WRITE_ONCE))
> > + return false;
> > +
> > + /* target-c9xx cores report arch_id and impid as 0 */
> > + if (arch_id != 0 || impid != 0)
> > + return false;
> > +
> > + if (stage == RISCV_ALTERNATIVES_BOOT ||
> > + stage == RISCV_ALTERNATIVES_MODULE)
> > + return true;
>
> Question: Are the affected cores the only ones that report
> arch_id==impid==0? If there are other known implementations
> that get the extra barrier but don't need it here, that
> should probably be mentioned in the Kconfig text and
> the code comment.

Thank you for your question.

So far, we have only observed this issue on the SG2042 chip. However,
in theory, it affects all older c9xx cores that report arch_id == 0
and impid == 0.

Since these early versions are relatively few in number and share the
same signature (arch_id = 0 && impid = 0), we decided to apply the
workaround to all cores that match this condition to ensure complete
coverage and avoid missing any affected silicon.

--
Best Regards
GUO Ren