* [PATCH V7 0/2] irqchip: add C-SKY SMP interrupt controller
@ 2018-09-18 13:49 Guo Ren
2018-09-18 13:49 ` Guo Ren
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Guo Ren @ 2018-09-18 13:49 UTC (permalink / raw)
To: tglx, jason, marc.zyngier, robh+dt, mark.rutland, arnd, robh, sfr
Cc: linux-kernel, devicetree, linux-arch, c-sky_gcc_upstream,
gnu-csky, green.hu, Guo Ren
Guo Ren (2):
irqchip: add C-SKY SMP interrupt controller
dt-bindings: interrupt-controller: C-SKY SMP intc
.../bindings/interrupt-controller/csky,mpintc.txt | 40 +++++
drivers/irqchip/Kconfig | 16 ++
drivers/irqchip/Makefile | 2 +
drivers/irqchip/irq-csky-mpintc.c | 196 +++++++++++++++++++++
4 files changed, 254 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt
create mode 100644 drivers/irqchip/irq-csky-mpintc.c
--
2.7.4
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH V7 0/2] irqchip: add C-SKY SMP interrupt controller 2018-09-18 13:49 [PATCH V7 0/2] irqchip: add C-SKY SMP interrupt controller Guo Ren @ 2018-09-18 13:49 ` Guo Ren 2018-09-18 13:49 ` [PATCH V7 1/2] " Guo Ren 2018-09-18 13:49 ` [PATCH V7 2/2] dt-bindings: interrupt-controller: C-SKY SMP intc Guo Ren 2 siblings, 0 replies; 6+ messages in thread From: Guo Ren @ 2018-09-18 13:49 UTC (permalink / raw) To: tglx, jason, marc.zyngier, robh+dt, mark.rutland, arnd, robh, sfr Cc: linux-kernel, devicetree, linux-arch, c-sky_gcc_upstream, gnu-csky, green.hu, Guo Ren Guo Ren (2): irqchip: add C-SKY SMP interrupt controller dt-bindings: interrupt-controller: C-SKY SMP intc .../bindings/interrupt-controller/csky,mpintc.txt | 40 +++++ drivers/irqchip/Kconfig | 16 ++ drivers/irqchip/Makefile | 2 + drivers/irqchip/irq-csky-mpintc.c | 196 +++++++++++++++++++++ 4 files changed, 254 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt create mode 100644 drivers/irqchip/irq-csky-mpintc.c -- 2.7.4 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH V7 1/2] irqchip: add C-SKY SMP interrupt controller 2018-09-18 13:49 [PATCH V7 0/2] irqchip: add C-SKY SMP interrupt controller Guo Ren 2018-09-18 13:49 ` Guo Ren @ 2018-09-18 13:49 ` Guo Ren 2018-09-18 13:49 ` Guo Ren 2018-09-18 13:49 ` [PATCH V7 2/2] dt-bindings: interrupt-controller: C-SKY SMP intc Guo Ren 2 siblings, 1 reply; 6+ messages in thread From: Guo Ren @ 2018-09-18 13:49 UTC (permalink / raw) To: tglx, jason, marc.zyngier, robh+dt, mark.rutland, arnd, robh, sfr Cc: linux-kernel, devicetree, linux-arch, c-sky_gcc_upstream, gnu-csky, green.hu, Guo Ren - irq-csky-mpintc is C-SKY smp system interrupt controller and it could support 16 soft irqs, 16 private irqs, and 992 max common irqs. Changelog: - remove irq_set_default_host() and use set_ipi_irq_mapping() - change name with upstream feed-back - change irq map, reserve soft_irq & private_irq space - add License and Copyright - support set_affinity for irq balance in SMP Signed-off-by: Guo Ren <ren_guo@c-sky.com> --- drivers/irqchip/Kconfig | 16 ++++ drivers/irqchip/Makefile | 2 + drivers/irqchip/irq-csky-mpintc.c | 196 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 214 insertions(+) create mode 100644 drivers/irqchip/irq-csky-mpintc.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 383e7b7..bf12549 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -371,6 +371,22 @@ config QCOM_PDC Power Domain Controller driver to manage and configure wakeup IRQs for Qualcomm Technologies Inc (QTI) mobile chips. +config CSKY_MPINTC + bool "C-SKY Multi Processor Interrupt Controller" + depends on CSKY + help + Say yes here to enable C-SKY SMP interrupt controller driver used + for C-SKY SMP system. In fact it's not mmio map and it use ld/st + to visit the controller's register inside CPU. + +config CSKY_APB_INTC + bool "C-SKY APB Interrupt Controller" + depends on CSKY + help + Say yes here to enable C-SKY APB interrupt controller driver used + by C-SKY single core SOC system. It use mmio map apb-bus to visit + the controller's register. + endmenu config SIFIVE_PLIC diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index fbd1ec8..72eaf53 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -87,4 +87,6 @@ obj-$(CONFIG_MESON_IRQ_GPIO) += irq-meson-gpio.o obj-$(CONFIG_GOLDFISH_PIC) += irq-goldfish-pic.o obj-$(CONFIG_NDS32) += irq-ativic32.o obj-$(CONFIG_QCOM_PDC) += qcom-pdc.o +obj-$(CONFIG_CSKY_MPINTC) += irq-csky-mpintc.o +obj-$(CONFIG_CSKY_APB_INTC) += irq-csky-apb-intc.o obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o diff --git a/drivers/irqchip/irq-csky-mpintc.c b/drivers/irqchip/irq-csky-mpintc.c new file mode 100644 index 0000000..dfe976d --- /dev/null +++ b/drivers/irqchip/irq-csky-mpintc.c @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/module.h> +#include <linux/irqdomain.h> +#include <linux/irqchip.h> +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <asm/irq.h> +#include <asm/io.h> +#include <asm/traps.h> +#include <asm/reg_ops.h> +#include <asm/smp.h> + +static struct irq_domain *root_domain; +static void __iomem *INTCG_base; +static void __iomem *INTCL_base; + +#define COMM_IRQ_BASE 32 + +#define INTCG_SIZE 0x8000 +#define INTCL_SIZE 0x1000 +#define INTC_SIZE INTCL_SIZE*nr_cpu_ids + INTCG_SIZE + +#define INTCG_ICTLR 0x0 +#define INTCG_CICFGR 0x100 +#define INTCG_CIDSTR 0x1000 + +#define INTCL_PICTLR 0x0 +#define INTCL_SIGR 0x60 +#define INTCL_HPPIR 0x68 +#define INTCL_RDYIR 0x6c +#define INTCL_SENR 0xa0 +#define INTCL_CENR 0xa4 +#define INTCL_CACR 0xb4 + +#define INTC_IRQS 256 + +static DEFINE_PER_CPU(void __iomem *, intcl_reg); + +static void csky_mpintc_handler(struct pt_regs *regs) +{ + void __iomem *reg_base = this_cpu_read(intcl_reg); + + do { + handle_domain_irq(root_domain, + readl_relaxed(reg_base + INTCL_RDYIR), + regs); + } while (readl_relaxed(reg_base + INTCL_HPPIR) & BIT(31)); +} + +static void csky_mpintc_enable(struct irq_data *d) +{ + void __iomem *reg_base = this_cpu_read(intcl_reg); + + writel_relaxed(d->hwirq, reg_base + INTCL_SENR); +} + +static void csky_mpintc_disable(struct irq_data *d) +{ + void __iomem *reg_base = this_cpu_read(intcl_reg); + + writel_relaxed(d->hwirq, reg_base + INTCL_CENR); +} + +static void csky_mpintc_eoi(struct irq_data *d) +{ + void __iomem *reg_base = this_cpu_read(intcl_reg); + + writel_relaxed(d->hwirq, reg_base + INTCL_CACR); +} + +#ifdef CONFIG_SMP +static int csky_irq_set_affinity(struct irq_data *d, + const struct cpumask *mask_val, + bool force) +{ + unsigned int cpu; + unsigned int offset = 4 * (d->hwirq - COMM_IRQ_BASE); + + if (!force) + cpu = cpumask_any_and(mask_val, cpu_online_mask); + else + cpu = cpumask_first(mask_val); + + if (cpu >= nr_cpu_ids) + return -EINVAL; + + /* Enable interrupt destination */ + cpu |= BIT(31); + + writel_relaxed(cpu, INTCG_base + INTCG_CIDSTR + offset); + + irq_data_update_effective_affinity(d, cpumask_of(cpu)); + + return IRQ_SET_MASK_OK_DONE; +} +#endif + +static struct irq_chip csky_irq_chip = { + .name = "C-SKY SMP Intc", + .irq_eoi = csky_mpintc_eoi, + .irq_enable = csky_mpintc_enable, + .irq_disable = csky_mpintc_disable, +#ifdef CONFIG_SMP + .irq_set_affinity = csky_irq_set_affinity, +#endif +}; + +static int csky_irqdomain_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hwirq) +{ + if(hwirq < COMM_IRQ_BASE) { + irq_set_percpu_devid(irq); + irq_set_chip_and_handler(irq, &csky_irq_chip, handle_percpu_irq); + } else { + irq_set_chip_and_handler(irq, &csky_irq_chip, handle_fasteoi_irq); + } + + return 0; +} + +static const struct irq_domain_ops csky_irqdomain_ops = { + .map = csky_irqdomain_map, + .xlate = irq_domain_xlate_onecell, +}; + +#ifdef CONFIG_SMP +static void csky_mpintc_send_ipi(const unsigned long *mask, unsigned long irq) +{ + void __iomem *reg_base = this_cpu_read(intcl_reg); + + /* + * INTCL_SIGR[3:0] INTID + * INTCL_SIGR[8:15] CPUMASK + */ + writel_relaxed((*mask) << 8 | irq, reg_base + INTCL_SIGR); +} + +static int csky_mpintc_ipi_irq_mapping(void) +{ + return irq_create_mapping(root_domain, IPI_IRQ); +} +#endif + +/* C-SKY multi processor interrupt controller */ +static int __init +csky_mpintc_init(struct device_node *node, struct device_node *parent) +{ + unsigned int cpu, nr_irq; + int ret; + + if (parent) + return 0; + + ret = of_property_read_u32(node, "csky,num-irqs", &nr_irq); + if (ret < 0) + nr_irq = INTC_IRQS; + + if (INTCG_base == NULL) { + INTCG_base = ioremap(mfcr("cr<31, 14>"), INTC_SIZE); + if (INTCG_base == NULL) + return -EIO; + + INTCL_base = INTCG_base + INTCG_SIZE; + + writel_relaxed(BIT(0), INTCG_base + INTCG_ICTLR); + } + + root_domain = irq_domain_add_linear(node, nr_irq, &csky_irqdomain_ops, + NULL); + if (!root_domain) + return -ENXIO; + + /* for every cpu */ + for_each_present_cpu(cpu) { + per_cpu(intcl_reg, cpu) = INTCL_base + (INTCL_SIZE * cpu); + writel_relaxed(BIT(0), per_cpu(intcl_reg, cpu) + INTCL_PICTLR); + } + + set_handle_irq(&csky_mpintc_handler); + +#ifdef CONFIG_SMP + set_send_ipi(&csky_mpintc_send_ipi); + + set_ipi_irq_mapping(&csky_mpintc_ipi_irq_mapping); +#endif + + return 0; +} +IRQCHIP_DECLARE(csky_mpintc, "csky,mpintc", csky_mpintc_init); + -- 2.7.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH V7 1/2] irqchip: add C-SKY SMP interrupt controller 2018-09-18 13:49 ` [PATCH V7 1/2] " Guo Ren @ 2018-09-18 13:49 ` Guo Ren 0 siblings, 0 replies; 6+ messages in thread From: Guo Ren @ 2018-09-18 13:49 UTC (permalink / raw) To: tglx, jason, marc.zyngier, robh+dt, mark.rutland, arnd, robh, sfr Cc: linux-kernel, devicetree, linux-arch, c-sky_gcc_upstream, gnu-csky, green.hu, Guo Ren - irq-csky-mpintc is C-SKY smp system interrupt controller and it could support 16 soft irqs, 16 private irqs, and 992 max common irqs. Changelog: - remove irq_set_default_host() and use set_ipi_irq_mapping() - change name with upstream feed-back - change irq map, reserve soft_irq & private_irq space - add License and Copyright - support set_affinity for irq balance in SMP Signed-off-by: Guo Ren <ren_guo@c-sky.com> --- drivers/irqchip/Kconfig | 16 ++++ drivers/irqchip/Makefile | 2 + drivers/irqchip/irq-csky-mpintc.c | 196 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 214 insertions(+) create mode 100644 drivers/irqchip/irq-csky-mpintc.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 383e7b7..bf12549 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -371,6 +371,22 @@ config QCOM_PDC Power Domain Controller driver to manage and configure wakeup IRQs for Qualcomm Technologies Inc (QTI) mobile chips. +config CSKY_MPINTC + bool "C-SKY Multi Processor Interrupt Controller" + depends on CSKY + help + Say yes here to enable C-SKY SMP interrupt controller driver used + for C-SKY SMP system. In fact it's not mmio map and it use ld/st + to visit the controller's register inside CPU. + +config CSKY_APB_INTC + bool "C-SKY APB Interrupt Controller" + depends on CSKY + help + Say yes here to enable C-SKY APB interrupt controller driver used + by C-SKY single core SOC system. It use mmio map apb-bus to visit + the controller's register. + endmenu config SIFIVE_PLIC diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index fbd1ec8..72eaf53 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -87,4 +87,6 @@ obj-$(CONFIG_MESON_IRQ_GPIO) += irq-meson-gpio.o obj-$(CONFIG_GOLDFISH_PIC) += irq-goldfish-pic.o obj-$(CONFIG_NDS32) += irq-ativic32.o obj-$(CONFIG_QCOM_PDC) += qcom-pdc.o +obj-$(CONFIG_CSKY_MPINTC) += irq-csky-mpintc.o +obj-$(CONFIG_CSKY_APB_INTC) += irq-csky-apb-intc.o obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o diff --git a/drivers/irqchip/irq-csky-mpintc.c b/drivers/irqchip/irq-csky-mpintc.c new file mode 100644 index 0000000..dfe976d --- /dev/null +++ b/drivers/irqchip/irq-csky-mpintc.c @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/module.h> +#include <linux/irqdomain.h> +#include <linux/irqchip.h> +#include <linux/irq.h> +#include <linux/interrupt.h> +#include <asm/irq.h> +#include <asm/io.h> +#include <asm/traps.h> +#include <asm/reg_ops.h> +#include <asm/smp.h> + +static struct irq_domain *root_domain; +static void __iomem *INTCG_base; +static void __iomem *INTCL_base; + +#define COMM_IRQ_BASE 32 + +#define INTCG_SIZE 0x8000 +#define INTCL_SIZE 0x1000 +#define INTC_SIZE INTCL_SIZE*nr_cpu_ids + INTCG_SIZE + +#define INTCG_ICTLR 0x0 +#define INTCG_CICFGR 0x100 +#define INTCG_CIDSTR 0x1000 + +#define INTCL_PICTLR 0x0 +#define INTCL_SIGR 0x60 +#define INTCL_HPPIR 0x68 +#define INTCL_RDYIR 0x6c +#define INTCL_SENR 0xa0 +#define INTCL_CENR 0xa4 +#define INTCL_CACR 0xb4 + +#define INTC_IRQS 256 + +static DEFINE_PER_CPU(void __iomem *, intcl_reg); + +static void csky_mpintc_handler(struct pt_regs *regs) +{ + void __iomem *reg_base = this_cpu_read(intcl_reg); + + do { + handle_domain_irq(root_domain, + readl_relaxed(reg_base + INTCL_RDYIR), + regs); + } while (readl_relaxed(reg_base + INTCL_HPPIR) & BIT(31)); +} + +static void csky_mpintc_enable(struct irq_data *d) +{ + void __iomem *reg_base = this_cpu_read(intcl_reg); + + writel_relaxed(d->hwirq, reg_base + INTCL_SENR); +} + +static void csky_mpintc_disable(struct irq_data *d) +{ + void __iomem *reg_base = this_cpu_read(intcl_reg); + + writel_relaxed(d->hwirq, reg_base + INTCL_CENR); +} + +static void csky_mpintc_eoi(struct irq_data *d) +{ + void __iomem *reg_base = this_cpu_read(intcl_reg); + + writel_relaxed(d->hwirq, reg_base + INTCL_CACR); +} + +#ifdef CONFIG_SMP +static int csky_irq_set_affinity(struct irq_data *d, + const struct cpumask *mask_val, + bool force) +{ + unsigned int cpu; + unsigned int offset = 4 * (d->hwirq - COMM_IRQ_BASE); + + if (!force) + cpu = cpumask_any_and(mask_val, cpu_online_mask); + else + cpu = cpumask_first(mask_val); + + if (cpu >= nr_cpu_ids) + return -EINVAL; + + /* Enable interrupt destination */ + cpu |= BIT(31); + + writel_relaxed(cpu, INTCG_base + INTCG_CIDSTR + offset); + + irq_data_update_effective_affinity(d, cpumask_of(cpu)); + + return IRQ_SET_MASK_OK_DONE; +} +#endif + +static struct irq_chip csky_irq_chip = { + .name = "C-SKY SMP Intc", + .irq_eoi = csky_mpintc_eoi, + .irq_enable = csky_mpintc_enable, + .irq_disable = csky_mpintc_disable, +#ifdef CONFIG_SMP + .irq_set_affinity = csky_irq_set_affinity, +#endif +}; + +static int csky_irqdomain_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hwirq) +{ + if(hwirq < COMM_IRQ_BASE) { + irq_set_percpu_devid(irq); + irq_set_chip_and_handler(irq, &csky_irq_chip, handle_percpu_irq); + } else { + irq_set_chip_and_handler(irq, &csky_irq_chip, handle_fasteoi_irq); + } + + return 0; +} + +static const struct irq_domain_ops csky_irqdomain_ops = { + .map = csky_irqdomain_map, + .xlate = irq_domain_xlate_onecell, +}; + +#ifdef CONFIG_SMP +static void csky_mpintc_send_ipi(const unsigned long *mask, unsigned long irq) +{ + void __iomem *reg_base = this_cpu_read(intcl_reg); + + /* + * INTCL_SIGR[3:0] INTID + * INTCL_SIGR[8:15] CPUMASK + */ + writel_relaxed((*mask) << 8 | irq, reg_base + INTCL_SIGR); +} + +static int csky_mpintc_ipi_irq_mapping(void) +{ + return irq_create_mapping(root_domain, IPI_IRQ); +} +#endif + +/* C-SKY multi processor interrupt controller */ +static int __init +csky_mpintc_init(struct device_node *node, struct device_node *parent) +{ + unsigned int cpu, nr_irq; + int ret; + + if (parent) + return 0; + + ret = of_property_read_u32(node, "csky,num-irqs", &nr_irq); + if (ret < 0) + nr_irq = INTC_IRQS; + + if (INTCG_base == NULL) { + INTCG_base = ioremap(mfcr("cr<31, 14>"), INTC_SIZE); + if (INTCG_base == NULL) + return -EIO; + + INTCL_base = INTCG_base + INTCG_SIZE; + + writel_relaxed(BIT(0), INTCG_base + INTCG_ICTLR); + } + + root_domain = irq_domain_add_linear(node, nr_irq, &csky_irqdomain_ops, + NULL); + if (!root_domain) + return -ENXIO; + + /* for every cpu */ + for_each_present_cpu(cpu) { + per_cpu(intcl_reg, cpu) = INTCL_base + (INTCL_SIZE * cpu); + writel_relaxed(BIT(0), per_cpu(intcl_reg, cpu) + INTCL_PICTLR); + } + + set_handle_irq(&csky_mpintc_handler); + +#ifdef CONFIG_SMP + set_send_ipi(&csky_mpintc_send_ipi); + + set_ipi_irq_mapping(&csky_mpintc_ipi_irq_mapping); +#endif + + return 0; +} +IRQCHIP_DECLARE(csky_mpintc, "csky,mpintc", csky_mpintc_init); + -- 2.7.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH V7 2/2] dt-bindings: interrupt-controller: C-SKY SMP intc 2018-09-18 13:49 [PATCH V7 0/2] irqchip: add C-SKY SMP interrupt controller Guo Ren 2018-09-18 13:49 ` Guo Ren 2018-09-18 13:49 ` [PATCH V7 1/2] " Guo Ren @ 2018-09-18 13:49 ` Guo Ren 2018-09-18 13:49 ` Guo Ren 2 siblings, 1 reply; 6+ messages in thread From: Guo Ren @ 2018-09-18 13:49 UTC (permalink / raw) To: tglx, jason, marc.zyngier, robh+dt, mark.rutland, arnd, robh, sfr Cc: linux-kernel, devicetree, linux-arch, c-sky_gcc_upstream, gnu-csky, green.hu, Guo Ren - Dt-bindings doc about C-SKY Multi-processors interrupt controller. Signed-off-by: Guo Ren <ren_guo@c-sky.com> --- .../bindings/interrupt-controller/csky,mpintc.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt b/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt new file mode 100644 index 0000000..49d1658 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt @@ -0,0 +1,40 @@ +=========================================== +C-SKY Multi-processors Interrupt Controller +=========================================== + +C-SKY Multi-processors Interrupt Controller is designed for ck807/ck810/ck860 +SMP soc, and it also could be used in non-SMP system. + +Interrupt number definition: + + 0-15 : software irq, and we use 15 as our IPI_IRQ. + 16-31 : private irq, and we use 16 as the co-processor timer. + 31-1024: common irq for soc ip. + +============================= +intc node bindings definition +============================= + + Description: Describes SMP interrupt controller + + PROPERTIES + + - compatible + Usage: required + Value type: <string> + Definition: must be "csky,mpintc" + - interrupt-cells + Usage: required + Value type: <u32> + Definition: must be <1> + - interrupt-controller: + Usage: required + +Examples: +--------- + + intc: interrupt-controller { + compatible = "csky,mpintc"; + #interrupt-cells = <1>; + interrupt-controller; + }; -- 2.7.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH V7 2/2] dt-bindings: interrupt-controller: C-SKY SMP intc 2018-09-18 13:49 ` [PATCH V7 2/2] dt-bindings: interrupt-controller: C-SKY SMP intc Guo Ren @ 2018-09-18 13:49 ` Guo Ren 0 siblings, 0 replies; 6+ messages in thread From: Guo Ren @ 2018-09-18 13:49 UTC (permalink / raw) To: tglx, jason, marc.zyngier, robh+dt, mark.rutland, arnd, robh, sfr Cc: linux-kernel, devicetree, linux-arch, c-sky_gcc_upstream, gnu-csky, green.hu, Guo Ren - Dt-bindings doc about C-SKY Multi-processors interrupt controller. Signed-off-by: Guo Ren <ren_guo@c-sky.com> --- .../bindings/interrupt-controller/csky,mpintc.txt | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt b/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt new file mode 100644 index 0000000..49d1658 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/csky,mpintc.txt @@ -0,0 +1,40 @@ +=========================================== +C-SKY Multi-processors Interrupt Controller +=========================================== + +C-SKY Multi-processors Interrupt Controller is designed for ck807/ck810/ck860 +SMP soc, and it also could be used in non-SMP system. + +Interrupt number definition: + + 0-15 : software irq, and we use 15 as our IPI_IRQ. + 16-31 : private irq, and we use 16 as the co-processor timer. + 31-1024: common irq for soc ip. + +============================= +intc node bindings definition +============================= + + Description: Describes SMP interrupt controller + + PROPERTIES + + - compatible + Usage: required + Value type: <string> + Definition: must be "csky,mpintc" + - interrupt-cells + Usage: required + Value type: <u32> + Definition: must be <1> + - interrupt-controller: + Usage: required + +Examples: +--------- + + intc: interrupt-controller { + compatible = "csky,mpintc"; + #interrupt-cells = <1>; + interrupt-controller; + }; -- 2.7.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-09-18 19:22 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2018-09-18 13:49 [PATCH V7 0/2] irqchip: add C-SKY SMP interrupt controller Guo Ren 2018-09-18 13:49 ` Guo Ren 2018-09-18 13:49 ` [PATCH V7 1/2] " Guo Ren 2018-09-18 13:49 ` Guo Ren 2018-09-18 13:49 ` [PATCH V7 2/2] dt-bindings: interrupt-controller: C-SKY SMP intc Guo Ren 2018-09-18 13:49 ` Guo Ren
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