From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dave Hansen Subject: Re: [RFC PATCH v3 12/24] x86/mm: Modify ptep_set_wrprotect and pmdp_set_wrprotect for _PAGE_DIRTY_SW Date: Thu, 30 Aug 2018 11:55:14 -0700 Message-ID: References: <20180830143904.3168-1-yu-cheng.yu@intel.com> <20180830143904.3168-13-yu-cheng.yu@intel.com> <079a55f2-4654-4adf-a6ef-6e480b594a2f@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Andy Lutomirski Cc: Jann Horn , yu-cheng.yu@intel.com, the arch/x86 maintainers , "H . Peter Anvin" , Thomas Gleixner , Ingo Molnar , kernel list , linux-doc@vger.kernel.org, Linux-MM , linux-arch , Linux API , Arnd Bergmann , Balbir Singh , Cyrill Gorcunov , Florian Weimer , hjl.tools@gmail.com, Jonathan Corbet , keescook@chromiun.org, Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra List-Id: linux-arch.vger.kernel.org On 08/30/2018 10:34 AM, Andy Lutomirski wrote: >> But, to keep B's TLB from picking up the entry, I think we can just make >> it !Present for a moment. No TLB can cache it, and I believe the same >> "don't set Dirty on a !Writable entry" logic also holds for !Present >> (modulo a weird erratum or two). > Can we get documentation? Pretty please? The accessed bit description in the SDM looks pretty good to me today: > Whenever the processor uses a paging-structure entry as part of > linear-address translation, it sets the accessed flag in that entry > (if it is not already set). If it's !Present, it can't used as part of a translation so can't be set. I think that covers the thing I was unsure about. But, Dirty is a bit, er, muddier, but mostly because it only gets set on leaf entries: > Whenever there is a write to a linear address, the processor sets the > dirty flag (if it is not already set) in the paging- structure entry > that identifies the final physical address for the linear address > (either a PTE or a paging-structure entry in which the PS flag is > 1). That little hunk will definitely need to get updated with something like: On processors enumerating support for CET, the processor will on set the dirty flag on paging structure entries in which the W flag is 1. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga18.intel.com ([134.134.136.126]:54642 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728020AbeH3W7Q (ORCPT ); Thu, 30 Aug 2018 18:59:16 -0400 Subject: Re: [RFC PATCH v3 12/24] x86/mm: Modify ptep_set_wrprotect and pmdp_set_wrprotect for _PAGE_DIRTY_SW References: <20180830143904.3168-1-yu-cheng.yu@intel.com> <20180830143904.3168-13-yu-cheng.yu@intel.com> <079a55f2-4654-4adf-a6ef-6e480b594a2f@linux.intel.com> From: Dave Hansen Message-ID: Date: Thu, 30 Aug 2018 11:55:14 -0700 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-arch-owner@vger.kernel.org List-ID: To: Andy Lutomirski Cc: Jann Horn , yu-cheng.yu@intel.com, the arch/x86 maintainers , "H . Peter Anvin" , Thomas Gleixner , Ingo Molnar , kernel list , linux-doc@vger.kernel.org, Linux-MM , linux-arch , Linux API , Arnd Bergmann , Balbir Singh , Cyrill Gorcunov , Florian Weimer , hjl.tools@gmail.com, Jonathan Corbet , keescook@chromiun.org, Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , ravi.v.shankar@intel.com, vedvyas.shanbhogue@intel.com Message-ID: <20180830185514.TiqynW7drJWPRjhvOLFzv8BV0GKRSV2ZvR2EL-bPEsU@z> On 08/30/2018 10:34 AM, Andy Lutomirski wrote: >> But, to keep B's TLB from picking up the entry, I think we can just make >> it !Present for a moment. No TLB can cache it, and I believe the same >> "don't set Dirty on a !Writable entry" logic also holds for !Present >> (modulo a weird erratum or two). > Can we get documentation? Pretty please? The accessed bit description in the SDM looks pretty good to me today: > Whenever the processor uses a paging-structure entry as part of > linear-address translation, it sets the accessed flag in that entry > (if it is not already set). If it's !Present, it can't used as part of a translation so can't be set. I think that covers the thing I was unsure about. But, Dirty is a bit, er, muddier, but mostly because it only gets set on leaf entries: > Whenever there is a write to a linear address, the processor sets the > dirty flag (if it is not already set) in the paging- structure entry > that identifies the final physical address for the linear address > (either a PTE or a paging-structure entry in which the PS flag is > 1). That little hunk will definitely need to get updated with something like: On processors enumerating support for CET, the processor will on set the dirty flag on paging structure entries in which the W flag is 1.