* [PATCH] Extend cache-l2x0 to support the 16-way PL310
@ 2010-04-30 19:13 Jason S. McMullan
2010-04-30 19:13 ` [PATCH] [arm l2x0] " Jason S. McMullan
2010-04-30 19:22 ` Jason S. McMullan
0 siblings, 2 replies; 6+ messages in thread
From: Jason S. McMullan @ 2010-04-30 19:13 UTC (permalink / raw)
To: linux-arm-kernel
Support the PL310 16-way cache controller.
Also adds support for smaller than 8 way PL210 controllers.
This is the 2nd iteration. (forgot to mask out only
the cache part ID bits).
Jason S. McMullan (1):
[arm l2x0] Extend cache-l2x0 to support the 16-way PL310
arch/arm/include/asm/hardware/cache-l2x0.h | 3 ++
arch/arm/mm/cache-l2x0.c | 30 ++++++++++++++++++++++++---
2 files changed, 29 insertions(+), 4 deletions(-)
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] [arm l2x0] Extend cache-l2x0 to support the 16-way PL310
2010-04-30 19:13 [PATCH] Extend cache-l2x0 to support the 16-way PL310 Jason S. McMullan
@ 2010-04-30 19:13 ` Jason S. McMullan
2010-05-04 9:10 ` Will Deacon
2010-04-30 19:22 ` Jason S. McMullan
1 sibling, 1 reply; 6+ messages in thread
From: Jason S. McMullan @ 2010-04-30 19:13 UTC (permalink / raw)
To: linux-arm-kernel
The L310 cache controller's interface is almost identical
to the L210. One major difference is that the PL310 can
have up to 16 ways.
This change uses the cache's part ID and the Assciativity
bits in the AUX_CTRL register to determine the number of ways.
Signed-off-by: Jason S. McMullan <jason.mcmullan@netronome.com>
---
arch/arm/include/asm/hardware/cache-l2x0.h | 3 ++
arch/arm/mm/cache-l2x0.c | 30 ++++++++++++++++++++++++---
2 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index cdb9022..6bcba48 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -21,6 +21,9 @@
#define __ASM_ARM_HARDWARE_L2X0_H
#define L2X0_CACHE_ID 0x000
+#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
+#define L2X0_CACHE_ID_PART_L210 (1 << 6)
+#define L2X0_CACHE_ID_PART_L310 (3 << 6)
#define L2X0_CACHE_TYPE 0x004
#define L2X0_CTRL 0x100
#define L2X0_AUX_CTRL 0x104
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 21ad68b..88c6131 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -27,6 +27,7 @@
static void __iomem *l2x0_base;
static DEFINE_SPINLOCK(l2x0_lock);
+static uint32_t l2x0_way_mask; /* Bitmask of active ways */
static inline void cache_wait(void __iomem *reg, unsigned long mask)
{
@@ -106,10 +107,9 @@ static inline void l2x0_inv_all(void)
{
unsigned long flags;
- /* invalidate all ways */
spin_lock_irqsave(&l2x0_lock, flags);
- writel(0xff, l2x0_base + L2X0_INV_WAY);
- cache_wait(l2x0_base + L2X0_INV_WAY, 0xff);
+ writel(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
+ cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
cache_sync();
spin_unlock_irqrestore(&l2x0_lock, flags);
}
@@ -217,10 +217,32 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
* accessing the below registers will fault.
*/
if (!(readl(l2x0_base + L2X0_CTRL) & 1)) {
+ int ways;
+ uint32_t cache_id;
/* l2x0 controller is disabled */
-
+ cache_id = readl(l2x0_base + L2X0_CACHE_ID);
aux = readl(l2x0_base + L2X0_AUX_CTRL);
+
+ /* Determine the number of ways */
+ switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
+ case L2X0_CACHE_ID_PART_L310:
+ if (aux & (1 << 16))
+ ways = 16;
+ else
+ ways = 8;
+ break;
+ case L2X0_CACHE_ID_PART_L210:
+ ways = (aux >> 13) & 0xf;
+ break;
+ default:
+ /* Assume unknown chips have 8 ways */
+ ways = 8;
+ break;
+ }
+
+ l2x0_way_mask = (1 << ways) - 1;
+
aux &= aux_mask;
aux |= aux_val;
writel(aux, l2x0_base + L2X0_AUX_CTRL);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH] [arm l2x0] Extend cache-l2x0 to support the 16-way PL310
2010-04-30 19:13 ` [PATCH] [arm l2x0] " Jason S. McMullan
@ 2010-05-04 9:10 ` Will Deacon
0 siblings, 0 replies; 6+ messages in thread
From: Will Deacon @ 2010-05-04 9:10 UTC (permalink / raw)
To: linux-arm-kernel
Hi Jason,
This is looking good. Some pedantry:
> diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
> index 21ad68b..88c6131 100644
> --- a/arch/arm/mm/cache-l2x0.c
> +++ b/arch/arm/mm/cache-l2x0.c
> @@ -27,6 +27,7 @@
>
> static void __iomem *l2x0_base;
> static DEFINE_SPINLOCK(l2x0_lock);
> +static uint32_t l2x0_way_mask; /* Bitmask of active ways */
>
> static inline void cache_wait(void __iomem *reg, unsigned long mask)
> {
> @@ -106,10 +107,9 @@ static inline void l2x0_inv_all(void)
> {
> unsigned long flags;
>
> - /* invalidate all ways */
> spin_lock_irqsave(&l2x0_lock, flags);
> - writel(0xff, l2x0_base + L2X0_INV_WAY);
> - cache_wait(l2x0_base + L2X0_INV_WAY, 0xff);
> + writel(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
> + cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
> cache_sync();
> spin_unlock_irqrestore(&l2x0_lock, flags);
> }
I think the comment can stay in the code as it's actually true now!
> @@ -217,10 +217,32 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
> * accessing the below registers will fault.
> */
> if (!(readl(l2x0_base + L2X0_CTRL) & 1)) {
> + int ways;
> + uint32_t cache_id;
These declarations should probably be at the top of the function. Actually,
you could just assign to l2x0_way_mask directly. Also, l2x0.c appears to use
the __u32 datatype instead of uint32_t or u32, so it's probably best just to
follow suit.
> /* l2x0 controller is disabled */
> -
> + cache_id = readl(l2x0_base + L2X0_CACHE_ID);
> aux = readl(l2x0_base + L2X0_AUX_CTRL);
> +
> + /* Determine the number of ways */
> + switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
> + case L2X0_CACHE_ID_PART_L310:
> + if (aux & (1 << 16))
> + ways = 16;
> + else
> + ways = 8;
> + break;
> + case L2X0_CACHE_ID_PART_L210:
> + ways = (aux >> 13) & 0xf;
> + break;
> + default:
> + /* Assume unknown chips have 8 ways */
> + ways = 8;
> + break;
> + }
> +
> + l2x0_way_mask = (1 << ways) - 1;
> +
> aux &= aux_mask;
> aux |= aux_val;
> writel(aux, l2x0_base + L2X0_AUX_CTRL);
As Russell pointed out, it would be helpful to print out a message here [instead
of "L2X0 cache controller enabled"], particularly if the chip is unknown and we
assume an 8-way configuration. Printing out the part, number of ways and perhaps
the auxiliary ctrl register would be useful.
Cheers,
Will
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] [arm l2x0] Extend cache-l2x0 to support the 16-way PL310
2010-04-30 19:13 [PATCH] Extend cache-l2x0 to support the 16-way PL310 Jason S. McMullan
2010-04-30 19:13 ` [PATCH] [arm l2x0] " Jason S. McMullan
@ 2010-04-30 19:22 ` Jason S. McMullan
1 sibling, 0 replies; 6+ messages in thread
From: Jason S. McMullan @ 2010-04-30 19:22 UTC (permalink / raw)
To: linux-arm-kernel
The L310 cache controller's interface is almost identical
to the L210. One major difference is that the PL310 can
have up to 16 ways.
This change uses the cache's part ID and the Assciativity
bits in the AUX_CTRL register to determine the number of ways.
Signed-off-by: Jason S. McMullan <jason.mcmullan@netronome.com>
---
arch/arm/include/asm/hardware/cache-l2x0.h | 3 ++
arch/arm/mm/cache-l2x0.c | 30 ++++++++++++++++++++++++---
2 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index cdb9022..6bcba48 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -21,6 +21,9 @@
#define __ASM_ARM_HARDWARE_L2X0_H
#define L2X0_CACHE_ID 0x000
+#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
+#define L2X0_CACHE_ID_PART_L210 (1 << 6)
+#define L2X0_CACHE_ID_PART_L310 (3 << 6)
#define L2X0_CACHE_TYPE 0x004
#define L2X0_CTRL 0x100
#define L2X0_AUX_CTRL 0x104
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 21ad68b..88c6131 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -27,6 +27,7 @@
static void __iomem *l2x0_base;
static DEFINE_SPINLOCK(l2x0_lock);
+static uint32_t l2x0_way_mask; /* Bitmask of active ways */
static inline void cache_wait(void __iomem *reg, unsigned long mask)
{
@@ -106,10 +107,9 @@ static inline void l2x0_inv_all(void)
{
unsigned long flags;
- /* invalidate all ways */
spin_lock_irqsave(&l2x0_lock, flags);
- writel(0xff, l2x0_base + L2X0_INV_WAY);
- cache_wait(l2x0_base + L2X0_INV_WAY, 0xff);
+ writel(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
+ cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
cache_sync();
spin_unlock_irqrestore(&l2x0_lock, flags);
}
@@ -217,10 +217,32 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
* accessing the below registers will fault.
*/
if (!(readl(l2x0_base + L2X0_CTRL) & 1)) {
+ int ways;
+ uint32_t cache_id;
/* l2x0 controller is disabled */
-
+ cache_id = readl(l2x0_base + L2X0_CACHE_ID);
aux = readl(l2x0_base + L2X0_AUX_CTRL);
+
+ /* Determine the number of ways */
+ switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
+ case L2X0_CACHE_ID_PART_L310:
+ if (aux & (1 << 16))
+ ways = 16;
+ else
+ ways = 8;
+ break;
+ case L2X0_CACHE_ID_PART_L210:
+ ways = (aux >> 13) & 0xf;
+ break;
+ default:
+ /* Assume unknown chips have 8 ways */
+ ways = 8;
+ break;
+ }
+
+ l2x0_way_mask = (1 << ways) - 1;
+
aux &= aux_mask;
aux |= aux_val;
writel(aux, l2x0_base + L2X0_AUX_CTRL);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] Extend cache-l2x0 to support the 16-way PL310
@ 2010-04-30 18:54 Jason S. McMullan
2010-04-30 18:54 ` [PATCH] [arm l2x0] " Jason S. McMullan
0 siblings, 1 reply; 6+ messages in thread
From: Jason S. McMullan @ 2010-04-30 18:54 UTC (permalink / raw)
To: linux-arm-kernel
Support the PL310 16-way cache controller.
Also adds support for smaller than 8 way PL210 controllers.
Signed-off-by: Jason S. McMullan <jason.mcmullan@netronome.com>
Jason S. McMullan (1):
[arm l2x0] Extend cache-l2x0 to support the 16-way PL310
arch/arm/include/asm/hardware/cache-l2x0.h | 3 ++
arch/arm/mm/cache-l2x0.c | 30 ++++++++++++++++++++++++---
2 files changed, 29 insertions(+), 4 deletions(-)
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] [arm l2x0] Extend cache-l2x0 to support the 16-way PL310
2010-04-30 18:54 [PATCH] " Jason S. McMullan
@ 2010-04-30 18:54 ` Jason S. McMullan
2010-04-30 19:06 ` Russell King - ARM Linux
0 siblings, 1 reply; 6+ messages in thread
From: Jason S. McMullan @ 2010-04-30 18:54 UTC (permalink / raw)
To: linux-arm-kernel
The L310 cache controller's interface is almost identical
to the L210. One major difference is that the PL310 can
have up to 16 ways.
This change uses the cache's part ID and the Assciativity
bits in the AUX_CTRL register to determine the number of ways.
Signed-off-by: Jason S. McMullan <jason.mcmullan@netronome.com>
---
arch/arm/include/asm/hardware/cache-l2x0.h | 3 ++
arch/arm/mm/cache-l2x0.c | 30 ++++++++++++++++++++++++---
2 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index cdb9022..6bcba48 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -21,6 +21,9 @@
#define __ASM_ARM_HARDWARE_L2X0_H
#define L2X0_CACHE_ID 0x000
+#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
+#define L2X0_CACHE_ID_PART_L210 (1 << 6)
+#define L2X0_CACHE_ID_PART_L310 (3 << 6)
#define L2X0_CACHE_TYPE 0x004
#define L2X0_CTRL 0x100
#define L2X0_AUX_CTRL 0x104
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 21ad68b..32a70a7 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -27,6 +27,7 @@
static void __iomem *l2x0_base;
static DEFINE_SPINLOCK(l2x0_lock);
+static uint32_t l2x0_way_mask; /* Bitmask of active ways */
static inline void cache_wait(void __iomem *reg, unsigned long mask)
{
@@ -106,10 +107,9 @@ static inline void l2x0_inv_all(void)
{
unsigned long flags;
- /* invalidate all ways */
spin_lock_irqsave(&l2x0_lock, flags);
- writel(0xff, l2x0_base + L2X0_INV_WAY);
- cache_wait(l2x0_base + L2X0_INV_WAY, 0xff);
+ writel(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
+ cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
cache_sync();
spin_unlock_irqrestore(&l2x0_lock, flags);
}
@@ -217,10 +217,32 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
* accessing the below registers will fault.
*/
if (!(readl(l2x0_base + L2X0_CTRL) & 1)) {
+ int ways;
+ uint32_t cache_id;
/* l2x0 controller is disabled */
-
+ cache_id = readl(l2x0_base + L2X0_CACHE_ID);
aux = readl(l2x0_base + L2X0_AUX_CTRL);
+
+ /* Determine the number of ways */
+ switch (cache_id) {
+ case L2X0_CACHE_ID_PART_L310:
+ if (aux & (1 << 16))
+ ways = 16;
+ else
+ ways = 8;
+ break;
+ case L2X0_CACHE_ID_PART_L210:
+ ways = (aux >> 13) & 0xf;
+ break;
+ default:
+ /* Assume unknown chips have 8 ways */
+ ways = 8;
+ break;
+ }
+
+ l2x0_way_mask = (1 << ways) - 1;
+
aux &= aux_mask;
aux |= aux_val;
writel(aux, l2x0_base + L2X0_AUX_CTRL);
--
1.7.0.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH] [arm l2x0] Extend cache-l2x0 to support the 16-way PL310
2010-04-30 18:54 ` [PATCH] [arm l2x0] " Jason S. McMullan
@ 2010-04-30 19:06 ` Russell King - ARM Linux
0 siblings, 0 replies; 6+ messages in thread
From: Russell King - ARM Linux @ 2010-04-30 19:06 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Apr 30, 2010 at 02:54:11PM -0400, Jason S. McMullan wrote:
> @@ -217,10 +217,32 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
> * accessing the below registers will fault.
> */
> if (!(readl(l2x0_base + L2X0_CTRL) & 1)) {
> + int ways;
> + uint32_t cache_id;
>
> /* l2x0 controller is disabled */
> -
> + cache_id = readl(l2x0_base + L2X0_CACHE_ID);
> aux = readl(l2x0_base + L2X0_AUX_CTRL);
> +
> + /* Determine the number of ways */
> + switch (cache_id) {
> + case L2X0_CACHE_ID_PART_L310:
> + if (aux & (1 << 16))
> + ways = 16;
> + else
> + ways = 8;
> + break;
> + case L2X0_CACHE_ID_PART_L210:
> + ways = (aux >> 13) & 0xf;
> + break;
One of the things I found myself wishing for with the problems OMAP is
currently having is a means by which the "L2X0 cache controller enabled"
could be more informative about the L2 cache controller.
Maybe it should be "%s cache controller rel%u enabled". Also note that
the L210 and L220 cache controllers have different cache IDs.
L210 has a 1 in bits 9:6, and L220 is 2 in bits 9:6.
However, as for the above patch, I don't think the above code will work;
you're defining the L2X0_CACHE_ID_PART_L310 / L2X0_CACHE_ID_PART_L210
IDs to refer just to the part number field, but you're not masking off
the rest of the fields in cache_id.
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2010-05-04 9:10 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2010-04-30 19:13 [PATCH] Extend cache-l2x0 to support the 16-way PL310 Jason S. McMullan
2010-04-30 19:13 ` [PATCH] [arm l2x0] " Jason S. McMullan
2010-05-04 9:10 ` Will Deacon
2010-04-30 19:22 ` Jason S. McMullan
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2010-04-30 18:54 [PATCH] " Jason S. McMullan
2010-04-30 18:54 ` [PATCH] [arm l2x0] " Jason S. McMullan
2010-04-30 19:06 ` Russell King - ARM Linux
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