* [PATCH 1/7] arm/versatile: move pci code to plat-versatile
2010-10-14 16:10 [PATCH 0/7] arm/versatile PCI support, second try Arnd Bergmann
@ 2010-10-14 16:10 ` Arnd Bergmann
2010-10-18 15:20 ` Linus Walleij
2010-10-14 16:10 ` [PATCH 2/7] arm/versatile: boot-time configure xilinx-pci Arnd Bergmann
` (7 subsequent siblings)
8 siblings, 1 reply; 16+ messages in thread
From: Arnd Bergmann @ 2010-10-14 16:10 UTC (permalink / raw)
To: linux-arm-kernel
The Xilinx PCI macro is used on both versatile-pb and
realview-eb, so we should move the implementation to place
where it can be shared.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/Kconfig | 5 +
arch/arm/mach-versatile/Makefile | 1 -
arch/arm/mach-versatile/pci.c | 361 ----------------------------------
arch/arm/plat-versatile/Makefile | 1 +
arch/arm/plat-versatile/xilinx-pci.c | 361 ++++++++++++++++++++++++++++++++++
5 files changed, 367 insertions(+), 362 deletions(-)
delete mode 100644 arch/arm/mach-versatile/pci.c
create mode 100644 arch/arm/plat-versatile/xilinx-pci.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b8f976a..5bf08c7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1172,6 +1172,11 @@ config PCI_HOST_ITE8152
default y
select DMABOUNCE
+config PCI_HOST_XILINX
+ bool
+ depends on PCI && (ARCH_VERSATILE_PB || MACH_REALVIEW_EB || MACH_REALVIEW_PB1176)
+ default y
+
source "drivers/pci/Kconfig"
source "drivers/pcmcia/Kconfig"
diff --git a/arch/arm/mach-versatile/Makefile b/arch/arm/mach-versatile/Makefile
index 97cf4d8..191b65b 100644
--- a/arch/arm/mach-versatile/Makefile
+++ b/arch/arm/mach-versatile/Makefile
@@ -5,4 +5,3 @@
obj-y := core.o
obj-$(CONFIG_ARCH_VERSATILE_PB) += versatile_pb.o
obj-$(CONFIG_MACH_VERSATILE_AB) += versatile_ab.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
deleted file mode 100644
index 13c7e5f..0000000
--- a/arch/arm/mach-versatile/pci.c
+++ /dev/null
@@ -1,361 +0,0 @@
-/*
- * linux/arch/arm/mach-versatile/pci.c
- *
- * (C) Copyright Koninklijke Philips Electronics NV 2004. All rights reserved.
- * You can redistribute and/or modify this software under the terms of version 2
- * of the GNU General Public License as published by the Free Software Foundation.
- * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
- * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- * Koninklijke Philips Electronics nor its subsidiaries is obligated to provide any support for this software.
- *
- * ARM Versatile PCI driver.
- *
- * 14/04/2005 Initial version, colin.king at philips.com
- *
- */
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/ioport.h>
-#include <linux/interrupt.h>
-#include <linux/spinlock.h>
-#include <linux/init.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/system.h>
-#include <asm/mach/pci.h>
-
-/*
- * these spaces are mapped using the following base registers:
- *
- * Usage Local Bus Memory Base/Map registers used
- *
- * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0, non prefetch
- * Mem 60000000 - 6FFFFFFF LB_BASE1/LB_MAP1, prefetch
- * IO 44000000 - 4FFFFFFF LB_BASE2/LB_MAP2, IO
- * Cfg 42000000 - 42FFFFFF PCI config
- *
- */
-#define __IO_ADDRESS(n) ((void __iomem *)(unsigned long)IO_ADDRESS(n))
-#define SYS_PCICTL __IO_ADDRESS(VERSATILE_SYS_PCICTL)
-#define PCI_IMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x0)
-#define PCI_IMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x4)
-#define PCI_IMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x8)
-#define PCI_SMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x10)
-#define PCI_SMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x14)
-#define PCI_SMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x18)
-#define PCI_SELFID __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0xc)
-
-#define DEVICE_ID_OFFSET 0x00
-#define CSR_OFFSET 0x04
-#define CLASS_ID_OFFSET 0x08
-
-#define VP_PCI_DEVICE_ID 0x030010ee
-#define VP_PCI_CLASS_ID 0x0b400000
-
-static unsigned long pci_slot_ignore = 0;
-
-static int __init versatile_pci_slot_ignore(char *str)
-{
- int retval;
- int slot;
-
- while ((retval = get_option(&str,&slot))) {
- if ((slot < 0) || (slot > 31)) {
- printk("Illegal slot value: %d\n",slot);
- } else {
- pci_slot_ignore |= (1 << slot);
- }
- }
- return 1;
-}
-
-__setup("pci_slot_ignore=", versatile_pci_slot_ignore);
-
-
-static void __iomem *__pci_addr(struct pci_bus *bus,
- unsigned int devfn, int offset)
-{
- unsigned int busnr = bus->number;
-
- /*
- * Trap out illegal values
- */
- if (offset > 255)
- BUG();
- if (busnr > 255)
- BUG();
- if (devfn > 255)
- BUG();
-
- return VERSATILE_PCI_CFG_VIRT_BASE + ((busnr << 16) |
- (PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) | offset);
-}
-
-static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int where,
- int size, u32 *val)
-{
- void __iomem *addr = __pci_addr(bus, devfn, where & ~3);
- u32 v;
- int slot = PCI_SLOT(devfn);
-
- if (pci_slot_ignore & (1 << slot)) {
- /* Ignore this slot */
- switch (size) {
- case 1:
- v = 0xff;
- break;
- case 2:
- v = 0xffff;
- break;
- default:
- v = 0xffffffff;
- }
- } else {
- switch (size) {
- case 1:
- v = __raw_readl(addr);
- if (where & 2) v >>= 16;
- if (where & 1) v >>= 8;
- v &= 0xff;
- break;
-
- case 2:
- v = __raw_readl(addr);
- if (where & 2) v >>= 16;
- v &= 0xffff;
- break;
-
- default:
- v = __raw_readl(addr);
- break;
- }
- }
-
- *val = v;
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int versatile_write_config(struct pci_bus *bus, unsigned int devfn, int where,
- int size, u32 val)
-{
- void __iomem *addr = __pci_addr(bus, devfn, where);
- int slot = PCI_SLOT(devfn);
-
- if (pci_slot_ignore & (1 << slot)) {
- return PCIBIOS_SUCCESSFUL;
- }
-
- switch (size) {
- case 1:
- __raw_writeb((u8)val, addr);
- break;
-
- case 2:
- __raw_writew((u16)val, addr);
- break;
-
- case 4:
- __raw_writel(val, addr);
- break;
- }
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static struct pci_ops pci_versatile_ops = {
- .read = versatile_read_config,
- .write = versatile_write_config,
-};
-
-static struct resource io_mem = {
- .name = "PCI I/O space",
- .start = VERSATILE_PCI_MEM_BASE0,
- .end = VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1,
- .flags = IORESOURCE_IO,
-};
-
-static struct resource non_mem = {
- .name = "PCI non-prefetchable",
- .start = VERSATILE_PCI_MEM_BASE1,
- .end = VERSATILE_PCI_MEM_BASE1+VERSATILE_PCI_MEM_BASE1_SIZE-1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct resource pre_mem = {
- .name = "PCI prefetchable",
- .start = VERSATILE_PCI_MEM_BASE2,
- .end = VERSATILE_PCI_MEM_BASE2+VERSATILE_PCI_MEM_BASE2_SIZE-1,
- .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
-};
-
-static int __init pci_versatile_setup_resources(struct resource **resource)
-{
- int ret = 0;
-
- ret = request_resource(&iomem_resource, &io_mem);
- if (ret) {
- printk(KERN_ERR "PCI: unable to allocate I/O "
- "memory region (%d)\n", ret);
- goto out;
- }
- ret = request_resource(&iomem_resource, &non_mem);
- if (ret) {
- printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
- "memory region (%d)\n", ret);
- goto release_io_mem;
- }
- ret = request_resource(&iomem_resource, &pre_mem);
- if (ret) {
- printk(KERN_ERR "PCI: unable to allocate prefetchable "
- "memory region (%d)\n", ret);
- goto release_non_mem;
- }
-
- /*
- * bus->resource[0] is the IO resource for this bus
- * bus->resource[1] is the mem resource for this bus
- * bus->resource[2] is the prefetch mem resource for this bus
- */
- resource[0] = &io_mem;
- resource[1] = &non_mem;
- resource[2] = &pre_mem;
-
- goto out;
-
- release_non_mem:
- release_resource(&non_mem);
- release_io_mem:
- release_resource(&io_mem);
- out:
- return ret;
-}
-
-int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
-{
- int ret = 0;
- int i;
- int myslot = -1;
- unsigned long val;
- void __iomem *local_pci_cfg_base;
-
- val = __raw_readl(SYS_PCICTL);
- if (!(val & 1)) {
- printk("Not plugged into PCI backplane!\n");
- ret = -EIO;
- goto out;
- }
-
- if (nr == 0) {
- sys->mem_offset = 0;
- ret = pci_versatile_setup_resources(sys->resource);
- if (ret < 0) {
- printk("pci_versatile_setup: resources... oops?\n");
- goto out;
- }
- } else {
- printk("pci_versatile_setup: resources... nr == 0??\n");
- goto out;
- }
-
- /*
- * We need to discover the PCI core first to configure itself
- * before the main PCI probing is performed
- */
- for (i=0; i<32; i++)
- if ((__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+DEVICE_ID_OFFSET) == VP_PCI_DEVICE_ID) &&
- (__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+CLASS_ID_OFFSET) == VP_PCI_CLASS_ID)) {
- myslot = i;
- break;
- }
-
- if (myslot == -1) {
- printk("Cannot find PCI core!\n");
- ret = -EIO;
- goto out;
- }
-
- printk("PCI core found (slot %d)\n",myslot);
-
- __raw_writel(myslot, PCI_SELFID);
- local_pci_cfg_base = VERSATILE_PCI_CFG_VIRT_BASE + (myslot << 11);
-
- val = __raw_readl(local_pci_cfg_base + CSR_OFFSET);
- val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
- __raw_writel(val, local_pci_cfg_base + CSR_OFFSET);
-
- /*
- * Configure the PCI inbound memory windows to be 1:1 mapped to SDRAM
- */
- __raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_0);
- __raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_1);
- __raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_2);
-
- /*
- * Do not to map Versatile FPGA PCI device into memory space
- */
- pci_slot_ignore |= (1 << myslot);
- ret = 1;
-
- out:
- return ret;
-}
-
-
-struct pci_bus * __init pci_versatile_scan_bus(int nr, struct pci_sys_data *sys)
-{
- return pci_scan_bus(sys->busnr, &pci_versatile_ops, sys);
-}
-
-void __init pci_versatile_preinit(void)
-{
- __raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0);
- __raw_writel(VERSATILE_PCI_MEM_BASE1 >> 28, PCI_IMAP1);
- __raw_writel(VERSATILE_PCI_MEM_BASE2 >> 28, PCI_IMAP2);
-
- __raw_writel(PHYS_OFFSET >> 28, PCI_SMAP0);
- __raw_writel(PHYS_OFFSET >> 28, PCI_SMAP1);
- __raw_writel(PHYS_OFFSET >> 28, PCI_SMAP2);
-
- __raw_writel(1, SYS_PCICTL);
-}
-
-/*
- * map the specified device/slot/pin to an IRQ. Different backplanes may need to modify this.
- */
-static int __init versatile_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
-{
- int irq;
- int devslot = PCI_SLOT(dev->devfn);
-
- /* slot, pin, irq
- * 24 1 27
- * 25 1 28
- * 26 1 29
- * 27 1 30
- */
- irq = 27 + ((slot + pin - 1) & 3);
-
- printk("PCI map irq: slot %d, pin %d, devslot %d, irq: %d\n",slot,pin,devslot,irq);
-
- return irq;
-}
-
-static struct hw_pci versatile_pci __initdata = {
- .swizzle = NULL,
- .map_irq = versatile_map_irq,
- .nr_controllers = 1,
- .setup = pci_versatile_setup,
- .scan = pci_versatile_scan_bus,
- .preinit = pci_versatile_preinit,
-};
-
-static int __init versatile_pci_init(void)
-{
- pci_common_init(&versatile_pci);
- return 0;
-}
-
-subsys_initcall(versatile_pci_init);
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
index 5cf88e8..de870b7 100644
--- a/arch/arm/plat-versatile/Makefile
+++ b/arch/arm/plat-versatile/Makefile
@@ -6,3 +6,4 @@ ifeq ($(CONFIG_LEDS_CLASS),y)
obj-$(CONFIG_ARCH_REALVIEW) += leds.o
obj-$(CONFIG_ARCH_VERSATILE) += leds.o
endif
+obj-$(CONFIG_PCI_HOST_XILINX) += xilinx-pci.o
diff --git a/arch/arm/plat-versatile/xilinx-pci.c b/arch/arm/plat-versatile/xilinx-pci.c
new file mode 100644
index 0000000..13c7e5f
--- /dev/null
+++ b/arch/arm/plat-versatile/xilinx-pci.c
@@ -0,0 +1,361 @@
+/*
+ * linux/arch/arm/mach-versatile/pci.c
+ *
+ * (C) Copyright Koninklijke Philips Electronics NV 2004. All rights reserved.
+ * You can redistribute and/or modify this software under the terms of version 2
+ * of the GNU General Public License as published by the Free Software Foundation.
+ * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
+ * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ * Koninklijke Philips Electronics nor its subsidiaries is obligated to provide any support for this software.
+ *
+ * ARM Versatile PCI driver.
+ *
+ * 14/04/2005 Initial version, colin.king at philips.com
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/init.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/mach/pci.h>
+
+/*
+ * these spaces are mapped using the following base registers:
+ *
+ * Usage Local Bus Memory Base/Map registers used
+ *
+ * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0, non prefetch
+ * Mem 60000000 - 6FFFFFFF LB_BASE1/LB_MAP1, prefetch
+ * IO 44000000 - 4FFFFFFF LB_BASE2/LB_MAP2, IO
+ * Cfg 42000000 - 42FFFFFF PCI config
+ *
+ */
+#define __IO_ADDRESS(n) ((void __iomem *)(unsigned long)IO_ADDRESS(n))
+#define SYS_PCICTL __IO_ADDRESS(VERSATILE_SYS_PCICTL)
+#define PCI_IMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x0)
+#define PCI_IMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x4)
+#define PCI_IMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x8)
+#define PCI_SMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x10)
+#define PCI_SMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x14)
+#define PCI_SMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x18)
+#define PCI_SELFID __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0xc)
+
+#define DEVICE_ID_OFFSET 0x00
+#define CSR_OFFSET 0x04
+#define CLASS_ID_OFFSET 0x08
+
+#define VP_PCI_DEVICE_ID 0x030010ee
+#define VP_PCI_CLASS_ID 0x0b400000
+
+static unsigned long pci_slot_ignore = 0;
+
+static int __init versatile_pci_slot_ignore(char *str)
+{
+ int retval;
+ int slot;
+
+ while ((retval = get_option(&str,&slot))) {
+ if ((slot < 0) || (slot > 31)) {
+ printk("Illegal slot value: %d\n",slot);
+ } else {
+ pci_slot_ignore |= (1 << slot);
+ }
+ }
+ return 1;
+}
+
+__setup("pci_slot_ignore=", versatile_pci_slot_ignore);
+
+
+static void __iomem *__pci_addr(struct pci_bus *bus,
+ unsigned int devfn, int offset)
+{
+ unsigned int busnr = bus->number;
+
+ /*
+ * Trap out illegal values
+ */
+ if (offset > 255)
+ BUG();
+ if (busnr > 255)
+ BUG();
+ if (devfn > 255)
+ BUG();
+
+ return VERSATILE_PCI_CFG_VIRT_BASE + ((busnr << 16) |
+ (PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) | offset);
+}
+
+static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int where,
+ int size, u32 *val)
+{
+ void __iomem *addr = __pci_addr(bus, devfn, where & ~3);
+ u32 v;
+ int slot = PCI_SLOT(devfn);
+
+ if (pci_slot_ignore & (1 << slot)) {
+ /* Ignore this slot */
+ switch (size) {
+ case 1:
+ v = 0xff;
+ break;
+ case 2:
+ v = 0xffff;
+ break;
+ default:
+ v = 0xffffffff;
+ }
+ } else {
+ switch (size) {
+ case 1:
+ v = __raw_readl(addr);
+ if (where & 2) v >>= 16;
+ if (where & 1) v >>= 8;
+ v &= 0xff;
+ break;
+
+ case 2:
+ v = __raw_readl(addr);
+ if (where & 2) v >>= 16;
+ v &= 0xffff;
+ break;
+
+ default:
+ v = __raw_readl(addr);
+ break;
+ }
+ }
+
+ *val = v;
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int versatile_write_config(struct pci_bus *bus, unsigned int devfn, int where,
+ int size, u32 val)
+{
+ void __iomem *addr = __pci_addr(bus, devfn, where);
+ int slot = PCI_SLOT(devfn);
+
+ if (pci_slot_ignore & (1 << slot)) {
+ return PCIBIOS_SUCCESSFUL;
+ }
+
+ switch (size) {
+ case 1:
+ __raw_writeb((u8)val, addr);
+ break;
+
+ case 2:
+ __raw_writew((u16)val, addr);
+ break;
+
+ case 4:
+ __raw_writel(val, addr);
+ break;
+ }
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops pci_versatile_ops = {
+ .read = versatile_read_config,
+ .write = versatile_write_config,
+};
+
+static struct resource io_mem = {
+ .name = "PCI I/O space",
+ .start = VERSATILE_PCI_MEM_BASE0,
+ .end = VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1,
+ .flags = IORESOURCE_IO,
+};
+
+static struct resource non_mem = {
+ .name = "PCI non-prefetchable",
+ .start = VERSATILE_PCI_MEM_BASE1,
+ .end = VERSATILE_PCI_MEM_BASE1+VERSATILE_PCI_MEM_BASE1_SIZE-1,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct resource pre_mem = {
+ .name = "PCI prefetchable",
+ .start = VERSATILE_PCI_MEM_BASE2,
+ .end = VERSATILE_PCI_MEM_BASE2+VERSATILE_PCI_MEM_BASE2_SIZE-1,
+ .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
+};
+
+static int __init pci_versatile_setup_resources(struct resource **resource)
+{
+ int ret = 0;
+
+ ret = request_resource(&iomem_resource, &io_mem);
+ if (ret) {
+ printk(KERN_ERR "PCI: unable to allocate I/O "
+ "memory region (%d)\n", ret);
+ goto out;
+ }
+ ret = request_resource(&iomem_resource, &non_mem);
+ if (ret) {
+ printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
+ "memory region (%d)\n", ret);
+ goto release_io_mem;
+ }
+ ret = request_resource(&iomem_resource, &pre_mem);
+ if (ret) {
+ printk(KERN_ERR "PCI: unable to allocate prefetchable "
+ "memory region (%d)\n", ret);
+ goto release_non_mem;
+ }
+
+ /*
+ * bus->resource[0] is the IO resource for this bus
+ * bus->resource[1] is the mem resource for this bus
+ * bus->resource[2] is the prefetch mem resource for this bus
+ */
+ resource[0] = &io_mem;
+ resource[1] = &non_mem;
+ resource[2] = &pre_mem;
+
+ goto out;
+
+ release_non_mem:
+ release_resource(&non_mem);
+ release_io_mem:
+ release_resource(&io_mem);
+ out:
+ return ret;
+}
+
+int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
+{
+ int ret = 0;
+ int i;
+ int myslot = -1;
+ unsigned long val;
+ void __iomem *local_pci_cfg_base;
+
+ val = __raw_readl(SYS_PCICTL);
+ if (!(val & 1)) {
+ printk("Not plugged into PCI backplane!\n");
+ ret = -EIO;
+ goto out;
+ }
+
+ if (nr == 0) {
+ sys->mem_offset = 0;
+ ret = pci_versatile_setup_resources(sys->resource);
+ if (ret < 0) {
+ printk("pci_versatile_setup: resources... oops?\n");
+ goto out;
+ }
+ } else {
+ printk("pci_versatile_setup: resources... nr == 0??\n");
+ goto out;
+ }
+
+ /*
+ * We need to discover the PCI core first to configure itself
+ * before the main PCI probing is performed
+ */
+ for (i=0; i<32; i++)
+ if ((__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+DEVICE_ID_OFFSET) == VP_PCI_DEVICE_ID) &&
+ (__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+CLASS_ID_OFFSET) == VP_PCI_CLASS_ID)) {
+ myslot = i;
+ break;
+ }
+
+ if (myslot == -1) {
+ printk("Cannot find PCI core!\n");
+ ret = -EIO;
+ goto out;
+ }
+
+ printk("PCI core found (slot %d)\n",myslot);
+
+ __raw_writel(myslot, PCI_SELFID);
+ local_pci_cfg_base = VERSATILE_PCI_CFG_VIRT_BASE + (myslot << 11);
+
+ val = __raw_readl(local_pci_cfg_base + CSR_OFFSET);
+ val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
+ __raw_writel(val, local_pci_cfg_base + CSR_OFFSET);
+
+ /*
+ * Configure the PCI inbound memory windows to be 1:1 mapped to SDRAM
+ */
+ __raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_0);
+ __raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_1);
+ __raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_2);
+
+ /*
+ * Do not to map Versatile FPGA PCI device into memory space
+ */
+ pci_slot_ignore |= (1 << myslot);
+ ret = 1;
+
+ out:
+ return ret;
+}
+
+
+struct pci_bus * __init pci_versatile_scan_bus(int nr, struct pci_sys_data *sys)
+{
+ return pci_scan_bus(sys->busnr, &pci_versatile_ops, sys);
+}
+
+void __init pci_versatile_preinit(void)
+{
+ __raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0);
+ __raw_writel(VERSATILE_PCI_MEM_BASE1 >> 28, PCI_IMAP1);
+ __raw_writel(VERSATILE_PCI_MEM_BASE2 >> 28, PCI_IMAP2);
+
+ __raw_writel(PHYS_OFFSET >> 28, PCI_SMAP0);
+ __raw_writel(PHYS_OFFSET >> 28, PCI_SMAP1);
+ __raw_writel(PHYS_OFFSET >> 28, PCI_SMAP2);
+
+ __raw_writel(1, SYS_PCICTL);
+}
+
+/*
+ * map the specified device/slot/pin to an IRQ. Different backplanes may need to modify this.
+ */
+static int __init versatile_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+ int irq;
+ int devslot = PCI_SLOT(dev->devfn);
+
+ /* slot, pin, irq
+ * 24 1 27
+ * 25 1 28
+ * 26 1 29
+ * 27 1 30
+ */
+ irq = 27 + ((slot + pin - 1) & 3);
+
+ printk("PCI map irq: slot %d, pin %d, devslot %d, irq: %d\n",slot,pin,devslot,irq);
+
+ return irq;
+}
+
+static struct hw_pci versatile_pci __initdata = {
+ .swizzle = NULL,
+ .map_irq = versatile_map_irq,
+ .nr_controllers = 1,
+ .setup = pci_versatile_setup,
+ .scan = pci_versatile_scan_bus,
+ .preinit = pci_versatile_preinit,
+};
+
+static int __init versatile_pci_init(void)
+{
+ pci_common_init(&versatile_pci);
+ return 0;
+}
+
+subsys_initcall(versatile_pci_init);
--
1.7.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 1/7] arm/versatile: move pci code to plat-versatile
2010-10-14 16:10 ` [PATCH 1/7] arm/versatile: move pci code to plat-versatile Arnd Bergmann
@ 2010-10-18 15:20 ` Linus Walleij
2010-10-18 15:35 ` Arnd Bergmann
0 siblings, 1 reply; 16+ messages in thread
From: Linus Walleij @ 2010-10-18 15:20 UTC (permalink / raw)
To: linux-arm-kernel
2010/10/14 Arnd Bergmann <arnd@arndb.de>:
> The Xilinx PCI macro is used on both versatile-pb and
> realview-eb, so we should move the implementation to place
> where it can be shared.
> ?arch/arm/Kconfig ? ? ? ? ? ? ? ? ? ? | ? ?5 +
> ?arch/arm/mach-versatile/Makefile ? ? | ? ?1 -
> ?arch/arm/mach-versatile/pci.c ? ? ? ?| ?361 ----------------------------------
> ?arch/arm/plat-versatile/Makefile ? ? | ? ?1 +
> ?arch/arm/plat-versatile/xilinx-pci.c | ?361 ++++++++++++++++++++++++++++++++++
What about arch/arm/common?
PCI drivers seem like they could be useful for others than ARM reference
designs too. Xilinx FPGAs are probably quite common anyway.
> (...)
> +obj-$(CONFIG_PCI_HOST_XILINX) += xilinx-pci.o
> diff --git a/arch/arm/plat-versatile/xilinx-pci.c b/arch/arm/plat-versatile/xilinx-pci.c
> new file mode 100644
> index 0000000..13c7e5f
> --- /dev/null
> +++ b/arch/arm/plat-versatile/xilinx-pci.c
> @@ -0,0 +1,361 @@
> +/*
> + * ?linux/arch/arm/mach-versatile/pci.c
Hm this file path seems inappropriate why not just delete it.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/7] arm/versatile: move pci code to plat-versatile
2010-10-18 15:20 ` Linus Walleij
@ 2010-10-18 15:35 ` Arnd Bergmann
0 siblings, 0 replies; 16+ messages in thread
From: Arnd Bergmann @ 2010-10-18 15:35 UTC (permalink / raw)
To: linux-arm-kernel
On Monday 18 October 2010, Linus Walleij wrote:
> 2010/10/14 Arnd Bergmann <arnd@arndb.de>:
>
> > The Xilinx PCI macro is used on both versatile-pb and
> > realview-eb, so we should move the implementation to place
> > where it can be shared.
>
> > arch/arm/Kconfig | 5 +
> > arch/arm/mach-versatile/Makefile | 1 -
> > arch/arm/mach-versatile/pci.c | 361 ----------------------------------
> > arch/arm/plat-versatile/Makefile | 1 +
> > arch/arm/plat-versatile/xilinx-pci.c | 361 ++++++++++++++++++++++++++++++++++
>
> What about arch/arm/common?
>
> PCI drivers seem like they could be useful for others than ARM reference
> designs too. Xilinx FPGAs are probably quite common anyway.
I don't care either way while we don't have any other users. Most likely
a new platform using the same code would need some extra tweaks so we
could just as well move it again then.
OTOH it may also be nice as a generic PCI implementation for qemu
on other platforms which don't have their own PCI. If we ever get device
tree support running, qemu could just define the PCI host on any platform
and Linux can instantiate it from the dt.
> > (...)
> > +obj-$(CONFIG_PCI_HOST_XILINX) += xilinx-pci.o
> > diff --git a/arch/arm/plat-versatile/xilinx-pci.c b/arch/arm/plat-versatile/xilinx-pci.c
> > new file mode 100644
> > index 0000000..13c7e5f
> > --- /dev/null
> > +++ b/arch/arm/plat-versatile/xilinx-pci.c
> > @@ -0,0 +1,361 @@
> > +/*
> > + * linux/arch/arm/mach-versatile/pci.c
>
> Hm this file path seems inappropriate why not just delete it.
Right, will do.
Thanks,
Arnd
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/7] arm/versatile: boot-time configure xilinx-pci
2010-10-14 16:10 [PATCH 0/7] arm/versatile PCI support, second try Arnd Bergmann
2010-10-14 16:10 ` [PATCH 1/7] arm/versatile: move pci code to plat-versatile Arnd Bergmann
@ 2010-10-14 16:10 ` Arnd Bergmann
2010-10-14 16:10 ` [PATCH 3/7] arm/versatile: enable PCI I/O space Arnd Bergmann
` (6 subsequent siblings)
8 siblings, 0 replies; 16+ messages in thread
From: Arnd Bergmann @ 2010-10-14 16:10 UTC (permalink / raw)
To: linux-arm-kernel
The Xilinx-pci code is currently hardcoded to the registers
used on the versatile-pb platform. Make all dependencies on
specific register locations set at boot time so we can use
the same code on realview.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/mach-versatile/versatile_pb.c | 61 +++++++
arch/arm/plat-versatile/include/plat/xilinx-pci.h | 27 +++
arch/arm/plat-versatile/xilinx-pci.c | 201 +++++++++------------
3 files changed, 177 insertions(+), 112 deletions(-)
create mode 100644 arch/arm/plat-versatile/include/plat/xilinx-pci.h
diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
index 239cd30..4e5e1c7 100644
--- a/arch/arm/mach-versatile/versatile_pb.c
+++ b/arch/arm/mach-versatile/versatile_pb.c
@@ -28,6 +28,8 @@
#include <linux/io.h>
#include <mach/hardware.h>
+#include <plat/xilinx-pci.h>
+
#include <asm/irq.h>
#include <asm/mach-types.h>
@@ -94,6 +96,63 @@ static struct amba_device *amba_devs[] __initdata = {
&mmc1_device,
};
+#ifdef CONFIG_PCI_HOST_XILINX
+/*
+ * these spaces are mapped using the following base registers:
+ *
+ * Usage Local Bus Memory Base/Map registers used
+ *
+ * Mem 44000000 - 4FFFFFFF LB_BASE0/LB_MAP0, unused
+ * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1, non prefetch
+ * Mem 60000000 - 6FFFFFFF LB_BASE2/LB_MAP2, prefetch
+ * IO 43000000 - 43FFFFFF IO space
+ * Cfg 42000000 - 42FFFFFF PCI config
+ *
+ */
+#define __IO_ADDRESS(n) ((void __iomem *)(unsigned long)IO_ADDRESS(n))
+static struct xilinx_pci_data versatile_pci_io = {
+ .base = VERSATILE_PCI_VIRT_BASE,
+ .cfg_base = VERSATILE_PCI_CFG_VIRT_BASE,
+ .io_base = NULL,
+ .sys_pcictl = __IO_ADDRESS(VERSATILE_SYS_PCICTL),
+ .core_base = __IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
+ .base_irq = 27,
+
+ /* identity map outbound AHB addresses to PCI addresses */
+ .imap = {
+ VERSATILE_PCI_MEM_BASE0 >> 28, /* 0x44000000 */
+ VERSATILE_PCI_MEM_BASE1 >> 28, /* 0x50000000 */
+ VERSATILE_PCI_MEM_BASE2 >> 28, /* 0x60000000 */
+ },
+
+ /* map all three BARs of the inbound space to RAM */
+ .smap = {
+ PHYS_OFFSET >> 28, /* inbound memory space mapping 0 */
+ PHYS_OFFSET >> 28, /* inbound memory space mapping 1 */
+ PHYS_OFFSET >> 28, /* inbound I/O space mapping */
+ },
+
+ .mem_spaces = {
+ {
+ .name = "PCI unused",
+ .start = VERSATILE_PCI_MEM_BASE0,
+ .end = VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1,
+ .flags = IORESOURCE_IO,
+ }, {
+ .name = "PCI non-prefetchable",
+ .start = VERSATILE_PCI_MEM_BASE1,
+ .end = VERSATILE_PCI_MEM_BASE1+VERSATILE_PCI_MEM_BASE1_SIZE-1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .name = "PCI prefetchable",
+ .start = VERSATILE_PCI_MEM_BASE2,
+ .end = VERSATILE_PCI_MEM_BASE2+VERSATILE_PCI_MEM_BASE2_SIZE-1,
+ .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
+ },
+ },
+};
+#endif
+
static void __init versatile_pb_init(void)
{
int i;
@@ -104,6 +163,8 @@ static void __init versatile_pb_init(void)
struct amba_device *d = amba_devs[i];
amba_device_register(d, &iomem_resource);
}
+
+ xilinx_pci_init(&versatile_pci_io);
}
MACHINE_START(VERSATILE_PB, "ARM-Versatile PB")
diff --git a/arch/arm/plat-versatile/include/plat/xilinx-pci.h b/arch/arm/plat-versatile/include/plat/xilinx-pci.h
new file mode 100644
index 0000000..b0394c5
--- /dev/null
+++ b/arch/arm/plat-versatile/include/plat/xilinx-pci.h
@@ -0,0 +1,27 @@
+#ifndef _PLAT_VERSATILE_XILINX_PCI_H
+#define _PLAT_VERSATILE_XILINX_PCI_H
+
+#include <linux/ioport.h>
+#include <linux/compiler.h>
+
+struct xilinx_pci_data {
+ void __iomem *sys_pcictl;
+ void __iomem *base;
+ void __iomem *core_base;
+ void __iomem *cfg_base;
+ void __iomem *io_base;
+ int base_irq;
+
+ u32 imap[3];
+ u32 smap[3];
+
+ struct resource mem_spaces[3];
+};
+
+#ifdef CONFIG_PCI_HOST_XILINX
+extern int __init xilinx_pci_init(struct xilinx_pci_data *x);
+#else
+#define xilinx_pci_init(x) do { } while (0)
+#endif
+
+#endif
diff --git a/arch/arm/plat-versatile/xilinx-pci.c b/arch/arm/plat-versatile/xilinx-pci.c
index 13c7e5f..28d1d7d 100644
--- a/arch/arm/plat-versatile/xilinx-pci.c
+++ b/arch/arm/plat-versatile/xilinx-pci.c
@@ -1,5 +1,5 @@
/*
- * linux/arch/arm/mach-versatile/pci.c
+ * linux/arch/arm/plat-versatile/pci.c
*
* (C) Copyright Koninklijke Philips Electronics NV 2004. All rights reserved.
* You can redistribute and/or modify this software under the terms of version 2
@@ -27,37 +27,31 @@
#include <asm/system.h>
#include <asm/mach/pci.h>
-/*
- * these spaces are mapped using the following base registers:
- *
- * Usage Local Bus Memory Base/Map registers used
- *
- * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0, non prefetch
- * Mem 60000000 - 6FFFFFFF LB_BASE1/LB_MAP1, prefetch
- * IO 44000000 - 4FFFFFFF LB_BASE2/LB_MAP2, IO
- * Cfg 42000000 - 42FFFFFF PCI config
- *
- */
-#define __IO_ADDRESS(n) ((void __iomem *)(unsigned long)IO_ADDRESS(n))
-#define SYS_PCICTL __IO_ADDRESS(VERSATILE_SYS_PCICTL)
-#define PCI_IMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x0)
-#define PCI_IMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x4)
-#define PCI_IMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x8)
-#define PCI_SMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x10)
-#define PCI_SMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x14)
-#define PCI_SMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x18)
-#define PCI_SELFID __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0xc)
-
-#define DEVICE_ID_OFFSET 0x00
-#define CSR_OFFSET 0x04
-#define CLASS_ID_OFFSET 0x08
-
-#define VP_PCI_DEVICE_ID 0x030010ee
-#define VP_PCI_CLASS_ID 0x0b400000
+#include <plat/xilinx-pci.h>
+
+static struct xilinx_pci_data *xilinx_pci;
+
+#define XILINX_PCI_VIRT_BASE (xilinx_pci->base)
+#define XILINX_PCI_CFG_VIRT_BASE (xilinx_pci->cfg_base)
+#define SYS_PCICTL (xilinx_pci->sys_pcictl)
+#define PCI_IMAP0 (xilinx_pci->core_base+0x0)
+#define PCI_IMAP1 (xilinx_pci->core_base+0x4)
+#define PCI_IMAP2 (xilinx_pci->core_base+0x8)
+#define PCI_SMAP0 (xilinx_pci->core_base+0x14)
+#define PCI_SMAP1 (xilinx_pci->core_base+0x18)
+#define PCI_SMAP2 (xilinx_pci->core_base+0x1c)
+#define PCI_SELFID (xilinx_pci->core_base+0xc)
+
+#define DEVICE_ID_OFFSET 0x00
+#define CSR_OFFSET 0x04
+#define CLASS_ID_OFFSET 0x08
+
+#define VP_PCI_DEVICE_ID 0x030010ee
+#define VP_PCI_CLASS_ID 0x0b400000
static unsigned long pci_slot_ignore = 0;
-static int __init versatile_pci_slot_ignore(char *str)
+static int __init xilinx_pci_slot_ignore(char *str)
{
int retval;
int slot;
@@ -72,7 +66,7 @@ static int __init versatile_pci_slot_ignore(char *str)
return 1;
}
-__setup("pci_slot_ignore=", versatile_pci_slot_ignore);
+__setup("pci_slot_ignore=", xilinx_pci_slot_ignore);
static void __iomem *__pci_addr(struct pci_bus *bus,
@@ -90,11 +84,11 @@ static void __iomem *__pci_addr(struct pci_bus *bus,
if (devfn > 255)
BUG();
- return VERSATILE_PCI_CFG_VIRT_BASE + ((busnr << 16) |
+ return XILINX_PCI_CFG_VIRT_BASE + ((busnr << 16) |
(PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) | offset);
}
-static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int where,
+static int xilinx_read_config(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 *val)
{
void __iomem *addr = __pci_addr(bus, devfn, where & ~3);
@@ -138,7 +132,7 @@ static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int wh
return PCIBIOS_SUCCESSFUL;
}
-static int versatile_write_config(struct pci_bus *bus, unsigned int devfn, int where,
+static int xilinx_write_config(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 val)
{
void __iomem *addr = __pci_addr(bus, devfn, where);
@@ -165,75 +159,48 @@ static int versatile_write_config(struct pci_bus *bus, unsigned int devfn, int w
return PCIBIOS_SUCCESSFUL;
}
-static struct pci_ops pci_versatile_ops = {
- .read = versatile_read_config,
- .write = versatile_write_config,
-};
-
-static struct resource io_mem = {
- .name = "PCI I/O space",
- .start = VERSATILE_PCI_MEM_BASE0,
- .end = VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1,
- .flags = IORESOURCE_IO,
-};
-
-static struct resource non_mem = {
- .name = "PCI non-prefetchable",
- .start = VERSATILE_PCI_MEM_BASE1,
- .end = VERSATILE_PCI_MEM_BASE1+VERSATILE_PCI_MEM_BASE1_SIZE-1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct resource pre_mem = {
- .name = "PCI prefetchable",
- .start = VERSATILE_PCI_MEM_BASE2,
- .end = VERSATILE_PCI_MEM_BASE2+VERSATILE_PCI_MEM_BASE2_SIZE-1,
- .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
+static struct pci_ops pci_xilinx_ops = {
+ .read = xilinx_read_config,
+ .write = xilinx_write_config,
};
-static int __init pci_versatile_setup_resources(struct resource **resource)
+static int __init pci_xilinx_setup_resources(struct resource **resource)
{
int ret = 0;
-
- ret = request_resource(&iomem_resource, &io_mem);
- if (ret) {
- printk(KERN_ERR "PCI: unable to allocate I/O "
- "memory region (%d)\n", ret);
- goto out;
- }
- ret = request_resource(&iomem_resource, &non_mem);
- if (ret) {
- printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
- "memory region (%d)\n", ret);
- goto release_io_mem;
- }
- ret = request_resource(&iomem_resource, &pre_mem);
- if (ret) {
- printk(KERN_ERR "PCI: unable to allocate prefetchable "
- "memory region (%d)\n", ret);
- goto release_non_mem;
+ int i;
+
+ for (i = 0; i < 3; i++) {
+ ret = request_resource(&iomem_resource,
+ &xilinx_pci->mem_spaces[i]);
+ if (ret) {
+ printk(KERN_ERR "PCI: unable to allocate memory "
+ "region %d\n", i);
+ goto out_release;
+ }
}
-
/*
* bus->resource[0] is the IO resource for this bus
* bus->resource[1] is the mem resource for this bus
* bus->resource[2] is the prefetch mem resource for this bus
*/
- resource[0] = &io_mem;
- resource[1] = &non_mem;
- resource[2] = &pre_mem;
-
+ resource[0] = &xilinx_pci->mem_spaces[0];
+ resource[1] = &xilinx_pci->mem_spaces[1];
+ resource[2] = &xilinx_pci->mem_spaces[2];
goto out;
- release_non_mem:
- release_resource(&non_mem);
- release_io_mem:
- release_resource(&io_mem);
+ out_release:
+ switch(i) {
+ case 2:
+ release_resource(&xilinx_pci->mem_spaces[1]);
+ case 1:
+ release_resource(&xilinx_pci->mem_spaces[0]);
+ break;
+ }
out:
return ret;
}
-int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
+int __init pci_xilinx_setup(int nr, struct pci_sys_data *sys)
{
int ret = 0;
int i;
@@ -250,13 +217,13 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
if (nr == 0) {
sys->mem_offset = 0;
- ret = pci_versatile_setup_resources(sys->resource);
+ ret = pci_xilinx_setup_resources(sys->resource);
if (ret < 0) {
- printk("pci_versatile_setup: resources... oops?\n");
+ printk("pci_xilinx_setup: resources... oops?\n");
goto out;
}
} else {
- printk("pci_versatile_setup: resources... nr == 0??\n");
+ printk("pci_xilinx_setup: resources... nr == 0??\n");
goto out;
}
@@ -265,8 +232,8 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
* before the main PCI probing is performed
*/
for (i=0; i<32; i++)
- if ((__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+DEVICE_ID_OFFSET) == VP_PCI_DEVICE_ID) &&
- (__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+CLASS_ID_OFFSET) == VP_PCI_CLASS_ID)) {
+ if ((__raw_readl(XILINX_PCI_VIRT_BASE+(i<<11)+DEVICE_ID_OFFSET) == VP_PCI_DEVICE_ID) &&
+ (__raw_readl(XILINX_PCI_VIRT_BASE+(i<<11)+CLASS_ID_OFFSET) == VP_PCI_CLASS_ID)) {
myslot = i;
break;
}
@@ -280,7 +247,7 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
printk("PCI core found (slot %d)\n",myslot);
__raw_writel(myslot, PCI_SELFID);
- local_pci_cfg_base = VERSATILE_PCI_CFG_VIRT_BASE + (myslot << 11);
+ local_pci_cfg_base = XILINX_PCI_CFG_VIRT_BASE + (myslot << 11);
val = __raw_readl(local_pci_cfg_base + CSR_OFFSET);
val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
@@ -304,28 +271,38 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
}
-struct pci_bus * __init pci_versatile_scan_bus(int nr, struct pci_sys_data *sys)
+struct pci_bus * __init pci_xilinx_scan_bus(int nr, struct pci_sys_data *sys)
{
- return pci_scan_bus(sys->busnr, &pci_versatile_ops, sys);
+ return pci_scan_bus(sys->busnr, &pci_xilinx_ops, sys);
}
-void __init pci_versatile_preinit(void)
+void __init pci_xilinx_preinit(void)
{
- __raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0);
- __raw_writel(VERSATILE_PCI_MEM_BASE1 >> 28, PCI_IMAP1);
- __raw_writel(VERSATILE_PCI_MEM_BASE2 >> 28, PCI_IMAP2);
+ pr_debug("xilinx-pci: before: imap %x %x %x smap %x %x %x\n",
+ readl(PCI_IMAP0), readl(PCI_IMAP1), readl(PCI_IMAP2),
+ readl(PCI_SMAP0), readl(PCI_SMAP1), readl(PCI_SMAP2));
+
+ pr_debug("xilinx-pci: writing: imap %x %x %x smap %x %x %x\n",
+ xilinx_pci->imap[0], xilinx_pci->imap[1], xilinx_pci->imap[2],
+ xilinx_pci->smap[0], xilinx_pci->smap[1], xilinx_pci->smap[2]);
+
+ writel((xilinx_pci->imap[0]), PCI_IMAP0);
+ writel((xilinx_pci->imap[1]), PCI_IMAP1);
+ writel((xilinx_pci->imap[2]), PCI_IMAP2);
- __raw_writel(PHYS_OFFSET >> 28, PCI_SMAP0);
- __raw_writel(PHYS_OFFSET >> 28, PCI_SMAP1);
- __raw_writel(PHYS_OFFSET >> 28, PCI_SMAP2);
+ writel((xilinx_pci->smap[0]), PCI_SMAP0);
+ writel((xilinx_pci->smap[1]), PCI_SMAP1);
+ writel((xilinx_pci->smap[2]), PCI_SMAP2);
- __raw_writel(1, SYS_PCICTL);
+ pr_debug("xilinx-pci: after: imap %x %x %x smap %x %x %x\n",
+ readl(PCI_IMAP0), readl(PCI_IMAP1), readl(PCI_IMAP2),
+ readl(PCI_SMAP0), readl(PCI_SMAP1), readl(PCI_SMAP2));
}
/*
* map the specified device/slot/pin to an IRQ. Different backplanes may need to modify this.
*/
-static int __init versatile_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+static int __init xilinx_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
int devslot = PCI_SLOT(dev->devfn);
@@ -336,26 +313,26 @@ static int __init versatile_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
* 26 1 29
* 27 1 30
*/
- irq = 27 + ((slot + pin - 1) & 3);
+ irq = xilinx_pci->base_irq + ((slot + pin - 1) & 3);
printk("PCI map irq: slot %d, pin %d, devslot %d, irq: %d\n",slot,pin,devslot,irq);
return irq;
}
-static struct hw_pci versatile_pci __initdata = {
+static struct hw_pci xilinx_hw_pci __initdata = {
.swizzle = NULL,
- .map_irq = versatile_map_irq,
+ .map_irq = xilinx_map_irq,
.nr_controllers = 1,
- .setup = pci_versatile_setup,
- .scan = pci_versatile_scan_bus,
- .preinit = pci_versatile_preinit,
+ .setup = pci_xilinx_setup,
+ .scan = pci_xilinx_scan_bus,
+ .preinit = pci_xilinx_preinit,
};
-static int __init versatile_pci_init(void)
+int __init xilinx_pci_init(struct xilinx_pci_data *x)
{
- pci_common_init(&versatile_pci);
+ xilinx_pci = x;
+ pci_common_init(&xilinx_hw_pci);
return 0;
}
-subsys_initcall(versatile_pci_init);
--
1.7.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 3/7] arm/versatile: enable PCI I/O space
2010-10-14 16:10 [PATCH 0/7] arm/versatile PCI support, second try Arnd Bergmann
2010-10-14 16:10 ` [PATCH 1/7] arm/versatile: move pci code to plat-versatile Arnd Bergmann
2010-10-14 16:10 ` [PATCH 2/7] arm/versatile: boot-time configure xilinx-pci Arnd Bergmann
@ 2010-10-14 16:10 ` Arnd Bergmann
2010-10-14 16:10 ` [PATCH 4/7] arm/versatile: use correct PCI IRQ swizzling Arnd Bergmann
` (5 subsequent siblings)
8 siblings, 0 replies; 16+ messages in thread
From: Arnd Bergmann @ 2010-10-14 16:10 UTC (permalink / raw)
To: linux-arm-kernel
I/O space handling on the versatile platform is currently
broken in multiple ways. Most importantly, the ports do
not get mapped into the virtual address space at all.
Also, there is some amount of confusion between PCI I/O
space and other statically mapped MMIO registers in the
platform code:
* The __io_address() macro that is used to access the
platform register maps to the same __io macro that gets
used for I/O space.
* The IO_SPACE_LIMIT is set to a value that is much larger
than the total available space.
* The I/O resource of the PCI bus is set to the physical
address of the mapping, which is way outside of the
actual I/O space limit as well as the address range that
gets decoded by traditional PCI cards.
* No attempt is made to stay outside of the ISA port range
that some device drivers try access.
* No resource gets requested as a child of ioport_resource,
but an IORESOURCE_IO type mapping gets requested
as a child of iomem_resource.
This patch attempts to correct all of the above. This makes
it possible to use virtio-pci based virtual devices as well
as actual PCI cards including those with legacy ISA port
ranges like VGA.
Some of the issues seem to be duplicated on other platforms.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/mach-versatile/core.c | 19 +++----------------
arch/arm/mach-versatile/include/mach/hardware.h | 15 +++++++--------
arch/arm/mach-versatile/include/mach/io.h | 6 ++++--
arch/arm/mach-versatile/include/mach/platform.h | 4 +++-
arch/arm/mach-versatile/versatile_pb.c | 4 ++--
arch/arm/plat-versatile/xilinx-pci.c | 19 +++++++++++++++++--
6 files changed, 36 insertions(+), 31 deletions(-)
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index e38acb0..b03a6d5 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -201,26 +201,13 @@ static struct map_desc versatile_io_desc[] __initdata = {
.pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
.length = VERSATILE_PCI_CFG_BASE_SIZE,
.type = MT_DEVICE
- },
-#if 0
- {
- .virtual = VERSATILE_PCI_VIRT_MEM_BASE0,
- .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
- .length = SZ_16M,
- .type = MT_DEVICE
}, {
- .virtual = VERSATILE_PCI_VIRT_MEM_BASE1,
- .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
- .length = SZ_16M,
- .type = MT_DEVICE
- }, {
- .virtual = VERSATILE_PCI_VIRT_MEM_BASE2,
- .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
- .length = SZ_16M,
+ .virtual = (unsigned long)PCIO_BASE,
+ .pfn = __phys_to_pfn(VERSATILE_PCI_IO_BASE),
+ .length = IO_SPACE_LIMIT,
.type = MT_DEVICE
},
#endif
-#endif
};
void __init versatile_map_io(void)
diff --git a/arch/arm/mach-versatile/include/mach/hardware.h b/arch/arm/mach-versatile/include/mach/hardware.h
index b5e75bb..59b7716 100644
--- a/arch/arm/mach-versatile/include/mach/hardware.h
+++ b/arch/arm/mach-versatile/include/mach/hardware.h
@@ -24,21 +24,20 @@
#include <asm/sizes.h>
+/* macro to get at MMIO space when running virtually */
+#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
+#define __io_address(n) ((void __iomem *)(IO_ADDRESS(n)))
+
/*
* PCI space virtual addresses
*/
#define VERSATILE_PCI_VIRT_BASE (void __iomem *)0xe8000000ul
#define VERSATILE_PCI_CFG_VIRT_BASE (void __iomem *)0xe9000000ul
+#define VERSATILE_PCI_IO_VIRT_BASE (void __iomem *)PCIO_BASE
-/* CIK guesswork */
-#define PCIBIOS_MIN_IO 0x44000000
-#define PCIBIOS_MIN_MEM 0x50000000
+#define PCIBIOS_MIN_IO 0x00001000
+#define PCIBIOS_MIN_MEM 0x00000000
#define pcibios_assign_all_busses() 1
-/* macro to get at IO space when running virtually */
-#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
-
-#define __io_address(n) __io(IO_ADDRESS(n))
-
#endif
diff --git a/arch/arm/mach-versatile/include/mach/io.h b/arch/arm/mach-versatile/include/mach/io.h
index f067c14..07f3aaf 100644
--- a/arch/arm/mach-versatile/include/mach/io.h
+++ b/arch/arm/mach-versatile/include/mach/io.h
@@ -20,9 +20,11 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
-#define IO_SPACE_LIMIT 0xffffffff
+#define PCIO_BASE (void __iomem *)0xeb000000ul
+#define PCIO_SIZE 0x00100000ul
+#define IO_SPACE_LIMIT (PCIO_SIZE - 1)
-#define __io(a) __typesafe_io(a)
+#define __io(a) ((a) + PCIO_BASE)
#define __mem_pci(a) (a)
#endif
diff --git a/arch/arm/mach-versatile/include/mach/platform.h b/arch/arm/mach-versatile/include/mach/platform.h
index ec08740..efb5328 100644
--- a/arch/arm/mach-versatile/include/mach/platform.h
+++ b/arch/arm/mach-versatile/include/mach/platform.h
@@ -231,12 +231,14 @@
/* PCI space */
#define VERSATILE_PCI_BASE 0x41000000 /* PCI Interface */
#define VERSATILE_PCI_CFG_BASE 0x42000000
+#define VERSATILE_PCI_IO_BASE 0x43000000
#define VERSATILE_PCI_MEM_BASE0 0x44000000
#define VERSATILE_PCI_MEM_BASE1 0x50000000
#define VERSATILE_PCI_MEM_BASE2 0x60000000
/* Sizes of above maps */
#define VERSATILE_PCI_BASE_SIZE 0x01000000
-#define VERSATILE_PCI_CFG_BASE_SIZE 0x02000000
+#define VERSATILE_PCI_CFG_BASE_SIZE 0x01000000
+#define VERSATILE_PCI_IO_BASE_SIZE 0x01000000
#define VERSATILE_PCI_MEM_BASE0_SIZE 0x0c000000 /* 32Mb */
#define VERSATILE_PCI_MEM_BASE1_SIZE 0x10000000 /* 256Mb */
#define VERSATILE_PCI_MEM_BASE2_SIZE 0x10000000 /* 256Mb */
diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
index 4e5e1c7..0f39fde 100644
--- a/arch/arm/mach-versatile/versatile_pb.c
+++ b/arch/arm/mach-versatile/versatile_pb.c
@@ -113,7 +113,7 @@ static struct amba_device *amba_devs[] __initdata = {
static struct xilinx_pci_data versatile_pci_io = {
.base = VERSATILE_PCI_VIRT_BASE,
.cfg_base = VERSATILE_PCI_CFG_VIRT_BASE,
- .io_base = NULL,
+ .io_base = PCIO_BASE,
.sys_pcictl = __IO_ADDRESS(VERSATILE_SYS_PCICTL),
.core_base = __IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
.base_irq = 27,
@@ -137,7 +137,7 @@ static struct xilinx_pci_data versatile_pci_io = {
.name = "PCI unused",
.start = VERSATILE_PCI_MEM_BASE0,
.end = VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1,
- .flags = IORESOURCE_IO,
+ .flags = IORESOURCE_MEM,
}, {
.name = "PCI non-prefetchable",
.start = VERSATILE_PCI_MEM_BASE1,
diff --git a/arch/arm/plat-versatile/xilinx-pci.c b/arch/arm/plat-versatile/xilinx-pci.c
index 28d1d7d..425604a 100644
--- a/arch/arm/plat-versatile/xilinx-pci.c
+++ b/arch/arm/plat-versatile/xilinx-pci.c
@@ -164,11 +164,25 @@ static struct pci_ops pci_xilinx_ops = {
.write = xilinx_write_config,
};
+static struct resource io_port = {
+ .name = "PCI",
+ .start = 0,
+ .end = IO_SPACE_LIMIT,
+ .flags = IORESOURCE_IO,
+};
+
static int __init pci_xilinx_setup_resources(struct resource **resource)
{
int ret = 0;
int i;
+ ret = request_resource(&ioport_resource, &io_port);
+ if (ret) {
+ printk(KERN_ERR "PCI: unable to allocate I/O "
+ "port region (%d)\n", ret);
+ goto out;
+ }
+
for (i = 0; i < 3; i++) {
ret = request_resource(&iomem_resource,
&xilinx_pci->mem_spaces[i]);
@@ -183,7 +197,7 @@ static int __init pci_xilinx_setup_resources(struct resource **resource)
* bus->resource[1] is the mem resource for this bus
* bus->resource[2] is the prefetch mem resource for this bus
*/
- resource[0] = &xilinx_pci->mem_spaces[0];
+ resource[0] = &io_port;
resource[1] = &xilinx_pci->mem_spaces[1];
resource[2] = &xilinx_pci->mem_spaces[2];
goto out;
@@ -194,6 +208,8 @@ static int __init pci_xilinx_setup_resources(struct resource **resource)
release_resource(&xilinx_pci->mem_spaces[1]);
case 1:
release_resource(&xilinx_pci->mem_spaces[0]);
+ case 0:
+ release_resource(&io_port);
break;
}
out:
@@ -335,4 +351,3 @@ int __init xilinx_pci_init(struct xilinx_pci_data *x)
pci_common_init(&xilinx_hw_pci);
return 0;
}
-
--
1.7.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 4/7] arm/versatile: use correct PCI IRQ swizzling
2010-10-14 16:10 [PATCH 0/7] arm/versatile PCI support, second try Arnd Bergmann
` (2 preceding siblings ...)
2010-10-14 16:10 ` [PATCH 3/7] arm/versatile: enable PCI I/O space Arnd Bergmann
@ 2010-10-14 16:10 ` Arnd Bergmann
2010-10-14 16:10 ` [PATCH 5/7] arm/realview: fix building PB-A8 and PBX with CONFIG_PCI Arnd Bergmann
` (4 subsequent siblings)
8 siblings, 0 replies; 16+ messages in thread
From: Arnd Bergmann @ 2010-10-14 16:10 UTC (permalink / raw)
To: linux-arm-kernel
The interrupts on the versatile platform only worked for
one slot with a single-function device.
This fixes the swizzling and the IRQ assignment to work for
both slots on the base plane including multi-function devices
and bridges.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/mach-versatile/versatile_pb.c | 1 +
arch/arm/plat-versatile/include/plat/xilinx-pci.h | 1 +
arch/arm/plat-versatile/xilinx-pci.c | 19 +++++++++++--------
3 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
index 0f39fde..e355057 100644
--- a/arch/arm/mach-versatile/versatile_pb.c
+++ b/arch/arm/mach-versatile/versatile_pb.c
@@ -117,6 +117,7 @@ static struct xilinx_pci_data versatile_pci_io = {
.sys_pcictl = __IO_ADDRESS(VERSATILE_SYS_PCICTL),
.core_base = __IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
.base_irq = 27,
+ .irq_rotate = 2,
/* identity map outbound AHB addresses to PCI addresses */
.imap = {
diff --git a/arch/arm/plat-versatile/include/plat/xilinx-pci.h b/arch/arm/plat-versatile/include/plat/xilinx-pci.h
index b0394c5..9156fcb 100644
--- a/arch/arm/plat-versatile/include/plat/xilinx-pci.h
+++ b/arch/arm/plat-versatile/include/plat/xilinx-pci.h
@@ -11,6 +11,7 @@ struct xilinx_pci_data {
void __iomem *cfg_base;
void __iomem *io_base;
int base_irq;
+ int irq_rotate;
u32 imap[3];
u32 smap[3];
diff --git a/arch/arm/plat-versatile/xilinx-pci.c b/arch/arm/plat-versatile/xilinx-pci.c
index 425604a..8da45e7 100644
--- a/arch/arm/plat-versatile/xilinx-pci.c
+++ b/arch/arm/plat-versatile/xilinx-pci.c
@@ -23,6 +23,7 @@
#include <linux/io.h>
#include <mach/hardware.h>
+#include <mach/platform.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/mach/pci.h>
@@ -323,21 +324,23 @@ static int __init xilinx_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
int irq;
int devslot = PCI_SLOT(dev->devfn);
- /* slot, pin, irq
- * 24 1 27
- * 25 1 28
- * 26 1 29
- * 27 1 30
+ /*
+ * Slot to IRQ mapping for RealView Platform Baseboard 926 Backplane
+ * name slot IntA IntB IntC IntD
+ * A 31 IRQ28 IRQ29 IRQ30 IRQ27
+ * B 30 IRQ27 IRQ28 IRQ29 IRQ30
+ * C 29 IRQ30 IRQ27 IRQ28 IRQ29
*/
- irq = xilinx_pci->base_irq + ((slot + pin - 1) & 3);
+ irq = xilinx_pci->base_irq +
+ ((slot + xilinx_pci->irq_rotate + pin - 1) & 3);
- printk("PCI map irq: slot %d, pin %d, devslot %d, irq: %d\n",slot,pin,devslot,irq);
+ pr_debug("PCI map (slot+3) irq: slot %d, pin %d, devslot %d, irq: %d\n",slot,pin,devslot,irq);
return irq;
}
static struct hw_pci xilinx_hw_pci __initdata = {
- .swizzle = NULL,
+ .swizzle = pci_std_swizzle,
.map_irq = xilinx_map_irq,
.nr_controllers = 1,
.setup = pci_xilinx_setup,
--
1.7.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 5/7] arm/realview: fix building PB-A8 and PBX with CONFIG_PCI
2010-10-14 16:10 [PATCH 0/7] arm/versatile PCI support, second try Arnd Bergmann
` (3 preceding siblings ...)
2010-10-14 16:10 ` [PATCH 4/7] arm/versatile: use correct PCI IRQ swizzling Arnd Bergmann
@ 2010-10-14 16:10 ` Arnd Bergmann
2010-10-14 16:10 ` [PATCH 6/7] arm/realview: enable PCI for realview-eb and realview-pb1176 Arnd Bergmann
` (3 subsequent siblings)
8 siblings, 0 replies; 16+ messages in thread
From: Arnd Bergmann @ 2010-10-14 16:10 UTC (permalink / raw)
To: linux-arm-kernel
In a multi-board kernel configuration with multiple realview
boards enabled, you can have CONFIG_PCI enabled on these,
which results in a build failure because of unresolved symbols.
Use the same symbol as on the other boards instead to work
around this.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/mach-realview/realview_pba8.c | 2 +-
arch/arm/mach-realview/realview_pbx.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 6c37621..6c8c89e 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -79,7 +79,7 @@ static struct map_desc realview_pba8_io_desc[] __initdata = {
},
#ifdef CONFIG_PCI
{
- .virtual = PCIX_UNIT_BASE,
+ .virtual = (unsigned long)REALVIEW_PCI_VIRT_BASE,
.pfn = __phys_to_pfn(REALVIEW_PBA8_PCI_BASE),
.length = REALVIEW_PBA8_PCI_BASE_SIZE,
.type = MT_DEVICE
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 9428eff..07f3647 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -80,7 +80,7 @@ static struct map_desc realview_pbx_io_desc[] __initdata = {
},
#ifdef CONFIG_PCI
{
- .virtual = PCIX_UNIT_BASE,
+ .virtual = (unsigned long)REALVIEW_PCI_VIRT_BASE,
.pfn = __phys_to_pfn(REALVIEW_PBX_PCI_BASE),
.length = REALVIEW_PBX_PCI_BASE_SIZE,
.type = MT_DEVICE,
--
1.7.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 6/7] arm/realview: enable PCI for realview-eb and realview-pb1176
2010-10-14 16:10 [PATCH 0/7] arm/versatile PCI support, second try Arnd Bergmann
` (4 preceding siblings ...)
2010-10-14 16:10 ` [PATCH 5/7] arm/realview: fix building PB-A8 and PBX with CONFIG_PCI Arnd Bergmann
@ 2010-10-14 16:10 ` Arnd Bergmann
2010-10-14 16:10 ` [PATCH 7/7] arm: Enable support for virtio Arnd Bergmann
` (2 subsequent siblings)
8 siblings, 0 replies; 16+ messages in thread
From: Arnd Bergmann @ 2010-10-14 16:10 UTC (permalink / raw)
To: linux-arm-kernel
These two boards use the Xilinx PCI macro, so enable the
code and set up all the I/O windows for it.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/Kconfig | 2 +-
arch/arm/mach-realview/include/mach/board-eb.h | 19 ++++
arch/arm/mach-realview/include/mach/board-pb1176.h | 1 +
arch/arm/mach-realview/include/mach/hardware.h | 14 +++-
arch/arm/mach-realview/include/mach/io.h | 6 +-
arch/arm/mach-realview/include/mach/irqs-eb.h | 5 +
arch/arm/mach-realview/include/mach/irqs-pb1176.h | 5 +-
arch/arm/mach-realview/realview_eb.c | 84 ++++++++++++++++-
arch/arm/mach-realview/realview_pb1176.c | 102 ++++++++++++++++++++
9 files changed, 232 insertions(+), 6 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5bf08c7..8533bbe 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1146,7 +1146,7 @@ config ISA_DMA_API
bool
config PCI
- bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX
+ bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX || ARCH_REALVIEW
help
Find out whether you have a PCI motherboard. PCI is the name of a
bus system, i.e. the way the CPU talks to the other stuff inside
diff --git a/arch/arm/mach-realview/include/mach/board-eb.h b/arch/arm/mach-realview/include/mach/board-eb.h
index 794a8d9..7510516 100644
--- a/arch/arm/mach-realview/include/mach/board-eb.h
+++ b/arch/arm/mach-realview/include/mach/board-eb.h
@@ -36,6 +36,7 @@
#define REALVIEW_EB_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */
#define REALVIEW_EB_GPIO0_BASE 0x10013000 /* GPIO port 0 */
#define REALVIEW_EB_RTC_BASE 0x10017000 /* Real Time Clock */
+#define REALVIEW_EB_PCI_CORE_BASE 0x10019000 /* PCI map and control */
#define REALVIEW_EB_CLCD_BASE 0x10020000 /* CLCD */
#define REALVIEW_EB_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
#define REALVIEW_EB_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
@@ -63,6 +64,24 @@
#endif
/*
+ * PCI regions
+ */
+#define REALVIEW_EB_PCI_BASE 0x60000000 /* PCI self config */
+#define REALVIEW_EB_PCI_CFG_BASE 0x61000000 /* PCI config */
+#define REALVIEW_EB_PCI_IO_BASE0 0x62000000 /* PCI IO region */
+#define REALVIEW_EB_PCI_MEM_BASE0 0x63000000 /* Memory region 1 */
+#define REALVIEW_EB_PCI_MEM_BASE1 0x64000000 /* Memory region 2 */
+#define REALVIEW_EB_PCI_MEM_BASE2 0x68000000 /* Memory region 3 */
+
+#define REALVIEW_EB_PCI_BASE_SIZE 0x01000000 /* 16MB */
+#define REALVIEW_EB_PCI_CFG_BASE_SIZE 0x01000000 /* 16MB */
+#define REALVIEW_EB_PCI_IO_BASE0_SIZE 0x01000000 /* 16MB */
+#define REALVIEW_EB_PCI_MEM_BASE0_SIZE 0x01000000 /* 16MB */
+#define REALVIEW_EB_PCI_MEM_BASE1_SIZE 0x04000000 /* 64MB */
+#define REALVIEW_EB_PCI_MEM_BASE2_SIZE 0x08000000 /* 128MB */
+
+
+/*
* Core tile identification (REALVIEW_SYS_PROCID)
*/
#define REALVIEW_EB_PROC_MASK 0xFF000000
diff --git a/arch/arm/mach-realview/include/mach/board-pb1176.h b/arch/arm/mach-realview/include/mach/board-pb1176.h
index 002ab5d..b11a159 100644
--- a/arch/arm/mach-realview/include/mach/board-pb1176.h
+++ b/arch/arm/mach-realview/include/mach/board-pb1176.h
@@ -27,6 +27,7 @@
* Peripheral addresses
*/
#define REALVIEW_PB1176_UART4_BASE 0x10009000 /* UART 4 */
+#define REALVIEW_PB1176_PCI_CORE_BASE 0x10019000 /* PCI map and control */
#define REALVIEW_PB1176_SCTL_BASE 0x10100000 /* System controller */
#define REALVIEW_PB1176_SMC_BASE 0x10111000 /* SMC */
#define REALVIEW_PB1176_DMC_BASE 0x10109000 /* DMC configuration */
diff --git a/arch/arm/mach-realview/include/mach/hardware.h b/arch/arm/mach-realview/include/mach/hardware.h
index 8a638d1..ff60011 100644
--- a/arch/arm/mach-realview/include/mach/hardware.h
+++ b/arch/arm/mach-realview/include/mach/hardware.h
@@ -37,6 +37,18 @@
#else
#define IO_ADDRESS(x) (x)
#endif
-#define __io_address(n) __io(IO_ADDRESS(n))
+#define __io_address(n) ((void __iomem *)(IO_ADDRESS(n)))
+
+/*
+ * PCI space virtual addresses
+ */
+#define REALVIEW_PCI_VIRT_BASE (void __iomem *)0xf8000000ul
+#define REALVIEW_PCI_CFG_VIRT_BASE (void __iomem *)0xf9000000ul
+#define REALVIEW_PCI_IO_VIRT_BASE (void __iomem *)PCIO_BASE
+
+#define PCIBIOS_MIN_IO 0x00001000
+#define PCIBIOS_MIN_MEM 0x00000000
+
+#define pcibios_assign_all_busses() 1
#endif
diff --git a/arch/arm/mach-realview/include/mach/io.h b/arch/arm/mach-realview/include/mach/io.h
index f05bcdf..14304f9 100644
--- a/arch/arm/mach-realview/include/mach/io.h
+++ b/arch/arm/mach-realview/include/mach/io.h
@@ -20,9 +20,11 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
-#define IO_SPACE_LIMIT 0xffffffff
+#define PCIO_BASE (void __iomem *)0xfa000000ul
+#define PCIO_SIZE 0x00100000ul
+#define IO_SPACE_LIMIT (PCIO_SIZE - 1)
-#define __io(a) __typesafe_io(a)
+#define __io(a) ((a) + PCIO_BASE)
#define __mem_pci(a) (a)
#endif
diff --git a/arch/arm/mach-realview/include/mach/irqs-eb.h b/arch/arm/mach-realview/include/mach/irqs-eb.h
index 204d537..1511518 100644
--- a/arch/arm/mach-realview/include/mach/irqs-eb.h
+++ b/arch/arm/mach-realview/include/mach/irqs-eb.h
@@ -59,6 +59,11 @@
#define IRQ_EB_TSPEN (IRQ_EB_GIC_START + 30) /* Touchscreen pen */
#define IRQ_EB_TSKPAD (IRQ_EB_GIC_START + 31) /* Touchscreen keypad */
+#define IRQ_EB_PCI0 (IRQ_EB_GIC_START + 48) /* PCI IntA */
+#define IRQ_EB_PCI1 (IRQ_EB_GIC_START + 49) /* PCI IntB */
+#define IRQ_EB_PCI2 (IRQ_EB_GIC_START + 50) /* PCI IntC */
+#define IRQ_EB_PCI3 (IRQ_EB_GIC_START + 51) /* PCI IntD */
+
/*
* RealView EB + ARM11MPCore interrupt sources (primary GIC on the core tile)
*/
diff --git a/arch/arm/mach-realview/include/mach/irqs-pb1176.h b/arch/arm/mach-realview/include/mach/irqs-pb1176.h
index 5c3c625..cf92425 100644
--- a/arch/arm/mach-realview/include/mach/irqs-pb1176.h
+++ b/arch/arm/mach-realview/include/mach/irqs-pb1176.h
@@ -63,7 +63,10 @@
#define IRQ_PB1176_GPIO2 (IRQ_PB1176_GIC_START + 9)
#define IRQ_PB1176_ETH (IRQ_PB1176_GIC_START + 10) /* Ethernet controller */
#define IRQ_PB1176_USB (IRQ_PB1176_GIC_START + 11) /* USB controller */
-
+#define IRQ_PB1176_PCI_INTA (IRQ_PB1176_GIC_START + 12) /* PCI IntA */
+#define IRQ_PB1176_PCI_INTB (IRQ_PB1176_GIC_START + 13) /* PCI IntB */
+#define IRQ_PB1176_PCI_INTC (IRQ_PB1176_GIC_START + 14) /* PCI IntC */
+#define IRQ_PB1176_PCI_INTD (IRQ_PB1176_GIC_START + 15) /* PCI IntD */
#define IRQ_PB1176_PISMO (IRQ_PB1176_GIC_START + 16)
#define IRQ_PB1176_AACI (IRQ_PB1176_GIC_START + 19) /* Audio Codec */
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 991c1f8..5e4e119 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -44,6 +44,7 @@
#include <mach/board-eb.h>
#include <mach/irqs.h>
+#include <plat/xilinx-pci.h>
#include "core.h"
@@ -85,7 +86,30 @@ static struct map_desc realview_eb_io_desc[] __initdata = {
.pfn = __phys_to_pfn(REALVIEW_EB_UART0_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
- }
+ },
+#endif
+#ifdef CONFIG_PCI
+ {
+ .virtual = IO_ADDRESS(REALVIEW_PCI_CORE_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_PCI_CORE_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE
+ }, {
+ .virtual = (unsigned long)REALVIEW_PCI_VIRT_BASE,
+ .pfn = __phys_to_pfn(REALVIEW_PCI_BASE),
+ .length = REALVIEW_PCI_BASE_SIZE,
+ .type = MT_DEVICE
+ }, {
+ .virtual = (unsigned long)REALVIEW_PCI_CFG_VIRT_BASE,
+ .pfn = __phys_to_pfn(REALVIEW_PCI_CFG_BASE),
+ .length = REALVIEW_PCI_CFG_BASE_SIZE,
+ .type = MT_DEVICE
+ }, {
+ .virtual = (unsigned long)REALVIEW_PCI_IO_VIRT_BASE,
+ .pfn = __phys_to_pfn(REALVIEW_PCI_IO_BASE),
+ .length = REALVIEW_PCI_IO_BASE_SIZE,
+ .type = MT_DEVICE
+ },
#endif
};
@@ -452,6 +476,63 @@ static void realview_eb_reset(char mode)
__raw_writel(0x0008, reset_ctrl);
}
+#ifdef CONFIG_PCI_HOST_XILINX
+/*
+ * Realview/EB and /PB1176 use a the following base registers
+ *
+ * Usage Local Bus Memory Base/Map registers used
+ *
+ * Self 60000000 - 60FFFFFF PCI selfconfig
+ * Cfg 61000000 - 61FFFFFF PCI config
+ * IO 62000000 - 62FFFFFF PCI IO
+ * Mem 63000000 - 63FFFFFF LB_BASE0/LB_MAP0, unused
+ * Mem 64000000 - 67FFFFFF LB_BASE1/LB_MAP1, non-prefetch
+ * Mem 68000000 - 6FFFFFFF LB_BASE2/LB_MAP2, prefetch
+ */
+#define __IO_ADDRESS(n) ((void __iomem *)(unsigned long)IO_ADDRESS(n))
+static struct xilinx_pci_data realview_eb_pci = {
+ .base = REALVIEW_PCI_VIRT_BASE,
+ .cfg_base = REALVIEW_PCI_CFG_VIRT_BASE,
+ .io_base = PCIO_BASE,
+ .sys_pcictl = __IO_ADDRESS(REALVIEW_SYS_PCICTL),
+ .core_base = __IO_ADDRESS(REALVIEW_EB_PCI_CORE_BASE),
+ .base_irq = IRQ_EB_PCI0,
+ .irq_rotate = 3, /* guessed, probably same as pb1176 */
+
+ /* This mapping is according to the Realview/EB user manual. */
+ .imap = {
+ REALVIEW_EB_PCI_MEM_BASE0 & 0xff000000, /* 0x63000000 */
+ REALVIEW_EB_PCI_MEM_BASE1 & 0xfc000000, /* 0x64000000 */
+ REALVIEW_EB_PCI_MEM_BASE2 & 0xf8000000, /* 0x68000000 */
+ },
+
+ .smap = {
+ PHYS_OFFSET && 0xff000000, /* inbound memory BAR 0 */
+ PHYS_OFFSET && 0xff000000, /* inbound memory BAR 1 */
+ PHYS_OFFSET && 0xff000000, /* inbound IO BAR */
+ },
+
+ .mem_spaces = {
+ {
+ .name = "PCI unused",
+ .start = REALVIEW_EB_PCI_MEM_BASE0,
+ .end = REALVIEW_EB_PCI_MEM_BASE0+REALVIEW_EB_PCI_MEM_BASE0_SIZE-1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .name = "PCI non-prefetchable",
+ .start = REALVIEW_EB_PCI_MEM_BASE1,
+ .end = REALVIEW_EB_PCI_MEM_BASE1+REALVIEW_EB_PCI_MEM_BASE1_SIZE-1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .name = "PCI prefetchable",
+ .start = REALVIEW_EB_PCI_MEM_BASE2,
+ .end = REALVIEW_EB_PCI_MEM_BASE2+REALVIEW_EB_PCI_MEM_BASE2_SIZE-1,
+ .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
+ },
+ },
+};
+#endif
+
static void __init realview_eb_init(void)
{
int i;
@@ -471,6 +552,7 @@ static void __init realview_eb_init(void)
platform_device_register(&realview_i2c_device);
platform_device_register(&char_lcd_device);
eth_device_register();
+ xilinx_pci_init(&realview_eb_pci);
realview_usb_register(realview_eb_isp1761_resources);
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index d2be12e..5801102 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -44,6 +44,7 @@
#include <mach/board-pb1176.h>
#include <mach/irqs.h>
+#include <plat/xilinx-pci.h>
#include "core.h"
@@ -102,6 +103,29 @@ static struct map_desc realview_pb1176_io_desc[] __initdata = {
.type = MT_DEVICE,
},
#endif
+#ifdef CONFIG_PCI
+ {
+ .virtual = IO_ADDRESS(REALVIEW_PB1176_PCI_CORE_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_PB1176_PCI_CORE_BASE),
+ .length = SZ_4K,
+ .type = MT_DEVICE
+ }, {
+ .virtual = (unsigned long)REALVIEW_PCI_VIRT_BASE,
+ .pfn = __phys_to_pfn(REALVIEW_PB1176_PCI_BASE),
+ .length = REALVIEW_PB1176_PCI_BASE_SIZE,
+ .type = MT_DEVICE
+ }, {
+ .virtual = (unsigned long)REALVIEW_PCI_CFG_VIRT_BASE,
+ .pfn = __phys_to_pfn(REALVIEW_PB1176_PCI_CFG_BASE),
+ .length = REALVIEW_PB1176_PCI_CFG_BASE_SIZE,
+ .type = MT_DEVICE
+ }, {
+ .virtual = (unsigned long)REALVIEW_PCI_IO_VIRT_BASE,
+ .pfn = __phys_to_pfn(REALVIEW_PB1176_PCI_IO_BASE0),
+ .length = REALVIEW_PB1176_PCI_IO_BASE0_SIZE,
+ .type = MT_DEVICE
+ },
+#endif
};
static void __init realview_pb1176_map_io(void)
@@ -348,6 +372,83 @@ static void realview_pb1176_fixup(struct machine_desc *mdesc,
meminfo->nr_banks = 1;
}
+#ifdef CONFIG_PCI_HOST_XILINX
+/*
+ * Realview/PB1176 uses the following base registers
+ *
+ * Usage Local Bus Memory Base/Map registers used
+ *
+ * Self 60000000 - 60FFFFFF PCI selfconfig
+ * Cfg 61000000 - 61FFFFFF PCI config
+ * IO 62000000 - 62FFFFFF PCI IO
+ * Mem 63000000 - 63FFFFFF LB_BASE0/LB_MAP0, unused
+ * Mem 64000000 - 67FFFFFF LB_BASE1/LB_MAP1, non-prefetch
+ * Mem 68000000 - 6FFFFFFF LB_BASE2/LB_MAP2, prefetch
+ *
+ */
+#define __IO_ADDRESS(n) ((void __iomem *)(unsigned long)IO_ADDRESS(n))
+static struct xilinx_pci_data realview_pb1176_pci = {
+ .base = REALVIEW_PCI_VIRT_BASE,
+ .cfg_base = REALVIEW_PCI_CFG_VIRT_BASE,
+ .io_base = PCIO_BASE,
+ .sys_pcictl = __IO_ADDRESS(REALVIEW_SYS_PCICTL),
+ .core_base = __IO_ADDRESS(REALVIEW_PB1176_PCI_CORE_BASE),
+ .base_irq = IRQ_PB1176_PCI_INTA,
+ .irq_rotate = 3,
+#if 0
+ /*
+ * This mapping is according to the PB1176 user manual but doesn't
+ * seem to work.
+ */
+ .imap = {
+ REALVIEW_PB1176_PCI_MEM_BASE0 >> 24, /* 0x63000000 */
+ REALVIEW_PB1176_PCI_MEM_BASE1 >> 26, /* 0x64000000 */
+ REALVIEW_PB1176_PCI_MEM_BASE2 >> 27, /* 0x68000000 */
+ },
+
+ .smap = {
+ PHYS_OFFSET >> 24, /* inbound memory BAR 0 */
+ PHYS_OFFSET >> 24, /* inbound memory BAR 1 */
+ PHYS_OFFSET >> 24, /* inbound IO BAR */
+ },
+#else
+ /*
+ * This mapping is according to the Realview/EB user manual,
+ * i.e. for another board, but apparently works to some degree.
+ */
+ .imap = {
+ REALVIEW_PB1176_PCI_MEM_BASE0 & 0xff000000, /* 0x63000000 */
+ REALVIEW_PB1176_PCI_MEM_BASE1 & 0xfc000000, /* 0x64000000 */
+ REALVIEW_PB1176_PCI_MEM_BASE2 & 0xf8000000, /* 0x68000000 */
+ },
+
+ .smap = {
+ PHYS_OFFSET && 0xff000000, /* inbound memory BAR 0 */
+ PHYS_OFFSET && 0xff000000, /* inbound memory BAR 1 */
+ PHYS_OFFSET && 0xff000000, /* inbound IO BAR */
+ },
+#endif
+ .mem_spaces = {
+ {
+ .name = "PCI unused",
+ .start = REALVIEW_PB1176_PCI_MEM_BASE0,
+ .end = REALVIEW_PB1176_PCI_MEM_BASE0+REALVIEW_PB1176_PCI_MEM_BASE0_SIZE-1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .name = "PCI non-prefetchable",
+ .start = REALVIEW_PB1176_PCI_MEM_BASE1,
+ .end = REALVIEW_PB1176_PCI_MEM_BASE1+REALVIEW_PB1176_PCI_MEM_BASE1_SIZE-1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .name = "PCI prefetchable",
+ .start = REALVIEW_PB1176_PCI_MEM_BASE2,
+ .end = REALVIEW_PB1176_PCI_MEM_BASE2+REALVIEW_PB1176_PCI_MEM_BASE2_SIZE-1,
+ .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
+ },
+ },
+};
+#endif
+
static void __init realview_pb1176_init(void)
{
int i;
@@ -364,6 +465,7 @@ static void __init realview_pb1176_init(void)
realview_usb_register(realview_pb1176_isp1761_resources);
platform_device_register(&pmu_device);
platform_device_register(&char_lcd_device);
+ xilinx_pci_init(&realview_pb1176_pci);
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
struct amba_device *d = amba_devs[i];
--
1.7.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 7/7] arm: Enable support for virtio
2010-10-14 16:10 [PATCH 0/7] arm/versatile PCI support, second try Arnd Bergmann
` (5 preceding siblings ...)
2010-10-14 16:10 ` [PATCH 6/7] arm/realview: enable PCI for realview-eb and realview-pb1176 Arnd Bergmann
@ 2010-10-14 16:10 ` Arnd Bergmann
2010-10-16 20:52 ` [PATCH 0/7] arm/versatile PCI support, second try Linus Walleij
2010-10-18 18:13 ` Peter Maydell
8 siblings, 0 replies; 16+ messages in thread
From: Arnd Bergmann @ 2010-10-14 16:10 UTC (permalink / raw)
To: linux-arm-kernel
Qemu can use virtio-pci based devices when emulating a
machine with PCI. This adds the necessary Kconfig entry
that allows users to select those drivers.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm/Kconfig | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8533bbe..319f1a0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1179,6 +1179,8 @@ config PCI_HOST_XILINX
source "drivers/pci/Kconfig"
+source "drivers/virtio/Kconfig"
+
source "drivers/pcmcia/Kconfig"
endmenu
--
1.7.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 0/7] arm/versatile PCI support, second try
2010-10-14 16:10 [PATCH 0/7] arm/versatile PCI support, second try Arnd Bergmann
` (6 preceding siblings ...)
2010-10-14 16:10 ` [PATCH 7/7] arm: Enable support for virtio Arnd Bergmann
@ 2010-10-16 20:52 ` Linus Walleij
2010-10-16 21:54 ` Arnd Bergmann
` (2 more replies)
2010-10-18 18:13 ` Peter Maydell
8 siblings, 3 replies; 16+ messages in thread
From: Linus Walleij @ 2010-10-16 20:52 UTC (permalink / raw)
To: linux-arm-kernel
2010/10/14 Arnd Bergmann <arnd@arndb.de>:
> With lots of help and testing from Peter Maydell, I've completed
> a second version of the PCI support for the versatile platform,
> which works much better now on real hardware, although it does
> not improve existing qemu setups.
I've got nothing better to do tonite than playing with the PB1176
board so tried this out...
Some fixup is needed in 6/7, the EB patch because I get this:
arch/arm/mach-realview/realview_eb.c:94: error:
'REALVIEW_PCI_CORE_BASE' undeclared here (not in a function)
arch/arm/mach-realview/realview_eb.c:110: error:
'REALVIEW_PCI_IO_BASE' undeclared here (not in a function)
arch/arm/mach-realview/realview_eb.c:111: error:
'REALVIEW_PCI_IO_BASE_SIZE' undeclared here (not in a function)
make[3]: *** [arch/arm/mach-realview/realview_eb.o] Error 1
make[2]: *** [arch/arm/mach-realview] Error 2
make[2]: *** Waiting for unfinished jobs....
No these are indeed named
REALVIEW_EB_PCI_CORE_BASE
REALVIEW_EB_PCI_IO_BASE0
etc...
If I disable the EB support it compiles and boots. Nothing much
else happens, not even if I enable PCI debugging. But I guess
that's normal since I don't have any PCI enclosure expansion
board for this card?
The only visible change is that /sys/bus/pci now exists with no
slots nor devices in it.
But it's not causing any regressions for me so with a fix
for the compile problem it's
Tested-by: Linus Walleij <linus.walleij@stericsson.com>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 0/7] arm/versatile PCI support, second try
2010-10-16 20:52 ` [PATCH 0/7] arm/versatile PCI support, second try Linus Walleij
@ 2010-10-16 21:54 ` Arnd Bergmann
2010-10-18 8:54 ` Colin Tuckley
[not found] ` <-1220762139438340023@unknownmsgid>
2 siblings, 0 replies; 16+ messages in thread
From: Arnd Bergmann @ 2010-10-16 21:54 UTC (permalink / raw)
To: linux-arm-kernel
On Saturday 16 October 2010, Linus Walleij wrote:
> 2010/10/14 Arnd Bergmann <arnd@arndb.de>:
>
> > With lots of help and testing from Peter Maydell, I've completed
> > a second version of the PCI support for the versatile platform,
> > which works much better now on real hardware, although it does
> > not improve existing qemu setups.
>
> I've got nothing better to do tonite than playing with the PB1176
> board so tried this out...
>
> Some fixup is needed in 6/7, the EB patch because I get this:
> arch/arm/mach-realview/realview_eb.c:94: error:
> 'REALVIEW_PCI_CORE_BASE' undeclared here (not in a function)
> arch/arm/mach-realview/realview_eb.c:110: error:
> 'REALVIEW_PCI_IO_BASE' undeclared here (not in a function)
> arch/arm/mach-realview/realview_eb.c:111: error:
> 'REALVIEW_PCI_IO_BASE_SIZE' undeclared here (not in a function)
> make[3]: *** [arch/arm/mach-realview/realview_eb.o] Error 1
> make[2]: *** [arch/arm/mach-realview] Error 2
> make[2]: *** Waiting for unfinished jobs....
>
> No these are indeed named
> REALVIEW_EB_PCI_CORE_BASE
> REALVIEW_EB_PCI_IO_BASE0
> etc...
Ah right, I removed these when I prepared the patches for submission,
initially I was using the common definitions for the realview boards
but I figured it would be bad since newer realviews have a different
controller. Apparently I forgot to move over the EB code to use the
new definitions I added later.
I'll fix these up.
> If I disable the EB support it compiles and boots. Nothing much
> else happens, not even if I enable PCI debugging. But I guess
> that's normal since I don't have any PCI enclosure expansion
> board for this card?
Yes, without a PCI card to plug into it it's pretty pointless.
> The only visible change is that /sys/bus/pci now exists with no
> slots nor devices in it.
>
> But it's not causing any regressions for me so with a fix
> for the compile problem it's
> Tested-by: Linus Walleij <linus.walleij@stericsson.com>
Thanks,
Arnd
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 0/7] arm/versatile PCI support, second try
2010-10-16 20:52 ` [PATCH 0/7] arm/versatile PCI support, second try Linus Walleij
2010-10-16 21:54 ` Arnd Bergmann
@ 2010-10-18 8:54 ` Colin Tuckley
2010-10-18 15:23 ` Arnd Bergmann
[not found] ` <-1220762139438340023@unknownmsgid>
2 siblings, 1 reply; 16+ messages in thread
From: Colin Tuckley @ 2010-10-18 8:54 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: Linus Walleij
> Sent: 16 October 2010 21:53
> > With lots of help and testing from Peter Maydell, I've completed
> > a second version of the PCI support for the versatile platform,
> > which works much better now on real hardware, although it does
> > not improve existing qemu setups.
>
> I've got nothing better to do tonite than playing with the PB1176
> board so tried this out...
Note that the PB1176 and EB are in mach-realview rather than mach-versatile
like the PB926. This complicates the PCI side of things since the other
boards in mach-realview have a different PCI implementation (via a NEC
custom Northbridge chip).
I am just about to push the PCI code patches for these boards (PBA8,
PB11MPCore and PBX) to the list.
Regards,
Colin
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 0/7] arm/versatile PCI support, second try
2010-10-18 8:54 ` Colin Tuckley
@ 2010-10-18 15:23 ` Arnd Bergmann
0 siblings, 0 replies; 16+ messages in thread
From: Arnd Bergmann @ 2010-10-18 15:23 UTC (permalink / raw)
To: linux-arm-kernel
On Monday 18 October 2010, Colin Tuckley wrote:
> > > With lots of help and testing from Peter Maydell, I've completed
> > > a second version of the PCI support for the versatile platform,
> > > which works much better now on real hardware, although it does
> > > not improve existing qemu setups.
> >
> > I've got nothing better to do tonite than playing with the PB1176
> > board so tried this out...
>
> Note that the PB1176 and EB are in mach-realview rather than mach-versatile
> like the PB926. This complicates the PCI side of things since the other
> boards in mach-realview have a different PCI implementation (via a NEC
> custom Northbridge chip).
Yes, I know that. All of them use plat-versatile though, which is where
the common code sits.
All the code I added is either specific to the xilinx PCI implementation
or specific to one of the boards (pb926, pb1176, eb).
> I am just about to push the PCI code patches for these boards (PBA8,
> PB11MPCore and PBX) to the list.
I don't expect any conflicts besides my patch 5/7, which will get obsoleted
by your patch. If you apply both series, we should be able to enable
both Xilinx and NEC PCI support on mach-realview and have it work
on all the boards.
Arnd
^ permalink raw reply [flat|nested] 16+ messages in thread
[parent not found: <-1220762139438340023@unknownmsgid>]
* [PATCH 0/7] arm/versatile PCI support, second try
2010-10-14 16:10 [PATCH 0/7] arm/versatile PCI support, second try Arnd Bergmann
` (7 preceding siblings ...)
2010-10-16 20:52 ` [PATCH 0/7] arm/versatile PCI support, second try Linus Walleij
@ 2010-10-18 18:13 ` Peter Maydell
8 siblings, 0 replies; 16+ messages in thread
From: Peter Maydell @ 2010-10-18 18:13 UTC (permalink / raw)
To: linux-arm-kernel
On 14 October 2010 17:10, Arnd Bergmann <arnd@arndb.de> wrote:
> With lots of help and testing from Peter Maydell, I've completed
> a second version of the PCI support for the versatile platform,
> which works much better now on real hardware, although it does
> not improve existing qemu setups.
>
> Please review and test.
Confirmed that this patchset gives working PCI (tested with a
sata_via PCI card and disk) on PB926, and working PCI except
for busmaster DMA on PB1176 (same test setup, booting with
libata.dma=0). (Without the patchset PCI doesn't work at all
because the sata_via driver crashes the first time it tries an
I/O access, so even without the 1176 busmastering it's a huge
improvement over the existing situation.)
Tested-by: Peter Maydell <peter.maydell@linaro.org>
-- PMM
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