* [PATCH 1/3] arm64: dts: exynos: ExynosAutov920: Add USB and USB-phy nodes
2025-10-24 11:48 ` [PATCH 0/3] Add and enable USB nodes for ExynosAutov920 SoC Pritam Manohar Sutar
@ 2025-10-24 11:48 ` Pritam Manohar Sutar
2025-10-24 11:48 ` [PATCH 2/3] arm64: dts: exynos: ExynosAutov920: Add regulators for the USB Pritam Manohar Sutar
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Pritam Manohar Sutar @ 2025-10-24 11:48 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, alim.akhtar
Cc: devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel,
rosa.pila, dev.tailor, faraz.ata, muhammed.ali, selvarasu.g,
pritam.sutar
Add USB and USB PHY controller nodes.
Signed-off-by: Pritam Manohar Sutar <pritam.sutar@samsung.com>
---
.../arm64/boot/dts/exynos/exynosautov920.dtsi | 162 ++++++++++++++++++
1 file changed, 162 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
index 6ee74d260776..6ff0e00fd901 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
@@ -1409,6 +1409,168 @@ pinctrl_hsi1: pinctrl@16450000 {
interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
};
+ usbdrd31_ssphy: phy@16480000 {
+ compatible = "samsung,exynosautov920-usb31drd-combo-ssphy";
+ reg = <0x16480000 0x0200>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "phy", "ref";
+ #phy-cells = <1>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ status = "disabled";
+ };
+
+ usbdrd31_hsphy: phy@16490000 {
+ compatible = "samsung,exynosautov920-usbdrd-combo-hsphy";
+ reg = <0x16490000 0x0200>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "phy", "ref";
+ #phy-cells = <1>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ status = "disabled";
+ };
+
+ usbdrd20_phy0: phy@16500000 {
+ compatible = "samsung,exynosautov920-usbdrd-phy";
+ reg = <0x16500000 0x0200>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "phy", "ref";
+ #phy-cells = <1>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ status = "disabled";
+ };
+
+ usbdrd20_phy1: phy@16510000 {
+ compatible = "samsung,exynosautov920-usbdrd-phy";
+ reg = <0x16510000 0x0200>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "phy", "ref";
+ #phy-cells = <1>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ status = "disabled";
+ };
+
+ usbdrd20_phy2: phy@16520000 {
+ compatible = "samsung,exynosautov920-usbdrd-phy";
+ reg = <0x16520000 0x0200>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "phy", "ref";
+ #phy-cells = <1>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ status = "disabled";
+ };
+
+ /* This usb port supports usb31 and usb20 speeds */
+ usbdrd31: usb@16600000 {
+ compatible = "samsung,exynosautov920-dwusb3";
+ ranges = <0x0 0x16600000 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ usbdrd31_dwc3: usb@0 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ interrupts = <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usbdrd31_hsphy 0>, <&usbdrd31_ssphy 0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ snps,has-lpm-erratum;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ };
+ };
+
+ /* This usb port supports only usb20 speeds */
+ usbdrd20_0: usb@16700000 {
+ compatible = "samsung,exynosautov920-dwusb3";
+ ranges = <0x0 0x16700000 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ usbdrd20_dwc3_0: usb@0 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ interrupts = <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usbdrd20_phy0 0>;
+ phy-names = "usb2-phy";
+ snps,has-lpm-erratum;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,quirk-frame-length-adjustment = <0x20>;
+ };
+ };
+
+ /* This usb port supports only usb20 speeds */
+ usbdrd20_1: usb@16800000 {
+ compatible = "samsung,exynosautov920-dwusb3";
+ ranges = <0x0 0x16800000 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ usbdrd20_dwc3_1: usb@0 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usbdrd20_phy1 0>;
+ phy-names = "usb2-phy";
+ snps,has-lpm-erratum;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,quirk-frame-length-adjustment = <0x20>;
+ };
+ };
+
+ /* This usb port supports only usb20 speeds */
+ usbdrd20_2: usb@16900000 {
+ compatible = "samsung,exynosautov920-dwusb3";
+ ranges = <0x0 0x16900000 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ usbdrd20_dwc3_2: usb@0 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x10000>;
+ clocks = <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>,
+ <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>;
+ clock-names = "ref", "susp_clk";
+ interrupts = <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usbdrd20_phy2 0>;
+ phy-names = "usb2-phy";
+ snps,has-lpm-erratum;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,quirk-frame-length-adjustment = <0x20>;
+ };
+ };
+
cmu_hsi2: clock-controller@16b00000 {
compatible = "samsung,exynosautov920-cmu-hsi2";
reg = <0x16b00000 0x8000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 2/3] arm64: dts: exynos: ExynosAutov920: Add regulators for the USB
2025-10-24 11:48 ` [PATCH 0/3] Add and enable USB nodes for ExynosAutov920 SoC Pritam Manohar Sutar
2025-10-24 11:48 ` [PATCH 1/3] arm64: dts: exynos: ExynosAutov920: Add USB and USB-phy nodes Pritam Manohar Sutar
@ 2025-10-24 11:48 ` Pritam Manohar Sutar
2025-10-24 11:48 ` [PATCH 3/3] arm64: dts: exynos: ExynosAutov920: Enable USB nodes Pritam Manohar Sutar
2026-01-22 10:31 ` [PATCH 0/3] Add and enable USB nodes for ExynosAutov920 SoC Pritam Manohar Sutar
3 siblings, 0 replies; 7+ messages in thread
From: Pritam Manohar Sutar @ 2025-10-24 11:48 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, alim.akhtar
Cc: devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel,
rosa.pila, dev.tailor, faraz.ata, muhammed.ali, selvarasu.g,
pritam.sutar
Add dummy regulator for USB and PHY supplies.
Add vbus regulator that is enabled by GPIO pin.
Signed-off-by: Pritam Manohar Sutar <pritam.sutar@samsung.com>
---
.../boot/dts/exynos/exynosautov920-sadk.dts | 139 ++++++++++++++++++
1 file changed, 139 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts
index a397f068ed53..f90f7704597c 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts
+++ b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts
@@ -52,6 +52,76 @@ memory@80000000 {
<0x8 0x80000000 0x1 0xfba00000>,
<0xa 0x00000000 0x2 0x00000000>;
};
+
+ /* TODO: Remove this once PMIC is implemented */
+ dummy_regulator: regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "dummy_regulator";
+ };
+
+ usbdrd31_dwc3_vbus: usbdrd31_dwc3-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usbdrd31_dwc3-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ gpio = <&gpp2 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* Use gpio for enabling vbus regulator */
+ usb_phy0: usb-phy0 {
+ compatible = "usb-nop-xceiv";
+ vbus-supply = <&usbdrd31_dwc3_vbus>;
+ };
+
+ usbdrd20_dwc3_0_vbus: usbdrd20_dwc3_0-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usbdrd20_dwc3_0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ gpio = <&gpp2 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* Use gpio for enabling vbus regulator */
+ usb_phy1: usb-phy1 {
+ compatible = "usb-nop-xceiv";
+ vbus-supply = <&usbdrd20_dwc3_0_vbus>;
+ };
+
+ usbdrd20_dwc3_1_vbus: usbdrd20_dwc3_1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usbdrd20_dwc3_1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ gpio = <&gpp2 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* Use gpio for enabling vbus regulator */
+ usb_phy2: usb-phy2 {
+ compatible = "usb-nop-xceiv";
+ vbus-supply = <&usbdrd20_dwc3_1_vbus>;
+ };
+
+ usbdrd20_dwc3_2_vbus: usbdrd20_dwc3_2-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usbdrd20_dwc3_2-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ gpio = <&gpp2 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* Use gpio for enabling vbus regulator */
+ usb_phy3: usb-phy3 {
+ compatible = "usb-nop-xceiv";
+ vbus-supply = <&usbdrd20_dwc3_2_vbus>;
+ };
};
&pinctrl_alive {
@@ -86,3 +156,72 @@ &usi_0 {
&xtcxo {
clock-frequency = <38400000>;
};
+
+&usbdrd31_ssphy {
+ dvdd-supply = <&dummy_regulator>;
+ vdd18-supply = <&dummy_regulator>;
+};
+
+&usbdrd31_hsphy {
+ dvdd-supply = <&dummy_regulator>;
+ vdd18-supply = <&dummy_regulator>;
+ vdd33-supply = <&dummy_regulator>;
+};
+
+&usbdrd31_dwc3 {
+ maximum-speed = "super-speed-plus";
+ usb-phy = <&usb_phy0>;
+};
+
+&usbdrd31 {
+ vdd10-supply = <&dummy_regulator>;
+ vdd33-supply = <&dummy_regulator>;
+};
+
+&usbdrd20_phy0 {
+ dvdd-supply = <&dummy_regulator>;
+ vdd18-supply = <&dummy_regulator>;
+ vdd33-supply = <&dummy_regulator>;
+};
+
+&usbdrd20_dwc3_0 {
+ maximum-speed = "high-speed";
+ usb-phy = <&usb_phy1>;
+};
+
+&usbdrd20_0 {
+ vdd10-supply = <&dummy_regulator>;
+ vdd33-supply = <&dummy_regulator>;
+};
+
+&usbdrd20_phy1 {
+ dvdd-supply = <&dummy_regulator>;
+ vdd18-supply = <&dummy_regulator>;
+ vdd33-supply = <&dummy_regulator>;
+};
+
+&usbdrd20_dwc3_1 {
+ maximum-speed = "high-speed";
+ usb-phy = <&usb_phy2>;
+};
+
+&usbdrd20_1 {
+ vdd10-supply = <&dummy_regulator>;
+ vdd33-supply = <&dummy_regulator>;
+};
+
+&usbdrd20_phy2 {
+ dvdd-supply = <&dummy_regulator>;
+ vdd18-supply = <&dummy_regulator>;
+ vdd33-supply = <&dummy_regulator>;
+};
+
+&usbdrd20_dwc3_2 {
+ maximum-speed = "high-speed";
+ usb-phy = <&usb_phy3>;
+};
+
+&usbdrd20_2 {
+ vdd10-supply = <&dummy_regulator>;
+ vdd33-supply = <&dummy_regulator>;
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 3/3] arm64: dts: exynos: ExynosAutov920: Enable USB nodes
2025-10-24 11:48 ` [PATCH 0/3] Add and enable USB nodes for ExynosAutov920 SoC Pritam Manohar Sutar
2025-10-24 11:48 ` [PATCH 1/3] arm64: dts: exynos: ExynosAutov920: Add USB and USB-phy nodes Pritam Manohar Sutar
2025-10-24 11:48 ` [PATCH 2/3] arm64: dts: exynos: ExynosAutov920: Add regulators for the USB Pritam Manohar Sutar
@ 2025-10-24 11:48 ` Pritam Manohar Sutar
2026-01-22 10:31 ` [PATCH 0/3] Add and enable USB nodes for ExynosAutov920 SoC Pritam Manohar Sutar
3 siblings, 0 replies; 7+ messages in thread
From: Pritam Manohar Sutar @ 2025-10-24 11:48 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, alim.akhtar
Cc: devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel,
rosa.pila, dev.tailor, faraz.ata, muhammed.ali, selvarasu.g,
pritam.sutar
Enable USB PHY and DWC3 USB controllers' nodes.
Signed-off-by: Pritam Manohar Sutar <pritam.sutar@samsung.com>
---
.../boot/dts/exynos/exynosautov920-sadk.dts | 21 +++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts
index f90f7704597c..5896dd69334a 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts
+++ b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts
@@ -160,15 +160,20 @@ &xtcxo {
&usbdrd31_ssphy {
dvdd-supply = <&dummy_regulator>;
vdd18-supply = <&dummy_regulator>;
+ status = "okay";
};
&usbdrd31_hsphy {
dvdd-supply = <&dummy_regulator>;
vdd18-supply = <&dummy_regulator>;
vdd33-supply = <&dummy_regulator>;
+ status = "okay";
};
&usbdrd31_dwc3 {
+ dr_mode = "otg";
+ usb-role-switch;
+ role-switch-default-mode = "peripheral";
maximum-speed = "super-speed-plus";
usb-phy = <&usb_phy0>;
};
@@ -176,15 +181,20 @@ &usbdrd31_dwc3 {
&usbdrd31 {
vdd10-supply = <&dummy_regulator>;
vdd33-supply = <&dummy_regulator>;
+ status = "okay";
};
&usbdrd20_phy0 {
dvdd-supply = <&dummy_regulator>;
vdd18-supply = <&dummy_regulator>;
vdd33-supply = <&dummy_regulator>;
+ status = "okay";
};
&usbdrd20_dwc3_0 {
+ dr_mode = "otg";
+ usb-role-switch;
+ role-switch-default-mode = "peripheral";
maximum-speed = "high-speed";
usb-phy = <&usb_phy1>;
};
@@ -192,15 +202,20 @@ &usbdrd20_dwc3_0 {
&usbdrd20_0 {
vdd10-supply = <&dummy_regulator>;
vdd33-supply = <&dummy_regulator>;
+ status = "okay";
};
&usbdrd20_phy1 {
dvdd-supply = <&dummy_regulator>;
vdd18-supply = <&dummy_regulator>;
vdd33-supply = <&dummy_regulator>;
+ status = "okay";
};
&usbdrd20_dwc3_1 {
+ dr_mode = "otg";
+ usb-role-switch;
+ role-switch-default-mode = "peripheral";
maximum-speed = "high-speed";
usb-phy = <&usb_phy2>;
};
@@ -208,15 +223,20 @@ &usbdrd20_dwc3_1 {
&usbdrd20_1 {
vdd10-supply = <&dummy_regulator>;
vdd33-supply = <&dummy_regulator>;
+ status = "okay";
};
&usbdrd20_phy2 {
dvdd-supply = <&dummy_regulator>;
vdd18-supply = <&dummy_regulator>;
vdd33-supply = <&dummy_regulator>;
+ status = "okay";
};
&usbdrd20_dwc3_2 {
+ dr_mode = "otg";
+ usb-role-switch;
+ role-switch-default-mode = "peripheral";
maximum-speed = "high-speed";
usb-phy = <&usb_phy3>;
};
@@ -224,4 +244,5 @@ &usbdrd20_dwc3_2 {
&usbdrd20_2 {
vdd10-supply = <&dummy_regulator>;
vdd33-supply = <&dummy_regulator>;
+ status = "okay";
};
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* RE: [PATCH 0/3] Add and enable USB nodes for ExynosAutov920 SoC
2025-10-24 11:48 ` [PATCH 0/3] Add and enable USB nodes for ExynosAutov920 SoC Pritam Manohar Sutar
` (2 preceding siblings ...)
2025-10-24 11:48 ` [PATCH 3/3] arm64: dts: exynos: ExynosAutov920: Enable USB nodes Pritam Manohar Sutar
@ 2026-01-22 10:31 ` Pritam Manohar Sutar
2026-01-22 10:40 ` Krzysztof Kozlowski
3 siblings, 1 reply; 7+ messages in thread
From: Pritam Manohar Sutar @ 2026-01-22 10:31 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, alim.akhtar
Cc: devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel,
rosa.pila, dev.tailor, faraz.ata, muhammed.ali, selvarasu.g
Hi All,
> -----Original Message-----
> From: Pritam Manohar Sutar <pritam.sutar@samsung.com>
> Sent: 24 October 2025 05:19 PM
> To: robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;
> alim.akhtar@samsung.com
> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> samsung-soc@vger.kernel.org; linux-kernel@vger.kernel.org;
> rosa.pila@samsung.com; dev.tailor@samsung.com; faraz.ata@samsung.com;
> muhammed.ali@samsung.com; selvarasu.g@samsung.com;
> pritam.sutar@samsung.com
> Subject: [PATCH 0/3] Add and enable USB nodes for ExynosAutov920 SoC
>
> This SoC has 2 USB typeC and 2 typeA ports those are DWC3 DRD controllers and
> amoung them, one is USB3.1 DRD combo phy and three
> USB2.0 phy controllers. This patchset adds and enables USB and USB-PHY nodes
> in dts.
>
> PMIC driver is not implmented yet, we rely on USB LDOs being enabled by the
> bootloader and used dummy regulators for now.
>
> To drive vbus for host mode, it needs GPIO pin to enable vbus regulator.
> GPIO expander is present in the dts, we used it to enable the vbus regulator
> using GPIO.
>
> USB ports are configured as OTG, and default mode is configured as peripheral.
> These configurations might be changed based on requirements.
>
> This patchset has dependancy on schema and driver implementation[1] and role
> switch control from userspace[2] patches.
> [1]: https://lore.kernel.org/linux-phy/20251010070912.3758334-1-
> pritam.sutar@samsung.com/
> [2]: https://lore.kernel.org/linux-usb/20251024085455.789555-1-
> pritam.sutar@samsung.com/
Above dependent patches are merged, can you please review the patchset?
>
> Pritam Manohar Sutar (3):
> arm64: dts: exynos: ExynosAutov920: Add USB and USB-phy nodes
> arm64: dts: exynos: ExynosAutov920: Add regulators for the USB
> arm64: dts: exynos: ExynosAutov920: Enable USB nodes
>
> .../boot/dts/exynos/exynosautov920-sadk.dts | 160 +++++++++++++++++
> .../arm64/boot/dts/exynos/exynosautov920.dtsi | 162 ++++++++++++++++++
> 2 files changed, 322 insertions(+)
>
> --
> 2.34.1
Thank you,
Regards,
Pritam
^ permalink raw reply [flat|nested] 7+ messages in thread