[PATCH v6 2/7] arm64: Introduce VA_BITS and translation level options

[PATCH v6 2/7] arm64: Introduce VA_BITS and translation level options

[Jungseok Lee]

This patch adds virtual address space size and a level of translation
tables to kernel configuration. It facilicates introduction of
different MMU options, such as 4KB + 4 levels, 16KB + 4 levels and
64KB + 3 levels, easily.

The idea is based on the discussion with Catalin Marinas:
http://www.spinics.net/linux/lists/arm-kernel/msg319552.html

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Steve Capper <steve.capper@linaro.org>
Signed-off-by: Jungseok Lee <jays.lee@samsung.com>
Reviewed-by: Sungjinn Chung <sungjinn.chung@samsung.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
---
 arch/arm64/Kconfig                     |   45 +++++++++++++++++++++++++++++++-
 arch/arm64/include/asm/memory.h        |    6 +----
 arch/arm64/include/asm/page.h          |    2 +-
 arch/arm64/include/asm/pgalloc.h       |    4 +--
 arch/arm64/include/asm/pgtable-hwdef.h |    2 +-
 arch/arm64/include/asm/pgtable.h       |    8 +++---
 arch/arm64/include/asm/tlb.h           |    2 +-
 7 files changed, 54 insertions(+), 15 deletions(-)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 9a5b5fe..9a28cbe 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -144,14 +144,57 @@ endmenu
 
 menu "Kernel Features"
 
+choice
+	prompt "Page size"
+	default ARM64_4K_PAGES
+	help
+	  Allows page size.
+
+config ARM64_4K_PAGES
+	bool "4KB"
+	help
+	  This feature enables 4KB pages support.
+
 config ARM64_64K_PAGES
-	bool "Enable 64KB pages support"
+	bool "64KB"
 	help
 	  This feature enables 64KB pages support (4KB by default)
 	  allowing only two levels of page tables and faster TLB
 	  look-up. AArch32 emulation is not available when this feature
 	  is enabled.
 
+endchoice
+
+choice
+	prompt "Virtual address space size"
+	default ARM64_VA_BITS_39 if ARM64_4K_PAGES
+	default ARM64_VA_BITS_42 if ARM64_64K_PAGES
+	help
+	  Allows choosing one of multiple possible virtual address
+	  space sizes. The level of translation table is determined by
+	  a combination of page size and virtual address space size.
+
+config ARM64_VA_BITS_39
+	bool "39-bit"
+	depends on ARM64_4K_PAGES
+
+config ARM64_VA_BITS_42
+	bool "42-bit"
+	depends on ARM64_64K_PAGES
+
+endchoice
+
+config ARM64_VA_BITS
+	int
+	default 39 if ARM64_VA_BITS_39
+	default 42 if ARM64_VA_BITS_42
+
+config ARM64_2_LEVELS
+	def_bool y if ARM64_64K_PAGES && ARM64_VA_BITS_42
+
+config ARM64_3_LEVELS
+	def_bool y if ARM64_4K_PAGES && ARM64_VA_BITS_39
+
 config CPU_BIG_ENDIAN
        bool "Build big-endian kernel"
        help
diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
index e94f945..f6e7480 100644
--- a/arch/arm64/include/asm/memory.h
+++ b/arch/arm64/include/asm/memory.h
@@ -41,11 +41,7 @@
  * The module space lives between the addresses given by TASK_SIZE
  * and PAGE_OFFSET - it must be within 128MB of the kernel text.
  */
-#ifdef CONFIG_ARM64_64K_PAGES
-#define VA_BITS			(42)
-#else
-#define VA_BITS			(39)
-#endif
+#define VA_BITS			(CONFIG_ARM64_VA_BITS)
 #define PAGE_OFFSET		(UL(0xffffffffffffffff) << (VA_BITS - 1))
 #define MODULES_END		(PAGE_OFFSET)
 #define MODULES_VADDR		(MODULES_END - SZ_64M)
diff --git a/arch/arm64/include/asm/page.h b/arch/arm64/include/asm/page.h
index 46bf666..268e53d 100644
--- a/arch/arm64/include/asm/page.h
+++ b/arch/arm64/include/asm/page.h
@@ -33,7 +33,7 @@
 
 #ifndef __ASSEMBLY__
 
-#ifdef CONFIG_ARM64_64K_PAGES
+#ifdef CONFIG_ARM64_2_LEVELS
 #include <asm/pgtable-2level-types.h>
 #else
 #include <asm/pgtable-3level-types.h>
diff --git a/arch/arm64/include/asm/pgalloc.h b/arch/arm64/include/asm/pgalloc.h
index 9bea6e7..4829837 100644
--- a/arch/arm64/include/asm/pgalloc.h
+++ b/arch/arm64/include/asm/pgalloc.h
@@ -26,7 +26,7 @@
 
 #define check_pgt_cache()		do { } while (0)
 
-#ifndef CONFIG_ARM64_64K_PAGES
+#ifndef CONFIG_ARM64_2_LEVELS
 
 static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
 {
@@ -44,7 +44,7 @@ static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
 	set_pud(pud, __pud(__pa(pmd) | PMD_TYPE_TABLE));
 }
 
-#endif	/* CONFIG_ARM64_64K_PAGES */
+#endif	/* CONFIG_ARM64_2_LEVELS */
 
 extern pgd_t *pgd_alloc(struct mm_struct *mm);
 extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index 955e8c5..c7c603b 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -16,7 +16,7 @@
 #ifndef __ASM_PGTABLE_HWDEF_H
 #define __ASM_PGTABLE_HWDEF_H
 
-#ifdef CONFIG_ARM64_64K_PAGES
+#ifdef CONFIG_ARM64_2_LEVELS
 #include <asm/pgtable-2level-hwdef.h>
 #else
 #include <asm/pgtable-3level-hwdef.h>
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index e4c60d6..4a350af 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -47,7 +47,7 @@ extern void __pmd_error(const char *file, int line, unsigned long val);
 extern void __pgd_error(const char *file, int line, unsigned long val);
 
 #define pte_ERROR(pte)		__pte_error(__FILE__, __LINE__, pte_val(pte))
-#ifndef CONFIG_ARM64_64K_PAGES
+#ifndef CONFIG_ARM64_2_LEVELS
 #define pmd_ERROR(pmd)		__pmd_error(__FILE__, __LINE__, pmd_val(pmd))
 #endif
 #define pgd_ERROR(pgd)		__pgd_error(__FILE__, __LINE__, pgd_val(pgd))
@@ -324,7 +324,7 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd)
  */
 #define mk_pte(page,prot)	pfn_pte(page_to_pfn(page),prot)
 
-#ifndef CONFIG_ARM64_64K_PAGES
+#ifndef CONFIG_ARM64_2_LEVELS
 
 #define pud_none(pud)		(!pud_val(pud))
 #define pud_bad(pud)		(!(pud_val(pud) & 2))
@@ -346,7 +346,7 @@ static inline pmd_t *pud_page_vaddr(pud_t pud)
 	return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK);
 }
 
-#endif	/* CONFIG_ARM64_64K_PAGES */
+#endif	/* CONFIG_ARM64_2_LEVELS */
 
 /* to find an entry in a page-table-directory */
 #define pgd_index(addr)		(((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
@@ -357,7 +357,7 @@ static inline pmd_t *pud_page_vaddr(pud_t pud)
 #define pgd_offset_k(addr)	pgd_offset(&init_mm, addr)
 
 /* Find an entry in the second-level page table.. */
-#ifndef CONFIG_ARM64_64K_PAGES
+#ifndef CONFIG_ARM64_2_LEVELS
 #define pmd_index(addr)		(((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
 {
diff --git a/arch/arm64/include/asm/tlb.h b/arch/arm64/include/asm/tlb.h
index 80e2c08..bc19101 100644
--- a/arch/arm64/include/asm/tlb.h
+++ b/arch/arm64/include/asm/tlb.h
@@ -91,7 +91,7 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
 	tlb_remove_page(tlb, pte);
 }
 
-#ifndef CONFIG_ARM64_64K_PAGES
+#ifndef CONFIG_ARM64_2_LEVELS
 static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
 				  unsigned long addr)
 {
-- 
1.7.10.4

[PATCH v6 2/7] arm64: Introduce VA_BITS and translation level options

[Timur Tabi]

On Mon, May 12, 2014 at 4:40 AM, Jungseok Lee <jays.lee@samsung.com> wrote:
> This patch adds virtual address space size and a level of translation
> tables to kernel configuration. It facilicates introduction of
> different MMU options, such as 4KB + 4 levels, 16KB + 4 levels and
> 64KB + 3 levels, easily.

Is there a reason why this patch has not yet been picked up?  It
appears to work just fine, and the change is necessary for ARM SOCs
that support large amounts of memory.  It seems weird that after so
many versions, reviews, and ACKs, that it still not in linux-next.

[PATCH v6 2/7] arm64: Introduce VA_BITS and translation level options

[Joel Schopp]

I agree that these patches would be very useful.  I just rebased my fix
for a VTTBR_BADDR_MASK bug on one of these patches that could be pulled
out independently.  See
https://lists.cs.columbia.edu/pipermail/kvmarm/2014-July/010480.html

The original author Jungseok Lee is no longer available to work on
future versions of these patches.  I was thinking that if they didn't
get picked up as they are that with the original author's blessing I
would pick them up and keep them forward ported/resubmitted.  I have an
SOC to test them on.

-Joel

On 07/14/2014 02:53 PM, Timur Tabi wrote:
> On Mon, May 12, 2014 at 4:40 AM, Jungseok Lee <jays.lee@samsung.com> wrote:
>> This patch adds virtual address space size and a level of translation
>> tables to kernel configuration. It facilicates introduction of
>> different MMU options, such as 4KB + 4 levels, 16KB + 4 levels and
>> 64KB + 3 levels, easily.
> Is there a reason why this patch has not yet been picked up?  It
> appears to work just fine, and the change is necessary for ARM SOCs
> that support large amounts of memory.  It seems weird that after so
> many versions, reviews, and ACKs, that it still not in linux-next.
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v6 2/7] arm64: Introduce VA_BITS and translation level options

[Catalin Marinas]

On Mon, Jul 14, 2014 at 09:38:59PM +0100, Joel Schopp wrote:
> I agree that these patches would be very useful.  I just rebased my fix
> for a VTTBR_BADDR_MASK bug on one of these patches that could be pulled
> out independently.  See
> https://lists.cs.columbia.edu/pipermail/kvmarm/2014-July/010480.html
> 
> The original author Jungseok Lee is no longer available to work on
> future versions of these patches.  I was thinking that if they didn't
> get picked up as they are that with the original author's blessing I
> would pick them up and keep them forward ported/resubmitted.  I have an
> SOC to test them on.

The patches are pretty good. I'll give them a try tomorrow and if there
isn't something fundamental missing I'll consider taking them for 3.17.

-- 
Catalin

[PATCH v6 2/7] arm64: Introduce VA_BITS and translation level options

[Jungseok Lee]

On Jul 15, 2014, at 7:41 AM, Catalin Marinas wrote:
> On Mon, Jul 14, 2014 at 09:38:59PM +0100, Joel Schopp wrote:
>> I agree that these patches would be very useful.  I just rebased my fix
>> for a VTTBR_BADDR_MASK bug on one of these patches that could be pulled
>> out independently.  See
>> https://lists.cs.columbia.edu/pipermail/kvmarm/2014-July/010480.html
>> 
>> The original author Jungseok Lee is no longer available to work on
>> future versions of these patches.  I was thinking that if they didn't
>> get picked up as they are that with the original author's blessing I
>> would pick them up and keep them forward ported/resubmitted.  I have an
>> SOC to test them on.
> 
> The patches are pretty good. I'll give them a try tomorrow and if there
> isn't something fundamental missing I'll consider taking them for 3.17.

Hi All,

If only stage1 side is taken and merged, KVM should be disabled under 4 level
lookups with the following configuration adjustment. I've tested it on top of
arm64/for-next/core branch and it works fine.

--- a/arch/arm64/kvm/Kconfig
+++ b/arch/arm64/kvm/Kconfig
@@ -18,6 +18,7 @@ if VIRTUALIZATION
 
 config KVM
        bool "Kernel-based Virtual Machine (KVM) support"
+       depends on !ARM64_4_LEVELS
        select MMU_NOTIFIER
        select PREEMPT_NOTIFIERS
        select ANON_INODES

However, I don't know whether it does make sense or not.
In other words, stage2 side should be prepared to fully support 4 level lookups.

In order to cover all combinations of host and guest, VTTBR_X should be determined
dynamically as referring to hardware capability. At this point, the patches have
been revised many times, but they don't have got ACKs from Christoffer and Marc yet.

That is why the patches are pending now in the author's point of view.

- Jungseok Lee

[PATCH v6 2/7] arm64: Introduce VA_BITS and translation level options

[Catalin Marinas]

On 15 Jul 2014, at 15:53, Jungseok Lee <jungseoklee85@gmail.com> wrote:
> On Jul 15, 2014, at 7:41 AM, Catalin Marinas wrote:
>> On Mon, Jul 14, 2014 at 09:38:59PM +0100, Joel Schopp wrote:
>>> I agree that these patches would be very useful.  I just rebased my fix
>>> for a VTTBR_BADDR_MASK bug on one of these patches that could be pulled
>>> out independently.  See
>>> https://lists.cs.columbia.edu/pipermail/kvmarm/2014-July/010480.html
>>>
>>> The original author Jungseok Lee is no longer available to work on
>>> future versions of these patches.  I was thinking that if they didn't
>>> get picked up as they are that with the original author's blessing I
>>> would pick them up and keep them forward ported/resubmitted.  I have an
>>> SOC to test them on.
>>
>> The patches are pretty good. I'll give them a try tomorrow and if there
>> isn't something fundamental missing I'll consider taking them for 3.17.
>
> Hi All,
>
> If only stage1 side is taken and merged, KVM should be disabled under 4 level
> lookups with the following configuration adjustment. I've tested it on top of
> arm64/for-next/core branch and it works fine.
>
> --- a/arch/arm64/kvm/Kconfig
> +++ b/arch/arm64/kvm/Kconfig
> @@ -18,6 +18,7 @@ if VIRTUALIZATION
>
> config KVM
>        bool "Kernel-based Virtual Machine (KVM) support"
> +       depends on !ARM64_4_LEVELS
>        select MMU_NOTIFIER
>        select PREEMPT_NOTIFIERS
>        select ANON_INODES
>
> However, I don't know whether it does make sense or not.

I added some patches on top of your series, I hope to be able to post
them tomorrow. My interim approach was to disable 4-levels if KVM is
enabled.

> In other words, stage2 side should be prepared to fully support 4 level lookups.
>
> In order to cover all combinations of host and guest, VTTBR_X should be determined
> dynamically as referring to hardware capability. At this point, the patches have
> been revised many times, but they don't have got ACKs from Christoffer and Marc yet.
>
> That is why the patches are pending now in the author's point of view.

I have some clean-up for stage 1 on top but nothing major.

Catalin

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[PATCH v6 2/7] arm64: Introduce VA_BITS and translation level options

[Jungseok Lee]

On Jul 16, 2014, at 6:44 AM, Catalin Marinas wrote:
> On 15 Jul 2014, at 15:53, Jungseok Lee <jungseoklee85@gmail.com> wrote:
>> On Jul 15, 2014, at 7:41 AM, Catalin Marinas wrote:
>>> On Mon, Jul 14, 2014 at 09:38:59PM +0100, Joel Schopp wrote:
>>>> I agree that these patches would be very useful.  I just rebased my fix
>>>> for a VTTBR_BADDR_MASK bug on one of these patches that could be pulled
>>>> out independently.  See
>>>> https://lists.cs.columbia.edu/pipermail/kvmarm/2014-July/010480.html
>>>> 
>>>> The original author Jungseok Lee is no longer available to work on
>>>> future versions of these patches.  I was thinking that if they didn't
>>>> get picked up as they are that with the original author's blessing I
>>>> would pick them up and keep them forward ported/resubmitted.  I have an
>>>> SOC to test them on.
>>> 
>>> The patches are pretty good. I'll give them a try tomorrow and if there
>>> isn't something fundamental missing I'll consider taking them for 3.17.
>> 
>> Hi All,
>> 
>> If only stage1 side is taken and merged, KVM should be disabled under 4 level
>> lookups with the following configuration adjustment. I've tested it on top of
>> arm64/for-next/core branch and it works fine.
>> 
>> --- a/arch/arm64/kvm/Kconfig
>> +++ b/arch/arm64/kvm/Kconfig
>> @@ -18,6 +18,7 @@ if VIRTUALIZATION
>> 
>> config KVM
>>       bool "Kernel-based Virtual Machine (KVM) support"
>> +       depends on !ARM64_4_LEVELS
>>       select MMU_NOTIFIER
>>       select PREEMPT_NOTIFIERS
>>       select ANON_INODES
>> 
>> However, I don't know whether it does make sense or not.
> 
> I added some patches on top of your series, I hope to be able to post
> them tomorrow. My interim approach was to disable 4-levels if KVM is
> enabled.

Hi Catalin,

Thanks for the work!
I will take a close look at them.

- Jungseok Lee