[PATCH v3 0/7] Migrate GIC to fasteoi flow control

[PATCH v3 0/7] Migrate GIC to fasteoi flow control

[Will Deacon]

Hello,

This is version 3 of the patch series originally posted here:

v1.) http://lists.infradead.org/pipermail/linux-arm-kernel/2011-February/043083.html
v2.) http://lists.infradead.org/pipermail/linux-arm-kernel/2011-February/043984.html

Changes since v2:

	* Added chained_irq_{enter,exit} functions to work with chained
	  handlers that support multiple primary chips and to aid in
	  bisectibility
	* Based on 2.6.38-rc8

As a result of these changes, all of the BSP code has been reworked so
I'm afraid I need some fresh acks and tested-bys because the old ones
are no longer valid.

I appreciate there is some debate concerning the sanity of chained
handlers with potentially multiple primary chips, but I can't think of
a way to fix these without considering the handlers on a case-by-case
basis which is not the intent of this patch series.

Cheers,

Will


Will Deacon (7):
  ARM: irq: introduce entry and exit functions for chained handlers
  ARM: omap: update GPIO chained IRQ handler to use entry/exit
    functions
  ARM: tegra: update GPIO chained IRQ handler to use entry/exit
    functions
  ARM: s5pv310: update IRQ combiner to use chained entry/exit functions
  ARM: msm: update GPIO chained IRQ handler to use entry/exit functions
  ARM: nmk: update GPIO chained IRQ handler to entry/exit functions
  ARM: gic: use handle_fasteoi_irq for SPIs

 arch/arm/common/gic.c                |   22 +++++++++-------------
 arch/arm/include/asm/mach/irq.h      |   27 +++++++++++++++++++++++++++
 arch/arm/mach-msm/gpio-v2.c          |    6 +++++-
 arch/arm/mach-s5pv310/irq-combiner.c |    6 ++----
 arch/arm/mach-tegra/gpio.c           |    7 ++++---
 arch/arm/plat-nomadik/gpio.c         |   10 ++--------
 arch/arm/plat-omap/gpio.c            |    7 ++++---
 7 files changed, 53 insertions(+), 32 deletions(-)

[PATCH 1/7] ARM: irq: introduce entry and exit functions for chained handlers

[Will Deacon]

Some chained IRQ handlers are written to cope with primary chips of
potentially different flow types. Whether this a sensible thing to do
is a point of contention.

This patch introduces entry/exit functions for chained handlers which
infer the flow type of the primary chip by checking whether or not
the ->irq_eoi function pointer is present and calling back to the
primary chip as necessary.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm/include/asm/mach/irq.h |   27 +++++++++++++++++++++++++++
 1 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h
index 22ac140..34d1de8 100644
--- a/arch/arm/include/asm/mach/irq.h
+++ b/arch/arm/include/asm/mach/irq.h
@@ -34,4 +34,31 @@ do {							\
 	raw_spin_unlock(&desc->lock);			\
 } while(0)
 
+#ifndef __ASSEMBLY__
+static inline void chained_irq_enter(struct irq_chip *chip,
+				     struct irq_desc *desc)
+{
+	/* FastEOI controllers require no action on entry. */
+	if (chip->irq_eoi)
+		return;
+
+	if (chip->irq_mask_ack) {
+		chip->irq_mask_ack(&desc->irq_data);
+	} else {
+		chip->irq_mask(&desc->irq_data);
+		if (chip->irq_ack)
+			chip->irq_ack(&desc->irq_data);
+	}
+}
+
+static inline void chained_irq_exit(struct irq_chip *chip,
+				    struct irq_desc *desc)
+{
+	if (chip->irq_eoi)
+		chip->irq_eoi(&desc->irq_data);
+	else
+		chip->irq_unmask(&desc->irq_data);
+}
+#endif
+
 #endif
-- 
1.7.0.4

[PATCH 2/7] ARM: omap: update GPIO chained IRQ handler to use entry/exit functions

[Will Deacon]

This patch updates the OMAP gpio chained IRQ handler to use the chained
IRQ enter/exit functions in order to function correctly on primary
controllers with different methods of flow control.

Cc: Colin Cross <ccross@google.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm/plat-omap/gpio.c |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 971d186..830c1a6 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -1143,8 +1143,9 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 	struct gpio_bank *bank;
 	u32 retrigger = 0;
 	int unmasked = 0;
+	struct irq_chip *chip = get_irq_desc_chip(desc);
 
-	desc->irq_data.chip->irq_ack(&desc->irq_data);
+	chained_irq_enter(chip, desc);
 
 	bank = get_irq_data(irq);
 #ifdef CONFIG_ARCH_OMAP1
@@ -1201,7 +1202,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 		configured, we could unmask GPIO bank interrupt immediately */
 		if (!level_mask && !unmasked) {
 			unmasked = 1;
-			desc->irq_data.chip->irq_unmask(&desc->irq_data);
+			chained_irq_exit(chip, desc);
 		}
 
 		isr |= retrigger;
@@ -1237,7 +1238,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 	interrupt */
 exit:
 	if (!unmasked)
-		desc->irq_data.chip->irq_unmask(&desc->irq_data);
+		chained_irq_exit(chip, desc);
 }
 
 static void gpio_irq_shutdown(struct irq_data *d)
-- 
1.7.0.4

[PATCH 3/7] ARM: tegra: update GPIO chained IRQ handler to use entry/exit functions

[Will Deacon]

This patch updates the Tegra gpio chained IRQ handler to use the chained
IRQ enter/exit functions in order to function correctly on primary
controllers with different methods of flow control.

This is required for the GIC to move to fasteoi interrupt handling.

Cc: Colin Cross <ccross@android.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm/mach-tegra/gpio.c |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c
index ad80488..406b687 100644
--- a/arch/arm/mach-tegra/gpio.c
+++ b/arch/arm/mach-tegra/gpio.c
@@ -220,8 +220,9 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 	int port;
 	int pin;
 	int unmasked = 0;
+	struct irq_chip chip = get_irq_desc_chip(desc);
 
-	desc->irq_data.chip->irq_ack(&desc->irq_data);
+	chained_irq_enter(chip, desc);
 
 	bank = get_irq_data(irq);
 
@@ -240,7 +241,7 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 			 */
 			if (lvl & (0x100 << pin)) {
 				unmasked = 1;
-				desc->irq_data.chip->irq_unmask(&desc->irq_data);
+				chained_irq_exit(chip, desc);
 			}
 
 			generic_handle_irq(gpio_to_irq(gpio + pin));
@@ -248,7 +249,7 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 	}
 
 	if (!unmasked)
-		desc->irq_data.chip->irq_unmask(&desc->irq_data);
+		chained_irq_exit(chip, desc);
 
 }
 
-- 
1.7.0.4

[PATCH 4/7] ARM: s5pv310: update IRQ combiner to use chained entry/exit functions

[Will Deacon]

This patch updates the IRQ combiner chained IRQ handler code to use the
chained IRQ enter/exit functions in order to function correctly on
primary controllers with different methods of flow control.

This is required for the GIC to move to fasteoi interrupt handling.

Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm/mach-s5pv310/irq-combiner.c |    6 ++----
 1 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-s5pv310/irq-combiner.c b/arch/arm/mach-s5pv310/irq-combiner.c
index 1ea4a9e..d5cf33e 100644
--- a/arch/arm/mach-s5pv310/irq-combiner.c
+++ b/arch/arm/mach-s5pv310/irq-combiner.c
@@ -59,8 +59,7 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 	unsigned int cascade_irq, combiner_irq;
 	unsigned long status;
 
-	/* primary controller ack'ing */
-	chip->irq_ack(&desc->irq_data);
+	chained_irq_enter(chip, desc);
 
 	spin_lock(&irq_controller_lock);
 	status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
@@ -79,8 +78,7 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 		generic_handle_irq(cascade_irq);
 
  out:
-	/* primary controller unmasking */
-	chip->irq_unmask(&desc->irq_data);
+	chained_irq_exit(chip, desc);
 }
 
 static struct irq_chip combiner_chip = {
-- 
1.7.0.4

[PATCH 5/7] ARM: msm: update GPIO chained IRQ handler to use entry/exit functions

[Will Deacon]

This patch updates the MSM gpio chained IRQ handler to use the chained
IRQ enter/exit functions in order to function correctly on primary
controllers with different methods of flow control.

Cc: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm/mach-msm/gpio-v2.c |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-msm/gpio-v2.c b/arch/arm/mach-msm/gpio-v2.c
index 0de19ec..62be63b 100644
--- a/arch/arm/mach-msm/gpio-v2.c
+++ b/arch/arm/mach-msm/gpio-v2.c
@@ -310,6 +310,9 @@ static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
 static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
 	unsigned long i;
+	struct irq_chip *chip = get_irq_desc_chip(desc);
+
+	chained_irq_enter(chip, desc);
 
 	for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS);
 	     i < NR_GPIO_IRQS;
@@ -318,7 +321,8 @@ static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
 			generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip,
 							   i));
 	}
-	desc->chip->ack(irq);
+
+	chained_irq_exit(chip, desc);
 }
 
 static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on)
-- 
1.7.0.4

[PATCH 6/7] ARM: nmk: update GPIO chained IRQ handler to entry/exit functions

[Will Deacon]

This patch updates the Nomadik gpio chained IRQ handler to use the
chained IRQ enter/exit functions in order to function correctly on
primary controllers with different methods of flow control.

Cc: Rabin Vincent <rabin@rab.in>
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm/plat-nomadik/gpio.c |   10 ++--------
 1 files changed, 2 insertions(+), 8 deletions(-)

diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
index 1e88ecb..f4e80c9 100644
--- a/arch/arm/plat-nomadik/gpio.c
+++ b/arch/arm/plat-nomadik/gpio.c
@@ -522,13 +522,7 @@ static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 	u32 pending;
 	unsigned int first_irq;
 
-	if (host_chip->irq_mask_ack)
-		host_chip->irq_mask_ack(&desc->irq_data);
-	else {
-		host_chip->irq_mask(&desc->irq_data);
-		if (host_chip->irq_ack)
-			host_chip->irq_ack(&desc->irq_data);
-	}
+	chained_irq_enter(host_chip, desc);
 
 	nmk_chip = get_irq_data(irq);
 	first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
@@ -537,7 +531,7 @@ static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 		generic_handle_irq(gpio_irq);
 	}
 
-	host_chip->irq_unmask(&desc->irq_data);
+	chained_irq_exit(host_chip, desc);
 }
 
 static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
-- 
1.7.0.4

[PATCH 7/7] ARM: gic: use handle_fasteoi_irq for SPIs

[Will Deacon]

Currently, the gic uses handle_level_irq for handling SPIs (Shared
Peripheral Interrupts), requiring active interrupts to be masked at
the distributor level during IRQ handling.

On a virtualised system, only the CPU interfaces are virtualised in
hardware. Accesses to the distributor must be trapped by the
hypervisor, adding latency to the critical interrupt path in Linux.

This patch modifies the GIC code to use handle_fasteoi_irq for handling
interrupts, which only requires us to signal EOI to the CPU interface
when handling is complete. Cascaded IRQ handling is also updated to use
the chained IRQ enter/exit functions to honour the flow control of the
parent chip.

Note that commit 846afbd1 ("GIC: Dont disable INT in ack callback")
broke cascading interrupts by forgetting to add IRQ masking. This is
no longer an issue because the unmask call is now unnecessary.

Tested on Versatile Express and Realview EB (1176 w/ cascaded GICs).

Cc: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Cc: Russell King - ARM Linux <linux@arm.linux.org.uk>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm/common/gic.c |   22 +++++++++-------------
 1 files changed, 9 insertions(+), 13 deletions(-)

diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 2243772..0ca4ed6 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -71,13 +71,6 @@ static inline unsigned int gic_irq(struct irq_data *d)
 /*
  * Routines to acknowledge, disable and enable interrupts
  */
-static void gic_ack_irq(struct irq_data *d)
-{
-	spin_lock(&irq_controller_lock);
-	writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
-	spin_unlock(&irq_controller_lock);
-}
-
 static void gic_mask_irq(struct irq_data *d)
 {
 	u32 mask = 1 << (d->irq % 32);
@@ -96,6 +89,11 @@ static void gic_unmask_irq(struct irq_data *d)
 	spin_unlock(&irq_controller_lock);
 }
 
+static void gic_eoi_irq(struct irq_data *d)
+{
+	writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
+}
+
 static int gic_set_type(struct irq_data *d, unsigned int type)
 {
 	void __iomem *base = gic_dist_base(d);
@@ -174,8 +172,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 	unsigned int cascade_irq, gic_irq;
 	unsigned long status;
 
-	/* primary controller ack'ing */
-	chip->irq_ack(&desc->irq_data);
+	chained_irq_enter(chip, desc);
 
 	spin_lock(&irq_controller_lock);
 	status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
@@ -192,15 +189,14 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 		generic_handle_irq(cascade_irq);
 
  out:
-	/* primary controller unmasking */
-	chip->irq_unmask(&desc->irq_data);
+	chained_irq_exit(chip, desc);
 }
 
 static struct irq_chip gic_chip = {
 	.name			= "GIC",
-	.irq_ack		= gic_ack_irq,
 	.irq_mask		= gic_mask_irq,
 	.irq_unmask		= gic_unmask_irq,
+	.irq_eoi		= gic_eoi_irq,
 	.irq_set_type		= gic_set_type,
 #ifdef CONFIG_SMP
 	.irq_set_affinity	= gic_set_cpu,
@@ -275,7 +271,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
 	for (i = irq_start; i < irq_limit; i++) {
 		set_irq_chip(i, &gic_chip);
 		set_irq_chip_data(i, gic);
-		set_irq_handler(i, handle_level_irq);
+		set_irq_handler(i, handle_fasteoi_irq);
 		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 	}
 
-- 
1.7.0.4

[PATCH v3 0/7] Migrate GIC to fasteoi flow control

[Will Deacon]

* I wrote:
 
> Hello,
> 
> This is version 3 of the patch series originally posted here:
> 
> v1.) http://lists.infradead.org/pipermail/linux-arm-kernel/2011-February/043083.html
> v2.) http://lists.infradead.org/pipermail/linux-arm-kernel/2011-February/043984.html
> 
> Changes since v2:
> 
> 	* Added chained_irq_{enter,exit} functions to work with chained
> 	  handlers that support multiple primary chips and to aid in
> 	  bisectibility
> 	* Based on 2.6.38-rc8
> 
> As a result of these changes, all of the BSP code has been reworked so
> I'm afraid I need some fresh acks and tested-bys because the old ones
> are no longer valid.
> 
> I appreciate there is some debate concerning the sanity of chained
> handlers with potentially multiple primary chips, but I can't think of
> a way to fix these without considering the handlers on a case-by-case
> basis which is not the intent of this patch series.

Well, I've not had any feedback on this lot but I'd like to
get the first patch merged so that the rest of it can go in
easily with no ordering dependencies.

Any comments on the first patch are more than welcome.

Will

[PATCH 1/7] ARM: irq: introduce entry and exit functions for chained handlers

[Thomas Gleixner]

On Tue, 8 Mar 2011, Will Deacon wrote:

> Some chained IRQ handlers are written to cope with primary chips of
> potentially different flow types. Whether this a sensible thing to do
> is a point of contention.

That wants a comment that these functions are only dealing with
fasteoi and level type flow control.

Otherwise fine with me. Feel free to add my Acked-by.

> This patch introduces entry/exit functions for chained handlers which
> infer the flow type of the primary chip by checking whether or not
> the ->irq_eoi function pointer is present and calling back to the
> primary chip as necessary.
> 
> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
> Signed-off-by: Will Deacon <will.deacon@arm.com>
> ---
>  arch/arm/include/asm/mach/irq.h |   27 +++++++++++++++++++++++++++
>  1 files changed, 27 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h
> index 22ac140..34d1de8 100644
> --- a/arch/arm/include/asm/mach/irq.h
> +++ b/arch/arm/include/asm/mach/irq.h
> @@ -34,4 +34,31 @@ do {							\
>  	raw_spin_unlock(&desc->lock);			\
>  } while(0)
>  
> +#ifndef __ASSEMBLY__
> +static inline void chained_irq_enter(struct irq_chip *chip,
> +				     struct irq_desc *desc)
> +{
> +	/* FastEOI controllers require no action on entry. */
> +	if (chip->irq_eoi)
> +		return;
> +
> +	if (chip->irq_mask_ack) {
> +		chip->irq_mask_ack(&desc->irq_data);
> +	} else {
> +		chip->irq_mask(&desc->irq_data);
> +		if (chip->irq_ack)
> +			chip->irq_ack(&desc->irq_data);
> +	}
> +}
> +
> +static inline void chained_irq_exit(struct irq_chip *chip,
> +				    struct irq_desc *desc)
> +{
> +	if (chip->irq_eoi)
> +		chip->irq_eoi(&desc->irq_data);
> +	else
> +		chip->irq_unmask(&desc->irq_data);
> +}
> +#endif
> +
>  #endif
> -- 
> 1.7.0.4
> 

[PATCH 1/7] ARM: irq: introduce entry and exit functions for chained handlers

[Will Deacon]

> On Tue, 8 Mar 2011, Will Deacon wrote:
> 
> > Some chained IRQ handlers are written to cope with primary chips of
> > potentially different flow types. Whether this a sensible thing to do
> > is a point of contention.
> 
> That wants a comment that these functions are only dealing with
> fasteoi and level type flow control.
> 
> Otherwise fine with me. Feel free to add my Acked-by.

Thanks Thomas, reworded as followed:

    ARM: irq: introduce entry and exit functions for chained handlers
    
    Some chained IRQ handlers are written to cope with primary chips of
    potentially different flow types. Whether this a sensible thing to do
    is a point of contention.
    
    This patch introduces entry/exit functions for chained handlers which
    infer the flow type of the primary chip as fasteoi or level-type by
    checking whether or not the ->irq_eoi function pointer is present and
    calling back to the primary chip as necessary. Other methods of flow
    control are not considered.

I'll add your Ack and put this (patch 1) in Russell's patch system next
week.

Will

[PATCH 1/7] ARM: irq: introduce entry and exit functions for chained handlers

[Thomas Gleixner]

On Fri, 11 Mar 2011, Will Deacon wrote:

> > On Tue, 8 Mar 2011, Will Deacon wrote:
> > 
> > > Some chained IRQ handlers are written to cope with primary chips of
> > > potentially different flow types. Whether this a sensible thing to do
> > > is a point of contention.
> > 
> > That wants a comment that these functions are only dealing with
> > fasteoi and level type flow control.
> > 
> > Otherwise fine with me. Feel free to add my Acked-by.
> 
> Thanks Thomas, reworded as followed:
> 
>     ARM: irq: introduce entry and exit functions for chained handlers
>     
>     Some chained IRQ handlers are written to cope with primary chips of
>     potentially different flow types. Whether this a sensible thing to do
>     is a point of contention.
>     
>     This patch introduces entry/exit functions for chained handlers which
>     infer the flow type of the primary chip as fasteoi or level-type by
>     checking whether or not the ->irq_eoi function pointer is present and
>     calling back to the primary chip as necessary. Other methods of flow
>     control are not considered.
> 
> I'll add your Ack and put this (patch 1) in Russell's patch system next
> week.

Having it in the changelog is nice, but the code itself would like a
comment as well.

Thanks,

	tglx

[PATCH 1/7] ARM: irq: introduce entry and exit functions for chained handlers

[Will Deacon]

> > > That wants a comment that these functions are only dealing with
> > > fasteoi and level type flow control.
> > >
> > > Otherwise fine with me. Feel free to add my Acked-by.
> >
> > Thanks Thomas, reworded as followed:
> >
> >     ARM: irq: introduce entry and exit functions for chained handlers
> >
> >     Some chained IRQ handlers are written to cope with primary chips of
> >     potentially different flow types. Whether this a sensible thing to do
> >     is a point of contention.
> >
> >     This patch introduces entry/exit functions for chained handlers which
> >     infer the flow type of the primary chip as fasteoi or level-type by
> >     checking whether or not the ->irq_eoi function pointer is present and
> >     calling back to the primary chip as necessary. Other methods of flow
> >     control are not considered.
> >
> > I'll add your Ack and put this (patch 1) in Russell's patch system next
> > week.
> 
> Having it in the changelog is nice, but the code itself would like a
> comment as well.

Rightio, submitted to Russell's patch system with code comment as 6806/1.

Thanks,

Will