From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 98D22C48BF6 for ; Thu, 29 Feb 2024 09:28:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:CC:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=10iQnYZANY4R7JeiQ2tYFfyyuK3DVf9Jnx7T/TfWIDw=; b=Qg+iLN+iyG/ksc oHCQ3/BoJ9kwjtea+fjpQSg2C8czhezfX4A5qgiIIXQVyP64tPsVTbZMAKHqy7DRbLwAvDRGPCyOV 9GYEfP4CoqQvm4XlRinN5OT1dLypBemnqDlJE4OvfJNAoEAeaN1ncYONhBilFIPNemwOZcJZb4/zK orr5iwhvZGw7xtBo4570UelYqqRung9GbR1DjI+v+7mZnSZ3HGD3QsKL7TbIjT8XJ7xJNijQ4eZa7 EHnuc5qFmCBN4OlQigxbX7wHCeWCYv01Kqee1QW7Efg+Mkojlgh8FExpp4PxIoL2HFG6WO5HI9m89 OWua41lEy0FW+lhj6xrA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rfci1-0000000CtNG-1pxK; Thu, 29 Feb 2024 09:28:09 +0000 Received: from fllv0016.ext.ti.com ([198.47.19.142]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rfchy-0000000CtMG-3tsd for linux-arm-kernel@lists.infradead.org; Thu, 29 Feb 2024 09:28:08 +0000 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 41T9RoZe012078; Thu, 29 Feb 2024 03:27:50 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1709198870; bh=GzKfgPrCzPpYr7lfuwIgLdFgDGketk3AdQD7tugAgqU=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=W8YMYZFACerPlpM5giQNVGU4rBqte6vfifJMRl01jPHMQjUCLYx3e4bsbL/bCYrZ+ bf2v1pieqHH8jIuVUEiechrmpsfn7Xnn4QwjmgaAcfs0YlGwuvJTVJ/NbhEHNtMDQr 4HJjLPPuZW0HFuR5/STT+E/YINQ7kzKHuQgOO+40= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 41T9RoYu074642 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 29 Feb 2024 03:27:50 -0600 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 29 Feb 2024 03:27:49 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 29 Feb 2024 03:27:49 -0600 Received: from localhost (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41T9RnMl089761; Thu, 29 Feb 2024 03:27:49 -0600 Date: Thu, 29 Feb 2024 14:57:48 +0530 From: Siddharth Vadapalli To: Andrew Lunn CC: Siddharth Vadapalli , Jiri Pirko , , , , , , , , , , , , , , Subject: Re: [PATCH net-next] net: ethernet: ti: am65-cpsw: Add priv-flag for Switch VLAN Aware mode Message-ID: <0004e3d5-0f62-49dc-b51f-5a302006c303@ti.com> References: <20240227082815.2073826-1-s-vadapalli@ti.com> <7d1496da-100a-4336-b744-33e843eba930@ti.com> <49e531f7-9465-40ea-b604-22a3a7f13d62@ti.com> <10287788-614a-4eef-9c9c-a0ef4039b78f@lunn.ch> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <10287788-614a-4eef-9c9c-a0ef4039b78f@lunn.ch> X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240229_012807_096523_60C4B555 X-CRM114-Status: GOOD ( 15.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Feb 28, 2024 at 02:36:55PM +0100, Andrew Lunn wrote: > > What if there is no kernel behavior associated with it? How can it be mimicked > > then? > > Simple. Implement the feature in software in the kernel for > everybody. Then offload it to your hardware. > > Your hardware is an accelerator. You use it to accelerate what linux > can already do. If Linux does not have the feature your accelerator > has, that accelerator feature goes unused. Is it acceptable to have a macro in the Ethernet Driver to conditionally disable/enable the feature (via setting the corresponding bit in the register)? The current implementation is: /* Control register */ writel(AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE | AM65_CPSW_CTL_VLAN_AWARE | AM65_CPSW_CTL_P0_RX_PAD, common->cpsw_base + AM65_CPSW_REG_CTL); which sets the "AM65_CPSW_CTL_VLAN_AWARE" bit by default. Could it be changed to: #define TI_K3_CPSW_VLAN_AWARE 1 .... /* Control register */ val = AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE | AM65_CPSW_CTL_P0_RX_PAD; #ifdef TI_K3_CPSW_VLAN_AWARE val |= AM65_CPSW_CTL_VLAN_AWARE; #endif writel(val, common->cpsw_base + AM65_CPSW_REG_CTL); Since no additional configuration is necessary to disable/enable the functionality except clearing/setting a bit in a register, I am unsure of the implementation for the offloading part being suggested. Please let me know if the above implementation is an acceptable alternative. Regards, Siddharth. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel