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Mon, 18 Aug 2025 08:54:31 +0000 (GMT) From: "Shradha Todi" To: "'Krzysztof Kozlowski'" , , , , , , Cc: , , , , , , , , , , , , , , In-Reply-To: Subject: RE: [PATCH v3 12/12] arm64: dts: fsd: Add PCIe support for Tesla FSD SoC Date: Mon, 18 Aug 2025 14:24:30 +0530 Message-ID: <000b01dc101d$b834db40$289e91c0$@samsung.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQHWPHKmIG2WTsjb/5pkHKJ2GfeRPwIotln8AZEe0jECYiuDgLRC4i+g Content-Language: en-in X-CMS-MailID: 20250818085434epcas5p23546464f6d2642c74d42db7b134d8aec X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250811154746epcas5p261ba0c811f9dd8748f8f241b76be6525 References: <20250811154638.95732-1-shradha.t@samsung.com> <20250811154638.95732-13-shradha.t@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250818_101847_904879_7CCA276A X-CRM114-Status: GOOD ( 11.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org > > +&pcieep2 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pcie1_clkreq>, <&pcie1_wake>, <&pcie1_preset>, > > + <&pcie0_slot1>; > > +}; > > + > > +&pcierc0 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pcie0_clkreq>, <&pcie0_wake0>, <&pcie0_preset0>, > > + <&pcie0_slot0>; > > +}; > > + > > +&pcieep0 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pcie0_clkreq>, <&pcie0_wake0>, <&pcie0_preset0>, > > + <&pcie0_slot0>; > > +}; > > + > > +&pcierc1 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pcie0_clkreq>, <&pcie0_wake1>, <&pcie0_preset0>; > > +}; > > + > > +&pcieep1 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pcie0_clkreq>, <&pcie0_wake1>, <&pcie0_preset0>; > > > All these are pointless, because the node is disabled. The board level > should be complete, so also supplies and enabling the device. > I will enable required nodes. Had enabled while testing but missed to add in patch. Though all nodes will not be enabled as it is a dual-mode controller and cannot run as both RC and EP at the same time. > Best regards, > Krzysztof