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From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/5] arm/oprofile: reserve the PMU when starting
Date: Mon, 14 Dec 2009 16:04:25 -0000	[thread overview]
Message-ID: <000f01ca7cd7$1c073e10$5415ba30$@deacon@arm.com> (raw)
In-Reply-To: <1260799481-29951-3-git-send-email-jamie.iles@picochip.com>

* Jamie Iles wrote:

> Make sure that we have access to the performance counters and
> that they aren't being used by perf events or anything else.
>
> diff --git a/arch/arm/oprofile/op_model_v6.c b/arch/arm/oprofile/op_model_v6.c
> index e468017..a22357a 100644
> --- a/arch/arm/oprofile/op_model_v6.c
> +++ b/arch/arm/oprofile/op_model_v6.c
> @@ -19,42 +19,47 @@
>  /* #define DEBUG */
>  #include <linux/types.h>
>  #include <linux/errno.h>
> +#include <linux/err.h>
>  #include <linux/sched.h>
>  #include <linux/oprofile.h>
>  #include <linux/interrupt.h>
>  #include <asm/irq.h>
>  #include <asm/system.h>
> +#include <asm/pmu.h>
> 
>  #include "op_counter.h"
>  #include "op_arm_model.h"
>  #include "op_model_arm11_core.h"
> 
> -static int irqs[] = {
> -#ifdef CONFIG_ARCH_OMAP2
> -	3,
> -#endif
> -#ifdef CONFIG_ARCH_BCMRING
> -	IRQ_PMUIRQ, /* for BCMRING, ARM PMU interrupt is 43 */
> -#endif
> -#ifdef CONFIG_ARCH_PC3XX
> -        IRQ_NPMUIRQ,
> -#endif
<snip>

These last three lines don't apply cleanly.
I think you've based this patch on top of your previous one.

Will

  parent reply	other threads:[~2009-12-14 16:04 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-12-14 14:04 ARMv6 performance counters v2 Jamie Iles
2009-12-14 14:04 ` [PATCH 1/5] arm: provide a mechanism to reserve performance counters Jamie Iles
2009-12-14 14:04   ` [PATCH 2/5] arm/oprofile: reserve the PMU when starting Jamie Iles
2009-12-14 14:04     ` [PATCH 3/5] arm: use the spinlocked, generic atomic64 support Jamie Iles
2009-12-14 14:04       ` [PATCH 4/5] arm: enable support for software perf events Jamie Iles
2009-12-14 14:04         ` [PATCH 5/5] arm/perfevents: implement perf event support for ARMv6 Jamie Iles
2009-12-14 16:12           ` Jean Pihet
2009-12-14 16:33             ` Jamie Iles
2009-12-14 16:57               ` Jean Pihet
2009-12-14 17:09             ` Will Deacon
2009-12-14 16:13           ` Will Deacon
2009-12-14 16:20             ` Jamie Iles
2009-12-14 16:24               ` Will Deacon
2009-12-14 17:38       ` [PATCH 3/5] arm: use the spinlocked, generic atomic64 support Nicolas Pitre
2009-12-14 19:36         ` Will Deacon
     [not found]         ` <001301ca7cf4$c04481a0$40cd84e0$%deacon@arm.com>
2009-12-14 19:52           ` Nicolas Pitre
2009-12-15 10:24             ` Catalin Marinas
2009-12-14 16:01     ` [PATCH 2/5] arm/oprofile: reserve the PMU when starting Jean Pihet
2009-12-14 16:04     ` Will Deacon [this message]
2009-12-14 16:10       ` Jamie Iles
2009-12-14 14:39   ` [PATCH 1/5] arm: provide a mechanism to reserve performance counters Will Deacon
2009-12-14 15:03     ` Jamie Iles
2009-12-14 16:01   ` Jean Pihet
  -- strict thread matches above, loose matches on Subject: below --
2009-12-15 11:15 ARMv6 performance counters v3 Jamie Iles
2009-12-15 11:15 ` [PATCH 1/5] arm: provide a mechanism to reserve performance counters Jamie Iles
2009-12-15 11:15   ` [PATCH 2/5] arm/oprofile: reserve the PMU when starting Jamie Iles
2010-01-04 10:48 ARM perf events support v4 Jamie Iles
2010-01-04 10:48 ` [PATCH 1/5] arm: provide a mechanism to reserve performance counters Jamie Iles
2010-01-04 10:48   ` [PATCH 2/5] arm/oprofile: reserve the PMU when starting Jamie Iles
2010-01-14 12:14 ARM perf events support v5 Jamie Iles
2010-01-14 12:14 ` [PATCH 1/5] arm: provide a mechanism to reserve performance counters Jamie Iles
2010-01-14 12:14   ` [PATCH 2/5] arm/oprofile: reserve the PMU when starting Jamie Iles
2010-02-05  6:01     ` George G. Davis
2010-02-05  9:13       ` Jamie Iles

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