[PATCH] S5PV210 Correct clock register properties

[kgene.kim@samsung.com (Kukjin Kim)]

MyungJoo Ham wrote:
> 
> From: MyungJoo Ham <myungJoo.ham@samsung.com>
> 
> Corrected shift values of I2S and UART clocks (CLK_GATE_IP3).
> 
> I2S (CLK_GATE_IP3) and UART (CLK_GATE_IP3) had wrong register shift
> values, which in turn, made them turn on and off wrong clocks.

(snip)

Sorry..kindly ignore below comments.
My mistake..

---
Your point is right..but your updated code was wrong :-(

Should be like below.

@@ -400,19 +400,19 @@ static struct clk init_clocks_disable[] = {
 		.id		= 0,
 		.parent		= &clk_p,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<4),
+		.ctrlbit	= (1 << 4),
 	}, {
 		.name		= "i2s_v32",
 		.id		= 0,
 		.parent		= &clk_p,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<4),
+		.ctrlbit	= (1 << 5),
 	}, {
 		.name		= "i2s_v32",
 		.id		= 1,
 		.parent		= &clk_p,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<4),
+		.ctrlbit	= (1 << 6),
---

(snip)


Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.