From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/5] arm: provide a mechanism to reserve performance counters
Date: Thu, 17 Dec 2009 16:14:22 -0000 [thread overview]
Message-ID: <001101ca7f33$fe8ddc90$fba995b0$@deacon@arm.com> (raw)
In-Reply-To: <1260875712-29712-2-git-send-email-jamie.iles@picochip.com>
Hi Jamie,
Just a small thing I noticed with the PMU reservation:
*Jamie Iles wrote:
> diff --git a/arch/arm/kernel/pmu.c b/arch/arm/kernel/pmu.c
> new file mode 100644
> index 0000000..3a178bb
> --- /dev/null
> +++ b/arch/arm/kernel/pmu.c
<snip>
> +static const int irqs[] = {
> +#ifdef CONFIG_ARCH_PC3XX
> + IRQ_NPMUIRQ,
> +#elif defined(CONFIG_ARCH_OMAP2)
> + 3,
> +#elif defined(CONFIG_ARCH_BCMRING)
> + IRQ_PMUIRQ,
> +#elif defined(CONFIG_MACH_REALVIEW_EB)
> + IRQ_EB11MP_PMU_CPU0,
> + IRQ_EB11MP_PMU_CPU1,
> + IRQ_EB11MP_PMU_CPU2,
> + IRQ_EB11MP_PMU_CPU3,
> +#elif defined(CONFIG_ARCH_OMAP3)
> + INT_34XX_BENCH_MPU_EMUL,
> +#elif defined(CONFIG_ARCH_IOP32X)
> + IRQ_IOP32X_CORE_PMU,
> +#elif defined(CONFIG_ARCH_IOP33X)
> + IRQ_IOP33X_CORE_PMU,
> +#elif defined(CONFIG_ARCH_PXA)
> + IRQ_PMU,
> +#endif
> +};
> +
> +static const struct pmu_irqs pmu_irqs = {
> + .irqs = irqs,
> + .num_irqs = ARRAY_SIZE(irqs),
> +};
> +
> +static DECLARE_MUTEX(pmu_mutex);
> +
> +const struct pmu_irqs *
> +reserve_pmu(void)
> +{
> + int ret = down_trylock(&pmu_mutex) ? -EBUSY : 0;
> +
> + return ret ? ERR_PTR(ret) : &pmu_irqs;
> +}
I think it would be sensible to return an error (-ENODEV) if
pmu_irqs.num_irqs == 0. Not doing so can cause applications
to fail silently when they are running on unsupported boards.
Will
next prev parent reply other threads:[~2009-12-17 16:14 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-12-15 11:15 ARMv6 performance counters v3 Jamie Iles
2009-12-15 11:15 ` [PATCH 1/5] arm: provide a mechanism to reserve performance counters Jamie Iles
2009-12-15 11:15 ` [PATCH 2/5] arm/oprofile: reserve the PMU when starting Jamie Iles
2009-12-15 11:15 ` [PATCH 3/5] arm: use the spinlocked, generic atomic64 support Jamie Iles
2009-12-15 11:15 ` [PATCH 4/5] arm: enable support for software perf events Jamie Iles
2009-12-15 11:15 ` [PATCH 5/5] arm/perfevents: implement perf event support for ARMv6 Jamie Iles
2009-12-15 14:29 ` Will Deacon
2009-12-15 15:02 ` Jamie Iles
2009-12-15 15:05 ` Will Deacon
2009-12-15 15:19 ` Jamie Iles
2009-12-15 15:30 ` Peter Zijlstra
2009-12-15 15:36 ` Jamie Iles
2009-12-16 10:54 ` Jamie Iles
2009-12-16 11:04 ` Will Deacon
2009-12-16 11:19 ` Jamie Iles
2009-12-18 17:05 ` Perf Event support for ARMv7 (was: Re: [PATCH 5/5] arm/perfevents: implement perf event support for ARMv6) Jean Pihet
2009-12-19 10:29 ` Jamie Iles
2009-12-19 10:53 ` Ingo Molnar
2009-12-21 11:32 ` Jean Pihet
2009-12-21 11:29 ` Jean Pihet
2009-12-21 11:04 ` Will Deacon
2009-12-21 11:43 ` Jean Pihet
2009-12-21 12:10 ` Will Deacon
2009-12-21 12:43 ` Jamie Iles
2009-12-21 13:35 ` Jean Pihet
2009-12-22 16:51 ` Jean Pihet
2009-12-28 7:57 ` Ingo Molnar
2009-12-29 13:52 ` Jean Pihet
2009-12-29 16:32 ` Jamie Iles
2010-01-06 15:16 ` Michał Nazarewicz
2010-01-06 15:30 ` Jamie Iles
2010-01-07 17:02 ` Michał Nazarewicz
2009-12-29 13:58 ` Jean Pihet
2010-01-04 16:52 ` Will Deacon
2010-01-15 15:30 ` Jean Pihet
2010-01-15 15:39 ` Jamie Iles
2010-01-15 15:43 ` Jean Pihet
2010-01-15 15:49 ` Jamie Iles
2010-01-20 13:40 ` Will Deacon
2010-01-08 22:17 ` Woodruff, Richard
2010-01-15 15:34 ` Jean Pihet
2009-12-15 14:13 ` [PATCH 1/5] arm: provide a mechanism to reserve performance counters Will Deacon
2009-12-15 14:36 ` Jamie Iles
2009-12-15 17:06 ` Will Deacon
2009-12-17 16:14 ` Will Deacon [this message]
2009-12-17 16:27 ` Jamie Iles
-- strict thread matches above, loose matches on Subject: below --
2010-01-14 12:14 ARM perf events support v5 Jamie Iles
2010-01-14 12:14 ` [PATCH 1/5] arm: provide a mechanism to reserve performance counters Jamie Iles
2010-01-21 9:30 ` Jamie Iles
2010-01-04 10:48 ARM perf events support v4 Jamie Iles
2010-01-04 10:48 ` [PATCH 1/5] arm: provide a mechanism to reserve performance counters Jamie Iles
2010-01-06 12:00 ` Michał Nazarewicz
2010-01-06 12:15 ` Jamie Iles
2009-12-14 14:04 ARMv6 performance counters v2 Jamie Iles
2009-12-14 14:04 ` [PATCH 1/5] arm: provide a mechanism to reserve performance counters Jamie Iles
2009-12-14 14:39 ` Will Deacon
2009-12-14 15:03 ` Jamie Iles
2009-12-14 16:01 ` Jean Pihet
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='001101ca7f33$fe8ddc90$fba995b0$@deacon@arm.com' \
--to=will.deacon@arm.com \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).