From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/5] arm: use the spinlocked, generic atomic64 support
Date: Mon, 14 Dec 2009 19:36:36 -0000 [thread overview]
Message-ID: <001301ca7cf4$c04481a0$40cd84e0$@deacon@arm.com> (raw)
In-Reply-To: <alpine.LFD.2.00.0912141156200.23173@xanadu.home>
Hi Nicolas,
*Nicolas Pitre wrote:
> Can't a variant of include/linux/cnt32_to_63.h be used here?>
> typedef struct {
> atomic_t low;
> u32 high;
> } atomic64_t;
>
> static inline void atomic64_set(atomic64_t *ptr, u64 new_val)
> {
> u32 low = new_val;
> u32 high = new_val >> 32;
> BUG_ON(high & 0x80000000);
> atomic_set(&ptr->low, low);
> ptr->high = (high & 0x7fffffff) | (low & 0x80000000);
> }
How do you ensure that this is atomic? To me it looks like one CPU
could write the lower 32-bits and another could write the upper 32,
leaving the memory location in an inconsistent state.
> static inline u64 atomic64_read(atomic64_t *ptr)
> {
> u32 high, low;
> high = ptr->high;
> smp_rmb();
> low = atomic_read(&ptr->low);
> if (unlikely((s32)(high ^ low) < 0))
> ptr->high = high = (high ^ 0x80000000) + (high >> 31);
> return ((u64)(high & 0x7fffffff) << 32) | low;
> }
>
> static inline u64 atomic64_inc_return(atomic64_t *ptr)
> {
> atomic_inc(&ptr->low);
> return atomic64_read(ptr);
> }
>
> The atomic64_add_return() could be implemented the same way, however the
> added value would have to be smaller than 31 bits for the algorythm to
> work.
I posted a patch to this list on Friday which provides 64-bit atomic
operations for ARM using exclusive loads and stores:
http://lists.infradead.org/pipermail/linux-arm-kernel/2009-December/005934.html
Once this patch has been successfully reviewed, these routines should be used
instead. For now it makes sense to use the generic spinlocks version as a
placeholder.
Will
next prev parent reply other threads:[~2009-12-14 19:36 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-12-14 14:04 ARMv6 performance counters v2 Jamie Iles
2009-12-14 14:04 ` [PATCH 1/5] arm: provide a mechanism to reserve performance counters Jamie Iles
2009-12-14 14:04 ` [PATCH 2/5] arm/oprofile: reserve the PMU when starting Jamie Iles
2009-12-14 14:04 ` [PATCH 3/5] arm: use the spinlocked, generic atomic64 support Jamie Iles
2009-12-14 14:04 ` [PATCH 4/5] arm: enable support for software perf events Jamie Iles
2009-12-14 14:04 ` [PATCH 5/5] arm/perfevents: implement perf event support for ARMv6 Jamie Iles
2009-12-14 16:12 ` Jean Pihet
2009-12-14 16:33 ` Jamie Iles
2009-12-14 16:57 ` Jean Pihet
2009-12-14 17:09 ` Will Deacon
2009-12-14 16:13 ` Will Deacon
2009-12-14 16:20 ` Jamie Iles
2009-12-14 16:24 ` Will Deacon
2009-12-14 17:38 ` [PATCH 3/5] arm: use the spinlocked, generic atomic64 support Nicolas Pitre
2009-12-14 19:36 ` Will Deacon [this message]
[not found] ` <001301ca7cf4$c04481a0$40cd84e0$%deacon@arm.com>
2009-12-14 19:52 ` Nicolas Pitre
2009-12-15 10:24 ` Catalin Marinas
2009-12-14 16:01 ` [PATCH 2/5] arm/oprofile: reserve the PMU when starting Jean Pihet
2009-12-14 16:04 ` Will Deacon
2009-12-14 16:10 ` Jamie Iles
2009-12-14 14:39 ` [PATCH 1/5] arm: provide a mechanism to reserve performance counters Will Deacon
2009-12-14 15:03 ` Jamie Iles
2009-12-14 16:01 ` Jean Pihet
-- strict thread matches above, loose matches on Subject: below --
2009-12-15 11:15 ARMv6 performance counters v3 Jamie Iles
2009-12-15 11:15 ` [PATCH 1/5] arm: provide a mechanism to reserve performance counters Jamie Iles
2009-12-15 11:15 ` [PATCH 2/5] arm/oprofile: reserve the PMU when starting Jamie Iles
2009-12-15 11:15 ` [PATCH 3/5] arm: use the spinlocked, generic atomic64 support Jamie Iles
2010-01-04 10:48 ARM perf events support v4 Jamie Iles
2010-01-04 10:48 ` [PATCH 1/5] arm: provide a mechanism to reserve performance counters Jamie Iles
2010-01-04 10:48 ` [PATCH 2/5] arm/oprofile: reserve the PMU when starting Jamie Iles
2010-01-04 10:48 ` [PATCH 3/5] arm: use the spinlocked, generic atomic64 support Jamie Iles
2010-01-05 18:57 ` Jamie Lokier
2010-01-05 19:08 ` Jamie Iles
2010-01-14 12:14 ARM perf events support v5 Jamie Iles
2010-01-14 12:14 ` [PATCH 1/5] arm: provide a mechanism to reserve performance counters Jamie Iles
2010-01-14 12:14 ` [PATCH 2/5] arm/oprofile: reserve the PMU when starting Jamie Iles
2010-01-14 12:14 ` [PATCH 3/5] arm: use the spinlocked, generic atomic64 support Jamie Iles
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