[patch v2 0/3] arm: pmu: support pmu/perf on OMAP4

[patch v2 0/3] arm: pmu: support pmu/perf on OMAP4

[tom.leiming at gmail.com]

Hi,

This patches support pmu irq routed from CTI, such as implemented
on OMAP4:

      - introduce some CTI helpers and registers' definition
      - introduce .enable_irq and .disable_irq into platform_data,
	so perf irq handler can handle irq correctly if it is
	routed from CTI on OMAP4
      - configure CTI on OMAP4 so that perf can work on OMAP4

The patches have been tested Ok on Pandaboard, and 'perf' does work
after applying them.

v2:
	- move cti related code out of perf_event.c
	- introduce .enable_irq and .disable_irq into platform_data
	as suggested by Will.

v1:
       - rebase the patch set against 2.6.38-rc6-next-20110301, fix
       conflicts, which is pointed out by Will Deacon

 arch/arm/include/asm/cti.h    |  177 +++++++++++++++++++++++++++++++++++++++++
 arch/arm/include/asm/pmu.h    |   15 +++-
 arch/arm/kernel/perf_event.c  |   15 +++-
 arch/arm/mach-omap2/dbg44xx.h |   18 ++++
 arch/arm/mach-omap2/devices.c |   83 ++++++++++++++++++-
 5 files changed, 299 insertions(+), 9 deletions(-)

thanks,
--
Lei Ming

[patch v2 1/3] arm: introduce cross trigger interface helpers

[tom.leiming at gmail.com]

From: Ming Lei <tom.leiming@gmail.com>

OMAP4 uses cross trigger interface(CTI) to route
performance monitor irq to GIC, so introduce cti
helpers to make access for cti easily.

Signed-off-by: Ming Lei <tom.leiming@gmail.com>
---
 arch/arm/include/asm/cti.h |  177 ++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 177 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/cti.h

diff --git a/arch/arm/include/asm/cti.h b/arch/arm/include/asm/cti.h
new file mode 100644
index 0000000..c9addd3
--- /dev/null
+++ b/arch/arm/include/asm/cti.h
@@ -0,0 +1,177 @@
+/*
+ *  arch/arm/include/asm/cti.h
+ */
+#ifndef __ASMARM_CTI_H
+#define __ASMARM_CTI_H
+
+#include	<asm/io.h>
+
+/*The registers' definition is from section 3.2 of
+ * 	Embedded Cross Trigger Revision: r0p0
+ **/
+#define		CTICONTROL		0x000
+#define		CTISTATUS		0x004
+#define		CTILOCK			0x008
+#define		CTIPROTECTION		0x00C
+#define		CTIINTACK		0x010
+#define		CTIAPPSET		0x014
+#define		CTIAPPCLEAR		0x018
+#define		CTIAPPPULSE		0x01c
+#define		CTIINEN			0x020
+#define		CTIOUTEN		0x0A0
+#define		CTITRIGINSTATUS		0x130
+#define		CTITRIGOUTSTATUS	0x134
+#define		CTICHINSTATUS		0x138
+#define		CTICHOUTSTATUS		0x13c
+#define		CTIPERIPHID0		0xFE0
+#define		CTIPERIPHID1		0xFE4
+#define		CTIPERIPHID2		0xFE8
+#define		CTIPERIPHID3		0xFEC
+#define		CTIPCELLID0		0xFF0
+#define		CTIPCELLID1		0xFF4
+#define		CTIPCELLID2		0xFF8
+#define		CTIPCELLID3		0xFFC
+
+/*The two below are from section 3.6.4 of
+ * 	CoreSight v1.0 Architecture Specification
+ **/
+#define		LOCKACCESS		0xFB0
+#define		LOCKSTATUS		0xFB4
+
+/**
+ * struct cti - cross trigger interface struct
+ * @base: mapped virtual address for the cti base
+ * @irq: irq number for the cti
+ * @trig_out_for_irq: triger out number which will cause
+ * 	the @irq happen
+ *
+ * cti struct used to operate cti registers.
+ */
+struct cti {
+	void *base;
+	int irq;
+	int trig_out_for_irq;
+};
+
+/**
+ * cti_init - initialize the cti instance
+ * @cti: cti instance
+ * @base: mapped virtual address for the cti base
+ * @irq: irq number for the cti
+ * @trig_out: triger out number which will cause
+ * 	the @irq happen
+ *
+ * called by machine code to pass the board dependent
+ * @base, @irq and @trig_out to cti.
+ */
+static inline void cti_init(struct cti *cti,
+	void *base, int irq, int trig_out)
+{
+	cti->base = base;
+	cti->irq  = irq;
+	cti->trig_out_for_irq = trig_out;
+}
+
+/**
+ * cti_map_trigger - use the @chan to map @trig_in to @trig_out
+ * @cti: cti instance
+ * @trig_in: trigger in number
+ * @trig_out: trigger out number
+ * @channel: channel number
+ *
+ * This function maps one trigger in of @trig_in to one trigger
+ * out of @trig_out using the channel @chan.
+ */
+static inline void cti_map_trigger(struct cti *cti,
+	int trig_in, int trig_out, int chan)
+{
+	void *base = cti->base;
+	unsigned long val;
+
+	val = __raw_readl(base + CTIINEN + trig_in * 4);
+	val |= 1 << chan;
+	__raw_writel(val, base + CTIINEN + trig_in * 4);
+
+	val = __raw_readl(base + CTIOUTEN + trig_out * 4);
+	val |= 1 << chan;
+	__raw_writel(val, base + CTIOUTEN + trig_out * 4);
+}
+
+/**
+ * cti_enable - enable the cti module
+ * @cti: cti instance
+ *
+ * enable the cti module
+ */
+static inline void cti_enable(struct cti *cti)
+{
+	__raw_writel(0x1, cti->base);
+}
+
+/**
+ * cti_disable - disable the cti module
+ * @cti: cti instance
+ *
+ * enable the cti module
+ */
+static inline void cti_disable(struct cti *cti)
+{
+	__raw_writel(0, cti->base);
+}
+
+/**
+ * cti_irq_ack - clear the cti irq
+ * @cti: cti instance
+ *
+ * clear the cti irq
+ */
+static inline void cti_irq_ack(struct cti *cti)
+{
+	void *base = cti->base;
+	unsigned long val;
+
+	val = __raw_readl(base + CTIINTACK);
+	val |= 1 << cti->trig_out_for_irq;
+	__raw_writel(val, base + CTIINTACK);
+}
+
+/**
+ * cti_unlock - unlock cti module
+ * @cti: cti instance
+ *
+ * unlock the cti module, or else any writes to the cti
+ * module is not allowed.
+ */
+static inline void cti_unlock(struct cti *cti)
+{
+	void *base = cti->base;
+	unsigned long val;
+
+	val = __raw_readl(base + LOCKSTATUS);
+
+	if (val & 1) {
+		val = 0xC5ACCE55;
+		__raw_writel(val, base + LOCKACCESS);
+	}
+}
+
+/**
+ * cti_unlock - lock cti module
+ * @cti: cti instance
+ *
+ * lock the cti module, so any writes to the cti
+ * module will be not allowed.
+ */
+static inline void cti_lock(struct cti *cti)
+{
+	void *base = cti->base;
+	unsigned long val;
+
+	val = __raw_readl(base + LOCKSTATUS);
+
+	if (!(val & 1)) {
+		val = ~0xC5ACCE55;
+		__raw_writel(val, base + LOCKACCESS);
+	}
+}
+#endif
-- 
1.7.3

[patch v2 2/3] arm: pmu: allow platform specifc irq enable/disable handling

[tom.leiming at gmail.com]

From: Ming Lei <tom.leiming@gmail.com>

This patch introduces .enable_irq and .disable_irq into
struct arm_pmu_platdata, so platform specific irq enablement
can be handled after request_irq, and platform specific irq
disablement can be handled before free_irq.

This patch is for support of  pmu irq routed from CTI on omap4.

Signed-off-by: Ming Lei <tom.leiming@gmail.com>
---
 arch/arm/include/asm/pmu.h   |   15 ++++++++++++---
 arch/arm/kernel/perf_event.c |   15 ++++++++++++---
 2 files changed, 24 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index 7544ce6..e50c542 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -22,13 +22,22 @@ enum arm_pmu_type {
 /*
  * struct arm_pmu_platdata - ARM PMU platform data
  *
- * @handle_irq: an optional handler which will be called from the interrupt and
- * passed the address of the low level handler, and can be used to implement
- * any platform specific handling before or after calling it.
+ * @handle_irq: an optional handler which will be called from the
+ * 	interrupt and passed the address of the low level handler,
+ * 	and can be used to implement any platform specific handling
+ * 	before or after calling it.
+ * @enable_irq: an optional handler which will be called after
+ * 	request_irq and be used to handle some platform specific
+ * 	irq enablement
+ * @disable_irq: an optional handler which will be called before
+ * 	free_irq and be used to handle some platform specific
+ * 	irq disablement
  */
 struct arm_pmu_platdata {
 	irqreturn_t (*handle_irq)(int irq, void *dev,
 				  irq_handler_t pmu_handler);
+	void (*enable_irq)(int irq);
+	void (*disable_irq)(int irq);
 };
 
 #ifdef CONFIG_CPU_HAS_PMU
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 22e194eb..61ff471 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -422,14 +422,18 @@ armpmu_reserve_hardware(void)
 			pr_warning("unable to request IRQ%d for ARM perf "
 				"counters\n", irq);
 			break;
-		}
+		} else if (plat->enable_irq)
+			plat->enable_irq(irq);
 	}
 
 	if (err) {
 		for (i = i - 1; i >= 0; --i) {
 			irq = platform_get_irq(pmu_device, i);
-			if (irq >= 0)
+			if (irq >= 0) {
+				if (plat->disable_irq)
+					plat->disable_irq(irq);
 				free_irq(irq, NULL);
+			}
 		}
 		release_pmu(pmu_device);
 		pmu_device = NULL;
@@ -442,11 +446,16 @@ static void
 armpmu_release_hardware(void)
 {
 	int i, irq;
+	struct arm_pmu_platdata *plat =
+		dev_get_platdata(&pmu_device->dev);
 
 	for (i = pmu_device->num_resources - 1; i >= 0; --i) {
 		irq = platform_get_irq(pmu_device, i);
-		if (irq >= 0)
+		if (irq >= 0) {
+			if (plat->disable_irq)
+				plat->disable_irq(irq);
 			free_irq(irq, NULL);
+		}
 	}
 	armpmu->stop();
 
-- 
1.7.3

[patch v2 2/3] arm: pmu: allow platform specifc irq enable/disable handling

[Will Deacon]

Hello,

> -----Original Message-----
> From: tom.leiming at gmail.com [mailto:tom.leiming at gmail.com]
> Sent: 02 March 2011 10:57
> To: linux at arm.linux.org.uk
> Cc: linux-arm-kernel at lists.infradead.org; Will Deacon; Ming Lei
> Subject: [patch v2 2/3] arm: pmu: allow platform specifc irq enable/disable handling
> 
> From: Ming Lei <tom.leiming@gmail.com>
> 
> This patch introduces .enable_irq and .disable_irq into
> struct arm_pmu_platdata, so platform specific irq enablement
> can be handled after request_irq, and platform specific irq
> disablement can be handled before free_irq.
> 
> This patch is for support of  pmu irq routed from CTI on omap4.
> 
> Signed-off-by: Ming Lei <tom.leiming@gmail.com>
> ---
>  arch/arm/include/asm/pmu.h   |   15 ++++++++++++---
>  arch/arm/kernel/perf_event.c |   15 ++++++++++++---
>  2 files changed, 24 insertions(+), 6 deletions(-)

[...]

Looks good to me. Unfortunately, I don't have an OMAP4 to test this
on (contributions welcome :) so I've just eyeballed the code:

Reviewed-by: Will Deacon <will.deacon@arm.com>

You'll need to wait for the ux500 stuff to be merged before you can
get this upstream (Linus W is handling the pull request afaik).

Will

[patch v2 2/3] arm: pmu: allow platform specifc irq enable/disable handling

[Ming Lei]

Hi Will,

2011/3/2 Will Deacon <will.deacon@arm.com>:
> Looks good to me. Unfortunately, I don't have an OMAP4 to test this
> on (contributions welcome :) so I've just eyeballed the code:
>
> Reviewed-by: Will Deacon <will.deacon@arm.com>
>
> You'll need to wait for the ux500 stuff to be merged before you can
> get this upstream (Linus W is handling the pull request afaik).

Thanks for your review, the ux500 stuff has been merged into -next
tree already, so this one may be into -next too.

thanks,
-- 
Lei Ming

[patch v2 2/3] arm: pmu: allow platform specifc irq enable/disable handling

[Will Deacon]

> Hi Will,

Hello,

> 2011/3/2 Will Deacon <will.deacon@arm.com>:
> > Looks good to me. Unfortunately, I don't have an OMAP4 to test this
> > on (contributions welcome :) so I've just eyeballed the code:
> >
> > Reviewed-by: Will Deacon <will.deacon@arm.com>
> >
> > You'll need to wait for the ux500 stuff to be merged before you can
> > get this upstream (Linus W is handling the pull request afaik).
> 
> Thanks for your review, the ux500 stuff has been merged into -next
> tree already, so this one may be into -next too.

Ok, that's great. I've just noticed that you've typoed the subject
line for the patch (s/specifc/specific/) so you might want to fix
that before Sergei spots it!

Will

[patch v2 3/3] arm: omap4: support pmu

[tom.leiming at gmail.com]

From: Ming Lei <tom.leiming@gmail.com>

This patch supports pmu irq routed from CTI, so
make pmu/perf working on OMAP4.

The idea is from Woodruff Richard in the disscussion
about "Oprofile on Pandaboard / Omap4" on pandaboard at googlegroups.com.

Cc: Woodruff Richard <r-woodruff2@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: linux-omap at vger.kernel.org
Signed-off-by: Ming Lei <tom.leiming@gmail.com>
---
 arch/arm/mach-omap2/dbg44xx.h |   18 +++++++++
 arch/arm/mach-omap2/devices.c |   83 +++++++++++++++++++++++++++++++++++++++-
 2 files changed, 98 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/mach-omap2/dbg44xx.h

diff --git a/arch/arm/mach-omap2/dbg44xx.h b/arch/arm/mach-omap2/dbg44xx.h
new file mode 100644
index 0000000..e447ad5
--- /dev/null
+++ b/arch/arm/mach-omap2/dbg44xx.h
@@ -0,0 +1,18 @@
+/*
+ * OMAP44xx on-chip debug support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
+ *     or "OMAP4430".
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_DBG44XX_H
+#define __ARCH_ARM_MACH_OMAP2_DBG44XX_H
+
+#define OMAP44XX_CTI0_BASE		0x54148000
+#define OMAP44XX_CTI1_BASE		0x54149000
+
+#endif
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index d216976..bae02d5 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -22,6 +22,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
 #include <asm/pmu.h>
+#include <asm/cti.h>
 
 #include <plat/tc.h>
 #include <plat/board.h>
@@ -35,6 +36,7 @@
 
 #include "mux.h"
 #include "control.h"
+#include "dbg44xx.h"
 
 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
 
@@ -322,20 +324,95 @@ static struct resource omap3_pmu_resource = {
 	.flags	= IORESOURCE_IRQ,
 };
 
+static struct resource omap4_pmu_resource[] = {
+	{
+		.start	= OMAP44XX_IRQ_CTI0,
+		.end	= OMAP44XX_IRQ_CTI0,
+		.flags	= IORESOURCE_IRQ,
+	},
+	{
+		.start	= OMAP44XX_IRQ_CTI1,
+		.end	= OMAP44XX_IRQ_CTI1,
+		.flags	= IORESOURCE_IRQ,
+	}
+};
+
 static struct platform_device omap_pmu_device = {
 	.name		= "arm-pmu",
 	.id		= ARM_PMU_DEVICE_CPU,
 	.num_resources	= 1,
 };
 
+static struct arm_pmu_platdata omap4_pmu_data;
+static struct cti omap4_cti[2];
+
+static void omap4_enable_cti(int irq)
+{
+	if (irq == OMAP44XX_IRQ_CTI0)
+		cti_enable(&omap4_cti[0]);
+	else if (irq == OMAP44XX_IRQ_CTI1)
+		cti_enable(&omap4_cti[1]);
+}
+
+static void omap4_disable_cti(int irq)
+{
+	if (irq == OMAP44XX_IRQ_CTI0)
+		cti_disable(&omap4_cti[0]);
+	else if (irq == OMAP44XX_IRQ_CTI1)
+		cti_disable(&omap4_cti[1]);
+}
+
+static irqreturn_t omap4_pmu_handler(int irq, void *dev, irq_handler_t handler)
+{
+	if (irq == OMAP44XX_IRQ_CTI0)
+		cti_irq_ack(&omap4_cti[0]);
+	else if (irq == OMAP44XX_IRQ_CTI1)
+		cti_irq_ack(&omap4_cti[1]);
+
+	return handler(irq, dev);
+}
+
+static void omap4_configure_pmu_irq(void)
+{
+	void *base0;
+	void *base1;
+
+	base0 = ioremap(OMAP44XX_CTI0_BASE, 4096);
+	base1 = ioremap(OMAP44XX_CTI1_BASE, 4096);
+	if (!base0 && !base1) {
+		pr_err("ioremap for omap4 CTI failed\n");
+		return;
+	}
+
+	/*configure CTI0 for pmu irq routing*/
+	cti_init(&omap4_cti[0], base0, OMAP44XX_IRQ_CTI0, 6);
+	cti_unlock(&omap4_cti[0]);
+	cti_map_trigger(&omap4_cti[0], 1, 6, 2);
+
+	/*configure CTI1 for pmu irq routing*/
+	cti_init(&omap4_cti[1], base1, OMAP44XX_IRQ_CTI1, 6);
+	cti_unlock(&omap4_cti[1]);
+	cti_map_trigger(&omap4_cti[1], 1, 6, 2);
+
+	omap4_pmu_data.handle_irq = omap4_pmu_handler;
+	omap4_pmu_data.enable_irq = omap4_enable_cti;
+	omap4_pmu_data.disable_irq = omap4_disable_cti;
+}
+
 static void omap_init_pmu(void)
 {
-	if (cpu_is_omap24xx())
+	if (cpu_is_omap24xx()) {
 		omap_pmu_device.resource = &omap2_pmu_resource;
-	else if (cpu_is_omap34xx())
+	} else if (cpu_is_omap34xx()) {
 		omap_pmu_device.resource = &omap3_pmu_resource;
-	else
+	} else if (cpu_is_omap44xx()) {
+		omap_pmu_device.resource = omap4_pmu_resource;
+		omap_pmu_device.num_resources = 2;
+		omap_pmu_device.dev.platform_data = &omap4_pmu_data;
+		omap4_configure_pmu_irq();
+	} else {
 		return;
+	}
 
 	platform_device_register(&omap_pmu_device);
 }
-- 
1.7.3

[patch v2 3/3] arm: omap4: support pmu

[Santosh Shilimkar]

Tom,
> -----Original Message-----
> From: linux-arm-kernel-bounces at lists.infradead.org [mailto:linux-
> arm-kernel-bounces at lists.infradead.org] On Behalf Of
> tom.leiming at gmail.com
> Sent: Wednesday, March 02, 2011 4:27 PM
> To: linux at arm.linux.org.uk
> Cc: Woodruff Richard; Tony Lindgren; Ming Lei; will.deacon at arm.com;
> linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org
> Subject: [patch v2 3/3] arm: omap4: support pmu
>
> From: Ming Lei <tom.leiming@gmail.com>
>
> This patch supports pmu irq routed from CTI, so
> make pmu/perf working on OMAP4.
>
> The idea is from Woodruff Richard in the disscussion
> about "Oprofile on Pandaboard / Omap4" on
> pandaboard at googlegroups.com.
>
> Cc: Woodruff Richard <r-woodruff2@ti.com>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: linux-omap at vger.kernel.org
> Signed-off-by: Ming Lei <tom.leiming@gmail.com>
> ---
Few comments.

>  arch/arm/mach-omap2/dbg44xx.h |   18 +++++++++
>  arch/arm/mach-omap2/devices.c |   83
> +++++++++++++++++++++++++++++++++++++++-
>  2 files changed, 98 insertions(+), 3 deletions(-)
>  create mode 100644 arch/arm/mach-omap2/dbg44xx.h
>
> diff --git a/arch/arm/mach-omap2/dbg44xx.h b/arch/arm/mach-
> omap2/dbg44xx.h
> new file mode 100644
> index 0000000..e447ad5
> --- /dev/null
> +++ b/arch/arm/mach-omap2/dbg44xx.h
> @@ -0,0 +1,18 @@
> +/*
> + * OMAP44xx on-chip debug support
> + *
> + * This program is free software; you can redistribute it and/or
> modify
> + * it under the terms of the GNU General Public License version 2
> as
> + * published by the Free Software Foundation.
> + *
> + * XXX This file needs to be updated to align on one of "OMAP4",
> "OMAP44XX",
> + *     or "OMAP4430".
> + */
> +
> +#ifndef __ARCH_ARM_MACH_OMAP2_DBG44XX_H
> +#define __ARCH_ARM_MACH_OMAP2_DBG44XX_H
> +
> +#define OMAP44XX_CTI0_BASE		0x54148000
> +#define OMAP44XX_CTI1_BASE		0x54149000
> +
> +#endif
You don't need this file. Move this base addresses to
arch/arm/plat-omap/include/plat/omap44xx.h

> diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-
> omap2/devices.c
> index d216976..bae02d5 100644
> --- a/arch/arm/mach-omap2/devices.c
> +++ b/arch/arm/mach-omap2/devices.c
> @@ -22,6 +22,7 @@
>  #include <asm/mach-types.h>
>  #include <asm/mach/map.h>
>  #include <asm/pmu.h>
> +#include <asm/cti.h>
>
>  #include <plat/tc.h>
>  #include <plat/board.h>
> @@ -35,6 +36,7 @@
>
>  #include "mux.h"
>  #include "control.h"
> +#include "dbg44xx.h"
>
>  #if defined(CONFIG_VIDEO_OMAP2) ||
> defined(CONFIG_VIDEO_OMAP2_MODULE)
>
> @@ -322,20 +324,95 @@ static struct resource omap3_pmu_resource = {
>  	.flags	= IORESOURCE_IRQ,
>  };
>
> +static struct resource omap4_pmu_resource[] = {
> +	{
> +		.start	= OMAP44XX_IRQ_CTI0,
> +		.end	= OMAP44XX_IRQ_CTI0,
> +		.flags	= IORESOURCE_IRQ,
> +	},
> +	{
> +		.start	= OMAP44XX_IRQ_CTI1,
> +		.end	= OMAP44XX_IRQ_CTI1,
> +		.flags	= IORESOURCE_IRQ,
> +	}
> +};
> +
>  static struct platform_device omap_pmu_device = {
>  	.name		= "arm-pmu",
>  	.id		= ARM_PMU_DEVICE_CPU,
>  	.num_resources	= 1,
>  };
>
> +static struct arm_pmu_platdata omap4_pmu_data;
> +static struct cti omap4_cti[2];
> +
> +static void omap4_enable_cti(int irq)
> +{
> +	if (irq == OMAP44XX_IRQ_CTI0)
> +		cti_enable(&omap4_cti[0]);
> +	else if (irq == OMAP44XX_IRQ_CTI1)
> +		cti_enable(&omap4_cti[1]);
> +}
> +
> +static void omap4_disable_cti(int irq)
> +{
> +	if (irq == OMAP44XX_IRQ_CTI0)
> +		cti_disable(&omap4_cti[0]);
> +	else if (irq == OMAP44XX_IRQ_CTI1)
> +		cti_disable(&omap4_cti[1]);
> +}
> +
> +static irqreturn_t omap4_pmu_handler(int irq, void *dev,
> irq_handler_t handler)
> +{
> +	if (irq == OMAP44XX_IRQ_CTI0)
> +		cti_irq_ack(&omap4_cti[0]);
> +	else if (irq == OMAP44XX_IRQ_CTI1)
> +		cti_irq_ack(&omap4_cti[1]);
> +
> +	return handler(irq, dev);
> +}
> +
> +static void omap4_configure_pmu_irq(void)
> +{
> +	void *base0;
> +	void *base1;
s/ void *base/ void __iomem *base
> +
> +	base0 = ioremap(OMAP44XX_CTI0_BASE, 4096);
s/4096/SZ_4K
> +	base1 = ioremap(OMAP44XX_CTI1_BASE, 4096);
> +	if (!base0 && !base1) {
> +		pr_err("ioremap for omap4 CTI failed\n");
s/omap4/OMAP4
> +		return;
> +	}
> +
> +	/*configure CTI0 for pmu irq routing*/
> +	cti_init(&omap4_cti[0], base0, OMAP44XX_IRQ_CTI0, 6);
> +	cti_unlock(&omap4_cti[0]);
> +	cti_map_trigger(&omap4_cti[0], 1, 6, 2);
> +
> +	/*configure CTI1 for pmu irq routing*/
> +	cti_init(&omap4_cti[1], base1, OMAP44XX_IRQ_CTI1, 6);
> +	cti_unlock(&omap4_cti[1]);
> +	cti_map_trigger(&omap4_cti[1], 1, 6, 2);
> +
> +	omap4_pmu_data.handle_irq = omap4_pmu_handler;
> +	omap4_pmu_data.enable_irq = omap4_enable_cti;
> +	omap4_pmu_data.disable_irq = omap4_disable_cti;
> +}
> +
>  static void omap_init_pmu(void)
>  {
> -	if (cpu_is_omap24xx())
> +	if (cpu_is_omap24xx()) {
>  		omap_pmu_device.resource = &omap2_pmu_resource;
> -	else if (cpu_is_omap34xx())
> +	} else if (cpu_is_omap34xx()) {
>  		omap_pmu_device.resource = &omap3_pmu_resource;
> -	else
> +	} else if (cpu_is_omap44xx()) {
> +		omap_pmu_device.resource = omap4_pmu_resource;
> +		omap_pmu_device.num_resources = 2;
> +		omap_pmu_device.dev.platform_data = &omap4_pmu_data;
> +		omap4_configure_pmu_irq();
> +	} else {
>  		return;
> +	}
>
>  	platform_device_register(&omap_pmu_device);
>  }
> --
> 1.7.3
>
>
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