* [PATCH 0/3] add CPUCL0 clock support for exynosauto v920 SoC
[not found] <CGME20250418061515epcas2p1ddd9ec01dd5de8b238c77dcef14d745a@epcas2p1.samsung.com>
@ 2025-04-18 6:14 ` Shin Son
2025-04-18 6:14 ` [PATCH 1/3] dt-bindings: clock: exynosautov920: add cpucl0 clock definitions Shin Son
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Shin Son @ 2025-04-18 6:14 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi,
Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring,
Conor Dooley, Sunyeal Hong
Cc: Shin Son, linux-samsung-soc, linux-clk, devicetree,
linux-arm-kernel, linux-kernel
This patchset adds the CMU_CPUCL0 block to support exynosauto v920 SoC
Shin Son (3):
dt-bindings: clock: exynosautov920: add cpucl0 clock definitions
clk: samsung: exynosautov920: add cpucl0 clock support
arm64: dts: exynosautov920: add cpucl0 clock DT nodes
.../clock/samsung,exynosautov920-clock.yaml | 25 ++++
.../arm64/boot/dts/exynos/exynosautov920.dtsi | 15 ++
drivers/clk/samsung/clk-exynosautov920.c | 129 ++++++++++++++++++
.../clock/samsung,exynosautov920.h | 19 +++
4 files changed, 188 insertions(+)
--
2.49.0
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 1/3] dt-bindings: clock: exynosautov920: add cpucl0 clock definitions
2025-04-18 6:14 ` [PATCH 0/3] add CPUCL0 clock support for exynosauto v920 SoC Shin Son
@ 2025-04-18 6:14 ` Shin Son
2025-04-22 7:54 ` Krzysztof Kozlowski
2025-04-18 6:14 ` [PATCH 2/3] clk: samsung: exynosautov920: add cpucl0 clock support Shin Son
2025-04-18 6:15 ` [PATCH 3/3] arm64: dts: exynosautov920: add cpucl0 clock DT nodes Shin Son
2 siblings, 1 reply; 10+ messages in thread
From: Shin Son @ 2025-04-18 6:14 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi,
Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring,
Conor Dooley, Sunyeal Hong
Cc: Shin Son, linux-samsung-soc, linux-clk, devicetree,
linux-arm-kernel, linux-kernel
Add cpucl0 clock definitions.
Signed-off-by: Shin Son <shin.son@samsung.com>
---
.../clock/samsung,exynosautov920-clock.yaml | 25 +++++++++++++++++++
.../clock/samsung,exynosautov920.h | 19 ++++++++++++++
2 files changed, 44 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml
index 3330b2727474..d12b17c177df 100644
--- a/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml
@@ -8,6 +8,7 @@ title: Samsung ExynosAuto v920 SoC clock controller
maintainers:
- Sunyeal Hong <sunyeal.hong@samsung.com>
+ - Shin Son <shin.son@samsung.com>
- Chanwoo Choi <cw00.choi@samsung.com>
- Krzysztof Kozlowski <krzk@kernel.org>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
@@ -32,6 +33,7 @@ properties:
compatible:
enum:
- samsung,exynosautov920-cmu-top
+ - samsung,exynosautov920-cmu-cpucl0
- samsung,exynosautov920-cmu-peric0
- samsung,exynosautov920-cmu-peric1
- samsung,exynosautov920-cmu-misc
@@ -69,6 +71,29 @@ allOf:
items:
- const: oscclk
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,exynosautov920-cmu-cpucl0
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (38.4 MHz)
+ - description: CMU_CPUCL0 SWITCH clock (from CMU_TOP)
+ - description: CMU_CPUCL0 CLUSTER clock (from CMU_TOP)
+ - description: CMU_CPUCL0 DBG clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: switch
+ - const: cluster
+ - const: dbg
+
- if:
properties:
compatible:
diff --git a/include/dt-bindings/clock/samsung,exynosautov920.h b/include/dt-bindings/clock/samsung,exynosautov920.h
index 0c681f2ba3d0..c57a1d749700 100644
--- a/include/dt-bindings/clock/samsung,exynosautov920.h
+++ b/include/dt-bindings/clock/samsung,exynosautov920.h
@@ -162,6 +162,25 @@
#define DOUT_CLKCMU_TAA_NOC 146
#define DOUT_TCXO_DIV2 147
+/* CMU_CPUCL0 */
+#define CLK_FOUT_CPUCL0_PLL 1
+
+#define CLK_MOUT_PLL_CPUCL0 2
+#define CLK_MOUT_CPUCL0_CLUSTER_USER 3
+#define CLK_MOUT_CPUCL0_DBG_USER 4
+#define CLK_MOUT_CPUCL0_SWITCH_USER 5
+#define CLK_MOUT_CPUCL0_CLUSTER 6
+#define CLK_MOUT_CPUCL0_CORE 7
+
+#define CLK_DOUT_CLUSTER0_ACLK 8
+#define CLK_DOUT_CLUSTER0_ATCLK 9
+#define CLK_DOUT_CLUSTER0_MPCLK 10
+#define CLK_DOUT_CLUSTER0_PCLK 11
+#define CLK_DOUT_CLUSTER0_PERIPHCLK 12
+#define CLK_DOUT_CPUCL0_DBG_NOC 13
+#define CLK_DOUT_CPUCL0_DBG_PCLKDBG 14
+#define CLK_DOUT_CPUCL0_NOCP 15
+
/* CMU_PERIC0 */
#define CLK_MOUT_PERIC0_IP_USER 1
#define CLK_MOUT_PERIC0_NOC_USER 2
--
2.49.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/3] clk: samsung: exynosautov920: add cpucl0 clock support
2025-04-18 6:14 ` [PATCH 0/3] add CPUCL0 clock support for exynosauto v920 SoC Shin Son
2025-04-18 6:14 ` [PATCH 1/3] dt-bindings: clock: exynosautov920: add cpucl0 clock definitions Shin Son
@ 2025-04-18 6:14 ` Shin Son
2025-04-22 7:59 ` Krzysztof Kozlowski
2025-04-18 6:15 ` [PATCH 3/3] arm64: dts: exynosautov920: add cpucl0 clock DT nodes Shin Son
2 siblings, 1 reply; 10+ messages in thread
From: Shin Son @ 2025-04-18 6:14 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi,
Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring,
Conor Dooley, Sunyeal Hong
Cc: Shin Son, linux-samsung-soc, linux-clk, devicetree,
linux-arm-kernel, linux-kernel
Register compatible and cmu_info data to support clock CMU_CPUCL0,
this provides clock for CPUCL0_SWTICH/DBG/CLUSTER.
Signed-off-by: Shin Son <shin.son@samsung.com>
---
drivers/clk/samsung/clk-exynosautov920.c | 129 +++++++++++++++++++++++
1 file changed, 129 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynosautov920.c b/drivers/clk/samsung/clk-exynosautov920.c
index dc8d4240f6de..59e5f1e61151 100644
--- a/drivers/clk/samsung/clk-exynosautov920.c
+++ b/drivers/clk/samsung/clk-exynosautov920.c
@@ -18,6 +18,7 @@
/* NOTE: Must be equal to the last clock ID increased by one */
#define CLKS_NR_TOP (DOUT_CLKCMU_TAA_NOC + 1)
+#define CLKS_NR_CPUCL0 (CLK_DOUT_CLUSTER0_PERIPHCLK + 1)
#define CLKS_NR_PERIC0 (CLK_DOUT_PERIC0_I3C + 1)
#define CLKS_NR_PERIC1 (CLK_DOUT_PERIC1_I3C + 1)
#define CLKS_NR_MISC (CLK_DOUT_MISC_OSC_DIV2 + 1)
@@ -1005,6 +1006,134 @@ static void __init exynosautov920_cmu_top_init(struct device_node *np)
CLK_OF_DECLARE(exynosautov920_cmu_top, "samsung,exynosautov920-cmu-top",
exynosautov920_cmu_top_init);
+/* ---- CMU_CPUCL0 --------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_CPUCL0 (0x1EC00000) */
+#define PLL_LOCKTIME_PLL_CPUCL0 0x0000
+#define PLL_CON0_PLL_CPUCL0 0x0100
+#define PLL_CON1_PLL_CPUCL0 0x0104
+#define PLL_CON3_PLL_CPUCL0 0x010c
+#define PLL_CON0_MUX_CLKCMU_CPUCL0_CLUSTER_USER 0x0600
+#define PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER 0x0610
+#define PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER 0x0620
+
+#define CLK_CON_MUX_MUX_CLK_CPUCL0_CLUSTER 0x1000
+#define CLK_CON_MUX_MUX_CLK_CPUCL0_CORE 0x1004
+
+#define CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK 0x1800
+#define CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK 0x1804
+#define CLK_CON_DIV_DIV_CLK_CLUSTER0_MPCLK 0x1808
+#define CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK 0x180c
+#define CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK 0x1810
+#define CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC 0x181c
+#define CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG 0x1820
+#define CLK_CON_DIV_DIV_CLK_CPUCL0_NOCP 0x1824
+
+static const unsigned long cpucl0_clk_regs[] __initconst = {
+ PLL_LOCKTIME_PLL_CPUCL0,
+ PLL_CON0_PLL_CPUCL0,
+ PLL_CON1_PLL_CPUCL0,
+ PLL_CON3_PLL_CPUCL0,
+ PLL_CON0_MUX_CLKCMU_CPUCL0_CLUSTER_USER,
+ PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER,
+ PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER,
+ CLK_CON_MUX_MUX_CLK_CPUCL0_CLUSTER,
+ CLK_CON_MUX_MUX_CLK_CPUCL0_CORE,
+ CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK,
+ CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK,
+ CLK_CON_DIV_DIV_CLK_CLUSTER0_MPCLK,
+ CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK,
+ CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK,
+ CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC,
+ CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG,
+ CLK_CON_DIV_DIV_CLK_CPUCL0_NOCP,
+};
+
+/* List of parent clocks for Muxes in CMU_CPUCL0 */
+PNAME(mout_pll_cpucl0_p) = { "oscclk", "fout_cpucl0_pll" };
+PNAME(mout_cpucl0_cluster_user_p) = { "oscclk", "dout_clkcmu_cpucl0_cluster" };
+PNAME(mout_cpucl0_dbg_user_p) = { "oscclk", "dout_clkcmu_cpucl0_dbg" };
+PNAME(mout_cpucl0_switch_user_p) = { "oscclk", "dout_clkcmu_cpucl0_switch" };
+PNAME(mout_cpucl0_cluster_p) = { "oscclk", "mout_cpucl0_cluster_user",
+ "mout_cpucl0_switch_user"};
+PNAME(mout_cpucl0_core_p) = { "oscclk", "mout_pll_cpucl0",
+ "mout_cpucl0_switch_user"};
+
+static const struct samsung_pll_rate_table cpu_pll_rates[] __initconst = {
+ PLL_35XX_RATE(38400000U, 2400000000U, 250, 4, 0),
+ PLL_35XX_RATE(38400000U, 2304000000U, 240, 4, 0),
+ PLL_35XX_RATE(38400000U, 2208000000U, 230, 4, 0),
+ PLL_35XX_RATE(38400000U, 2112000000U, 220, 4, 0),
+ PLL_35XX_RATE(38400000U, 2016000000U, 210, 4, 0),
+ PLL_35XX_RATE(38400000U, 1824000000U, 190, 4, 0),
+ PLL_35XX_RATE(38400000U, 1680000000U, 175, 4, 0),
+ PLL_35XX_RATE(38400000U, 1344000000U, 140, 4, 0),
+ PLL_35XX_RATE(38400000U, 1152000000U, 120, 4, 0),
+ PLL_35XX_RATE(38400000U, 576000000U, 120, 4, 1),
+ PLL_35XX_RATE(38400000U, 288000000U, 120, 4, 2),
+};
+
+static const struct samsung_pll_clock cpucl0_pll_clks[] __initconst = {
+ /* CMU_CPUCL0_PURECLKCOMP */
+ PLL(pll_531x, CLK_FOUT_CPUCL0_PLL, "fout_cpucl0_pll", "oscclk",
+ PLL_LOCKTIME_PLL_CPUCL0, PLL_CON3_PLL_CPUCL0, cpu_pll_rates),
+};
+
+static const struct samsung_mux_clock cpucl0_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_PLL_CPUCL0, "mout_pll_cpucl0", mout_pll_cpucl0_p,
+ PLL_CON0_PLL_CPUCL0, 4, 1),
+ MUX(CLK_MOUT_CPUCL0_CLUSTER_USER, "mout_cpucl0_cluster_user", mout_cpucl0_cluster_user_p,
+ PLL_CON0_MUX_CLKCMU_CPUCL0_CLUSTER_USER, 4, 1),
+ MUX(CLK_MOUT_CPUCL0_DBG_USER, "mout_cpucl0_dbg_user", mout_cpucl0_dbg_user_p,
+ PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER, 4, 1),
+ MUX(CLK_MOUT_CPUCL0_SWITCH_USER, "mout_cpucl0_switch_user", mout_cpucl0_switch_user_p,
+ PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER, 4, 1),
+ MUX(CLK_MOUT_CPUCL0_CLUSTER, "mout_cpucl0_cluster", mout_cpucl0_cluster_p,
+ CLK_CON_MUX_MUX_CLK_CPUCL0_CLUSTER, 0, 2),
+ MUX(CLK_MOUT_CPUCL0_CORE, "mout_cpucl0_core", mout_cpucl0_core_p,
+ CLK_CON_MUX_MUX_CLK_CPUCL0_CORE, 0, 2),
+};
+
+static const struct samsung_div_clock cpucl0_div_clks[] __initconst = {
+ DIV(CLK_DOUT_CLUSTER0_ACLK, "dout_cluster0_aclk",
+ "mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK, 0, 4),
+ DIV(CLK_DOUT_CLUSTER0_ATCLK, "dout_cluster0_atclk",
+ "mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK, 0, 4),
+ DIV(CLK_DOUT_CLUSTER0_MPCLK, "dout_cluster0_mpclk",
+ "mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_MPCLK, 0, 4),
+ DIV(CLK_DOUT_CLUSTER0_PCLK, "dout_cluster0_pclk",
+ "mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK, 0, 4),
+ DIV(CLK_DOUT_CLUSTER0_PERIPHCLK, "dout_cluster0_periphclk",
+ "mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK, 0, 4),
+ DIV(CLK_DOUT_CPUCL0_DBG_NOC, "dout_cpucl0_dbg_noc",
+ "mout_cpucl0_dbg_user", CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC, 0, 3),
+ DIV(CLK_DOUT_CPUCL0_DBG_PCLKDBG, "dout_cpucl0_dbg_pclkdbg",
+ "mout_cpucl0_dbg_user", CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG, 0, 3),
+ DIV(CLK_DOUT_CPUCL0_NOCP, "dout_cpucl0_nocp",
+ "mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CPUCL0_NOCP, 0, 4),
+};
+
+static const struct samsung_cmu_info cpucl0_cmu_info __initconst = {
+ .pll_clks = cpucl0_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(cpucl0_pll_clks),
+ .mux_clks = cpucl0_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(cpucl0_mux_clks),
+ .div_clks = cpucl0_div_clks,
+ .nr_div_clks = ARRAY_SIZE(cpucl0_div_clks),
+ .nr_clk_ids = CLKS_NR_CPUCL0,
+ .clk_regs = cpucl0_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(cpucl0_clk_regs),
+ .clk_name = "cpucl0",
+};
+
+static void __init exynosautov920_cmu_cpucl0_init(struct device_node *np)
+{
+ exynos_arm64_register_cmu(NULL, np, &cpucl0_cmu_info);
+}
+
+CLK_OF_DECLARE(exynosautov920_cmu_cpucl0, "samsung,exynosautov920-cmu-cpucl0",
+ exynosautov920_cmu_cpucl0_init);
+
/* ---- CMU_PERIC0 --------------------------------------------------------- */
/* Register Offset definitions for CMU_PERIC0 (0x10800000) */
--
2.49.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 3/3] arm64: dts: exynosautov920: add cpucl0 clock DT nodes
2025-04-18 6:14 ` [PATCH 0/3] add CPUCL0 clock support for exynosauto v920 SoC Shin Son
2025-04-18 6:14 ` [PATCH 1/3] dt-bindings: clock: exynosautov920: add cpucl0 clock definitions Shin Son
2025-04-18 6:14 ` [PATCH 2/3] clk: samsung: exynosautov920: add cpucl0 clock support Shin Son
@ 2025-04-18 6:15 ` Shin Son
2025-04-22 8:00 ` Krzysztof Kozlowski
2 siblings, 1 reply; 10+ messages in thread
From: Shin Son @ 2025-04-18 6:15 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sylwester Nawrocki, Chanwoo Choi,
Alim Akhtar, Michael Turquette, Stephen Boyd, Rob Herring,
Conor Dooley, Sunyeal Hong
Cc: Shin Son, linux-samsung-soc, linux-clk, devicetree,
linux-arm-kernel, linux-kernel
Add cmu_cpucl0 clocks for switch, cluster, and dbg domains respectively.
Signed-off-by: Shin Son <shin.son@samsung.com>
---
arch/arm64/boot/dts/exynos/exynosautov920.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
index fc6ac531d597..d1528633adfe 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
@@ -582,6 +582,21 @@ pinctrl_aud: pinctrl@1a460000 {
compatible = "samsung,exynosautov920-pinctrl";
reg = <0x1a460000 0x10000>;
};
+
+ cmu_cpucl0: clock-controller@1ec00000 {
+ compatible = "samsung,exynosautov920-cmu-cpucl0";
+ reg = <0x1EC00000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&xtcxo>,
+ <&cmu_top DOUT_CLKCMU_CPUCL0_SWITCH>,
+ <&cmu_top DOUT_CLKCMU_CPUCL0_CLUSTER>,
+ <&cmu_top DOUT_CLKCMU_CPUCL0_DBG>;
+ clock-names = "oscclk",
+ "switch",
+ "cluster",
+ "dbg";
+ };
};
timer {
--
2.49.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] dt-bindings: clock: exynosautov920: add cpucl0 clock definitions
2025-04-18 6:14 ` [PATCH 1/3] dt-bindings: clock: exynosautov920: add cpucl0 clock definitions Shin Son
@ 2025-04-22 7:54 ` Krzysztof Kozlowski
2025-04-23 0:45 ` 손신
0 siblings, 1 reply; 10+ messages in thread
From: Krzysztof Kozlowski @ 2025-04-22 7:54 UTC (permalink / raw)
To: Shin Son, Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar,
Michael Turquette, Stephen Boyd, Rob Herring, Conor Dooley,
Sunyeal Hong
Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel,
linux-kernel
On 18/04/2025 08:14, Shin Son wrote:
> Add cpucl0 clock definitions.
... and cpucl0 is? Describe the hardware in the commit msg in the future.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] clk: samsung: exynosautov920: add cpucl0 clock support
2025-04-18 6:14 ` [PATCH 2/3] clk: samsung: exynosautov920: add cpucl0 clock support Shin Son
@ 2025-04-22 7:59 ` Krzysztof Kozlowski
2025-04-23 0:59 ` 손신
0 siblings, 1 reply; 10+ messages in thread
From: Krzysztof Kozlowski @ 2025-04-22 7:59 UTC (permalink / raw)
To: Shin Son, Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar,
Michael Turquette, Stephen Boyd, Rob Herring, Conor Dooley,
Sunyeal Hong
Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel,
linux-kernel
On 18/04/2025 08:14, Shin Son wrote:
> Register compatible and cmu_info data to support clock CMU_CPUCL0,
> this provides clock for CPUCL0_SWTICH/DBG/CLUSTER.
>
Explain why this is needed as clk of declare, instead of platform driver.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] arm64: dts: exynosautov920: add cpucl0 clock DT nodes
2025-04-18 6:15 ` [PATCH 3/3] arm64: dts: exynosautov920: add cpucl0 clock DT nodes Shin Son
@ 2025-04-22 8:00 ` Krzysztof Kozlowski
2025-04-23 1:05 ` 손신
0 siblings, 1 reply; 10+ messages in thread
From: Krzysztof Kozlowski @ 2025-04-22 8:00 UTC (permalink / raw)
To: Shin Son, Sylwester Nawrocki, Chanwoo Choi, Alim Akhtar,
Michael Turquette, Stephen Boyd, Rob Herring, Conor Dooley,
Sunyeal Hong
Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel,
linux-kernel
On 18/04/2025 08:15, Shin Son wrote:
> Add cmu_cpucl0 clocks for switch, cluster, and dbg domains respectively.
>
> Signed-off-by: Shin Son <shin.son@samsung.com>
> ---
> arch/arm64/boot/dts/exynos/exynosautov920.dtsi | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> index fc6ac531d597..d1528633adfe 100644
> --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> @@ -582,6 +582,21 @@ pinctrl_aud: pinctrl@1a460000 {
> compatible = "samsung,exynosautov920-pinctrl";
> reg = <0x1a460000 0x10000>;
> };
> +
> + cmu_cpucl0: clock-controller@1ec00000 {
> + compatible = "samsung,exynosautov920-cmu-cpucl0";
> + reg = <0x1EC00000 0x8000>;
Lowercase hex.
> + #clock-cells = <1>;
> +
> + clocks = <&xtcxo>,
> + <&cmu_top DOUT_CLKCMU_CPUCL0_SWITCH>,
This looks misaligned.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [PATCH 1/3] dt-bindings: clock: exynosautov920: add cpucl0 clock definitions
2025-04-22 7:54 ` Krzysztof Kozlowski
@ 2025-04-23 0:45 ` 손신
0 siblings, 0 replies; 10+ messages in thread
From: 손신 @ 2025-04-23 0:45 UTC (permalink / raw)
To: 'Krzysztof Kozlowski', 'Sylwester Nawrocki',
'Chanwoo Choi', 'Alim Akhtar',
'Michael Turquette', 'Stephen Boyd',
'Rob Herring', 'Conor Dooley',
'Sunyeal Hong'
Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel,
linux-kernel
Hello Krzysztof Kozlowski,
> -----Original Message-----
> From: Krzysztof Kozlowski [mailto:krzk@kernel.org]
> Sent: Tuesday, April 22, 2025 4:54 PM
> To: Shin Son <shin.son@samsung.com>; Sylwester Nawrocki
> <s.nawrocki@samsung.com>; Chanwoo Choi <cw00.choi@samsung.com>; Alim
> Akhtar <alim.akhtar@samsung.com>; Michael Turquette
> <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob Herring
> <robh@kernel.org>; Conor Dooley <conor+dt@kernel.org>; Sunyeal Hong
> <sunyeal.hong@samsung.com>
> Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org
> Subject: Re: [PATCH 1/3] dt-bindings: clock: exynosautov920: add cpucl0
> clock definitions
>
> On 18/04/2025 08:14, Shin Son wrote:
> > Add cpucl0 clock definitions.
>
> ... and cpucl0 is? Describe the hardware in the commit msg in the future.
>
>
> Best regards,
> Krzysztof
Thanks for the feedback.
I'll update the commit message to include a brief description of the hardware.
Best regards,
Shin Son
^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [PATCH 2/3] clk: samsung: exynosautov920: add cpucl0 clock support
2025-04-22 7:59 ` Krzysztof Kozlowski
@ 2025-04-23 0:59 ` 손신
0 siblings, 0 replies; 10+ messages in thread
From: 손신 @ 2025-04-23 0:59 UTC (permalink / raw)
To: 'Krzysztof Kozlowski', 'Sylwester Nawrocki',
'Chanwoo Choi', 'Alim Akhtar',
'Michael Turquette', 'Stephen Boyd',
'Rob Herring', 'Conor Dooley',
'Sunyeal Hong'
Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel,
linux-kernel
Hello Krzysztof Kozlowski,
> -----Original Message-----
> From: Krzysztof Kozlowski [mailto:krzk@kernel.org]
> Sent: Tuesday, April 22, 2025 4:59 PM
> To: Shin Son <shin.son@samsung.com>; Sylwester Nawrocki
> <s.nawrocki@samsung.com>; Chanwoo Choi <cw00.choi@samsung.com>; Alim
> Akhtar <alim.akhtar@samsung.com>; Michael Turquette
> <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob Herring
> <robh@kernel.org>; Conor Dooley <conor+dt@kernel.org>; Sunyeal Hong
> <sunyeal.hong@samsung.com>
> Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org
> Subject: Re: [PATCH 2/3] clk: samsung: exynosautov920: add cpucl0 clock
> support
>
> On 18/04/2025 08:14, Shin Son wrote:
> > Register compatible and cmu_info data to support clock CMU_CPUCL0,
> > this provides clock for CPUCL0_SWTICH/DBG/CLUSTER.
> >
>
> Explain why this is needed as clk of declare, instead of platform driver.
>
>
>
> Best regards,
> Krzysztof
CPUCL0 refers CPU Cluster 0.
Since the CPU clocks need to be available as early as possible, I used CLK_OF_DECLARE instead of a platform driver.
I'll update the commit message and add a comment in the code to clarify this.
Best regards,
Shin Son
^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [PATCH 3/3] arm64: dts: exynosautov920: add cpucl0 clock DT nodes
2025-04-22 8:00 ` Krzysztof Kozlowski
@ 2025-04-23 1:05 ` 손신
0 siblings, 0 replies; 10+ messages in thread
From: 손신 @ 2025-04-23 1:05 UTC (permalink / raw)
To: 'Krzysztof Kozlowski', 'Sylwester Nawrocki',
'Chanwoo Choi', 'Alim Akhtar',
'Michael Turquette', 'Stephen Boyd',
'Rob Herring', 'Conor Dooley',
'Sunyeal Hong'
Cc: linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel,
linux-kernel
Hello Krzysztof Kozlowski,
> -----Original Message-----
> From: Krzysztof Kozlowski [mailto:krzk@kernel.org]
> Sent: Tuesday, April 22, 2025 5:00 PM
> To: Shin Son <shin.son@samsung.com>; Sylwester Nawrocki
> <s.nawrocki@samsung.com>; Chanwoo Choi <cw00.choi@samsung.com>; Alim
> Akhtar <alim.akhtar@samsung.com>; Michael Turquette
> <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob Herring
> <robh@kernel.org>; Conor Dooley <conor+dt@kernel.org>; Sunyeal Hong
> <sunyeal.hong@samsung.com>
> Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org
> Subject: Re: [PATCH 3/3] arm64: dts: exynosautov920: add cpucl0 clock DT
> nodes
>
> On 18/04/2025 08:15, Shin Son wrote:
> > Add cmu_cpucl0 clocks for switch, cluster, and dbg domains respectively.
> >
> > Signed-off-by: Shin Son <shin.son@samsung.com>
> > ---
> > arch/arm64/boot/dts/exynos/exynosautov920.dtsi | 15 +++++++++++++++
> > 1 file changed, 15 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> > index fc6ac531d597..d1528633adfe 100644
> > --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> > +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> > @@ -582,6 +582,21 @@ pinctrl_aud: pinctrl@1a460000 {
> > compatible = "samsung,exynosautov920-pinctrl";
> > reg = <0x1a460000 0x10000>;
> > };
> > +
> > + cmu_cpucl0: clock-controller@1ec00000 {
> > + compatible = "samsung,exynosautov920-cmu-cpucl0";
> > + reg = <0x1EC00000 0x8000>;
>
> Lowercase hex.
> > + #clock-cells = <1>;
> > +
> > + clocks = <&xtcxo>,
> > + <&cmu_top DOUT_CLKCMU_CPUCL0_SWITCH>,
>
> This looks misaligned.
>
>
> Best regards,
> Krzysztof
Thanks for the quick response.
I'll revise everything you pointed out and send an updated patch shortly.
Best regards,
Shin Son
^ permalink raw reply [flat|nested] 10+ messages in thread
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2025-04-18 6:14 ` [PATCH 0/3] add CPUCL0 clock support for exynosauto v920 SoC Shin Son
2025-04-18 6:14 ` [PATCH 1/3] dt-bindings: clock: exynosautov920: add cpucl0 clock definitions Shin Son
2025-04-22 7:54 ` Krzysztof Kozlowski
2025-04-23 0:45 ` 손신
2025-04-18 6:14 ` [PATCH 2/3] clk: samsung: exynosautov920: add cpucl0 clock support Shin Son
2025-04-22 7:59 ` Krzysztof Kozlowski
2025-04-23 0:59 ` 손신
2025-04-18 6:15 ` [PATCH 3/3] arm64: dts: exynosautov920: add cpucl0 clock DT nodes Shin Son
2025-04-22 8:00 ` Krzysztof Kozlowski
2025-04-23 1:05 ` 손신
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