* [PATCH v2 0/4] Add pinctrl support for AST2700 SoC
@ 2025-09-04 10:33 Billy Tsai
2025-09-04 10:33 ` [PATCH v2 1/4] dt-bindings: mfd: aspeed,ast2x00-scu: Support ast2700 pinctrl Billy Tsai
` (4 more replies)
0 siblings, 5 replies; 11+ messages in thread
From: Billy Tsai @ 2025-09-04 10:33 UTC (permalink / raw)
To: lee, robh, krzk+dt, conor+dt, joel, andrew, linus.walleij, brgl,
billy_tsai, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel, openbmc, linux-gpio, BMC-SW
Document and add the pinctrl driver for AST2700 SoC.
Changes since v1:
- Update pinctrl aspeed binding files.
- Update the commit message for pinctrl binding patch.
Billy Tsai (4):
dt-bindings: mfd: aspeed,ast2x00-scu: Support ast2700 pinctrl
dt-bindings: pinctrl: aspeed: Add support for AST27xx
pinctrl: aspeed: Add AST2700 pinmux support
arm64: dts: add AST27xx pinctrl configuration nodes
.../bindings/mfd/aspeed,ast2x00-scu.yaml | 2 +
.../pinctrl/aspeed,ast2700-soc0-pinctrl.yaml | 115 +
.../pinctrl/aspeed,ast2700-soc1-pinctrl.yaml | 435 +++
.../boot/dts/aspeed/aspeed-g7-pinctrl.dtsi | 1359 +++++++++
drivers/pinctrl/aspeed/Kconfig | 8 +
drivers/pinctrl/aspeed/Makefile | 1 +
.../pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c | 503 ++++
.../pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c | 2523 +++++++++++++++++
drivers/pinctrl/aspeed/pinctrl-aspeed.c | 47 +
drivers/pinctrl/aspeed/pinctrl-aspeed.h | 11 +-
drivers/pinctrl/aspeed/pinmux-aspeed.h | 35 +-
11 files changed, 5034 insertions(+), 5 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml
create mode 100644 Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml
create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7-pinctrl.dtsi
create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c
create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c
--
2.25.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 1/4] dt-bindings: mfd: aspeed,ast2x00-scu: Support ast2700 pinctrl
2025-09-04 10:33 [PATCH v2 0/4] Add pinctrl support for AST2700 SoC Billy Tsai
@ 2025-09-04 10:33 ` Billy Tsai
2025-09-05 8:13 ` Krzysztof Kozlowski
2025-09-04 10:33 ` [PATCH v2 2/4] dt-bindings: pinctrl: aspeed: Add support for AST27xx Billy Tsai
` (3 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Billy Tsai @ 2025-09-04 10:33 UTC (permalink / raw)
To: lee, robh, krzk+dt, conor+dt, joel, andrew, linus.walleij, brgl,
billy_tsai, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel, openbmc, linux-gpio, BMC-SW
Add the ast2700 pinctrl compatible string.
"aspeed,ast2700-soc0-pinctrl" and "aspeed,ast2700-soc1-pinctrl"
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
---
Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
index 5eccd10d95ce..3a993702a6f6 100644
--- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
+++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
@@ -61,6 +61,8 @@ patternProperties:
- aspeed,ast2400-pinctrl
- aspeed,ast2500-pinctrl
- aspeed,ast2600-pinctrl
+ - aspeed,ast2700-soc0-pinctrl
+ - aspeed,ast2700-soc1-pinctrl
required:
- compatible
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 2/4] dt-bindings: pinctrl: aspeed: Add support for AST27xx
2025-09-04 10:33 [PATCH v2 0/4] Add pinctrl support for AST2700 SoC Billy Tsai
2025-09-04 10:33 ` [PATCH v2 1/4] dt-bindings: mfd: aspeed,ast2x00-scu: Support ast2700 pinctrl Billy Tsai
@ 2025-09-04 10:33 ` Billy Tsai
2025-09-05 8:16 ` Krzysztof Kozlowski
2025-09-04 10:34 ` [PATCH v2 4/4] arm64: dts: add AST27xx pinctrl configuration nodes Billy Tsai
` (2 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Billy Tsai @ 2025-09-04 10:33 UTC (permalink / raw)
To: lee, robh, krzk+dt, conor+dt, joel, andrew, linus.walleij, brgl,
billy_tsai, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel, openbmc, linux-gpio, BMC-SW
Add bindings for the pin controller found in the ASPEED AST27xx SoC.
The ASPEED AST2700 SoC contains two separate pin controllers, each
managed by a distinct System Control Unit (SCU).
Because these two controllers have different register maps, control
different sets of pins, support different pin configuration options, and
implement different multi-function switch logic, they are not compatible.
Therefore, two separate device tree bindings,'aspeed,ast2700-soc0-pinctrl'
and 'aspeed,ast2700-soc1-pinctrl', are introduced.
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
---
.../pinctrl/aspeed,ast2700-soc0-pinctrl.yaml | 115 +++++
.../pinctrl/aspeed,ast2700-soc1-pinctrl.yaml | 435 ++++++++++++++++++
2 files changed, 550 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml
create mode 100644 Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml
new file mode 100644
index 000000000000..0fee62259250
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ASPEED AST2700 SoC0 Pin Controller
+
+maintainers:
+ - Billy Tsai <billy_tsai@aspeedtech.com>
+
+description: |
+ Bindings for the ASPEED AST2700 SoC0 Pin Controller.
+
+properties:
+ compatible:
+ const: aspeed,ast2700-soc0-pinctrl
+
+additionalProperties:
+ $ref: pinmux-node.yaml#
+ additionalProperties: false
+
+ properties:
+ function:
+ enum:
+ - EMMC
+ - VGADDC
+ - USB3A
+ - USB2A
+ - USB3B
+ - USB2B
+ - JTAG0
+ - PCIERC
+
+ groups:
+ enum:
+ - EMMCG1
+ - EMMCG4
+ - EMMCG8
+ - EMMCWPN
+ - EMMCCDN
+ - VGADDC
+ - USB3AXHD
+ - USB3AXHPD
+ - USB3AXH
+ - USB3AXHP
+ - USB3AXH2B
+ - USB3AXHP2B
+ - USB2AXHD1
+ - USB2AXHPD1
+ - USB2AD1
+ - USB2AXH
+ - USB2AXHP
+ - USB2AXH2B
+ - USB2AXHP2B
+ - USB2AHPD0
+ - USB2AD0
+ - USB2AH
+ - USB2AHP
+ - USB3BXHD
+ - USB3BXHPD
+ - USB3BXH
+ - USB3BXHP
+ - USB3BXH2A
+ - USB3BXHP2A
+ - USB2BXHD1
+ - USB2BXHPD1
+ - USB2BD1
+ - USB2BXH
+ - USB2BXHP
+ - USB2BXH2A
+ - USB2BXHP2A
+ - USB2BHPD0
+ - USB2BD0
+ - USB2BH
+ - USB2BHP
+ - JTAGM0
+ - PSP
+ - SSP
+ - TSP
+ - DDR
+ - USB3A
+ - USB3B
+ - PCIEA
+ - PCIEB
+ - PCIERC0PERST
+ - PCIERC1PERST
+
+ pins:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ drive-strength:
+ minimum: 0
+ maximum: 15
+
+allOf:
+ - $ref: pinctrl.yaml#
+
+required:
+ - compatible
+
+examples:
+ - |
+ pinctrl0: pinctrl{
+ compatible = "aspeed,ast2700-soc0-pinctrl";
+
+ pinctrl_emmc_default: emmc-default {
+ function = "EMMC";
+ groups = "EMMCG1";
+ };
+
+ pinctrl_emmcclk_driving: emmcclk-driving {
+ pins = "AC14";
+ drive-strength = <2>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml
new file mode 100644
index 000000000000..1c0121aa26cd
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml
@@ -0,0 +1,435 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ASPEED AST2700 SoC1 Pin Controller
+
+maintainers:
+ - Billy Tsai <billy_tsai@aspeedtech.com>
+
+description: |
+ Bindings for the ASPEED AST2700 SoC1 Pin Controller.
+
+properties:
+ compatible:
+ const: aspeed,ast2700-soc1-pinctrl
+
+additionalProperties:
+ $ref: pinmux-node.yaml#
+ additionalProperties: false
+
+ properties:
+ function:
+ enum:
+ - ADC0
+ - ADC1
+ - ADC2
+ - ADC3
+ - ADC4
+ - ADC5
+ - ADC6
+ - ADC7
+ - ADC8
+ - ADC9
+ - ADC10
+ - ADC11
+ - ADC12
+ - ADC13
+ - ADC14
+ - ADC15
+ - CANBUS
+ - DDR
+ - ESPI0
+ - ESPI1
+ - FSI0
+ - FSI1
+ - FSI2
+ - FSI3
+ - FWQSPI
+ - I2C0
+ - I2C1
+ - I2C2
+ - I2C3
+ - I2C4
+ - I2C5
+ - I2C6
+ - I2C7
+ - I2C8
+ - I2C9
+ - I2C10
+ - I2C11
+ - I2C12
+ - I2C13
+ - I2C14
+ - I2C15
+ - I3C0
+ - I3C1
+ - I3C2
+ - I3C3
+ - I3C4
+ - I3C5
+ - I3C6
+ - I3C7
+ - I3C8
+ - I3C9
+ - I3C10
+ - I3C11
+ - I3C12
+ - I3C13
+ - I3C14
+ - I3C15
+ - JTAGM0
+ - JTAGM1
+ - LPC0
+ - LPC1
+ - LTPI_PS_I2C0
+ - LTPI_PS_I2C1
+ - LTPI_PS_I2C2
+ - LTPI_PS_I2C3
+ - MDIO0
+ - MDIO1
+ - MDIO2
+ - NCTS5
+ - NDCD5
+ - NDSR5
+ - NRI5
+ - PCIERC
+ - PWM0
+ - PWM1
+ - PWM2
+ - PWM3
+ - PWM4
+ - PWM5
+ - PWM6
+ - PWM7
+ - PWM8
+ - PWM9
+ - PWM10
+ - PWM11
+ - PWM12
+ - PWM13
+ - PWM14
+ - PWM15
+ - QSPI0
+ - QSPI1
+ - QSPI2
+ - RGMII0
+ - RGMII1
+ - RMII0
+ - RMII0RCLKO
+ - RMII1
+ - RMII1RCLKO
+ - SALT0
+ - SALT1
+ - SALT2
+ - SALT3
+ - SALT4
+ - SALT5
+ - SALT6
+ - SALT7
+ - SALT8
+ - SALT9
+ - SALT10
+ - SALT11
+ - SALT12
+ - SALT13
+ - SALT14
+ - SALT15
+ - SD
+ - SGMII
+ - SGPM0
+ - SGPM1
+ - SGPS
+ - SPI0
+ - SPI0CS1
+ - SPI1
+ - SPI1CS1
+ - SPI2
+ - SPI2CS1
+ - SSP
+ - TACH0
+ - TACH1
+ - TACH2
+ - TACH3
+ - TACH4
+ - TACH5
+ - TACH6
+ - TACH7
+ - TACH8
+ - TACH9
+ - TACH10
+ - TACH11
+ - TACH12
+ - TACH13
+ - TACH14
+ - TACH15
+ - THRU0
+ - THRU1
+ - THRU2
+ - THRU3
+ - TSP
+ - UART0
+ - UART1
+ - UART2
+ - UART3
+ - UART5
+ - UART6
+ - UART7
+ - UART8
+ - UART9
+ - UART10
+ - UART11
+ - USB2C
+ - USB2D
+ - VPI
+
+ groups:
+ enum:
+ - ADC0
+ - ADC1
+ - ADC2
+ - ADC3
+ - ADC4
+ - ADC5
+ - ADC6
+ - ADC7
+ - ADC8
+ - ADC9
+ - ADC10
+ - ADC11
+ - ADC12
+ - ADC13
+ - ADC14
+ - ADC15
+ - CANBUS
+ - DI2C0
+ - DI2C1
+ - DI2C2
+ - DI2C3
+ - DI2C8
+ - DI2C9
+ - DI2C10
+ - DI2C11
+ - DI2C12
+ - DI2C13
+ - DI2C14
+ - DI2C15
+ - DSGPM0
+ - ESPI0
+ - ESPI1
+ - FSI0
+ - FSI1
+ - FSI2
+ - FSI3
+ - FWQSPI
+ - HVI3C0
+ - HVI3C1
+ - HVI3C2
+ - HVI3C3
+ - HVI3C12
+ - HVI3C13
+ - HVI3C14
+ - HVI3C15
+ - I2C0
+ - I2C1
+ - I2C2
+ - I2C3
+ - I2C4
+ - I2C5
+ - I2C6
+ - I2C7
+ - I2C8
+ - I2C9
+ - I2C10
+ - I2C11
+ - I2C12
+ - I2C13
+ - I2C14
+ - I2C15
+ - I3C4
+ - I3C5
+ - I3C6
+ - I3C7
+ - I3C8
+ - I3C9
+ - I3C10
+ - I3C11
+ - JTAGM1
+ - LPC0
+ - LPC1
+ - LTPI_PS_I2C0
+ - LTPI_PS_I2C1
+ - LTPI_PS_I2C2
+ - LTPI_PS_I2C3
+ - MDIO0
+ - MDIO1
+ - MDIO2
+ - NCTS0
+ - NCTS1
+ - NCTS5
+ - NCTS6
+ - NDCD0
+ - NDCD1
+ - NDCD5
+ - NDCD6
+ - NDSR0
+ - NDSR1
+ - NDSR5
+ - NDSR6
+ - NDTR0
+ - NDTR1
+ - NDTR5
+ - NDTR6
+ - NRI0
+ - NRI1
+ - NRI5
+ - NRI6
+ - NRTS0
+ - NRTS1
+ - NRTS5
+ - NRTS6
+ - PE2SGRSTN
+ - PWM0
+ - PWM1
+ - PWM2
+ - PWM3
+ - PWM4
+ - PWM5
+ - PWM6
+ - PWM7
+ - PWM8
+ - PWM9
+ - PWM10
+ - PWM11
+ - PWM12
+ - PWM13
+ - PWM14
+ - PWM15
+ - QSPI0
+ - QSPI1
+ - QSPI2
+ - RGMII0
+ - RGMII1
+ - RMII0
+ - RMII0RCLKO
+ - RMII1
+ - RMII1RCLKO
+ - RXD0
+ - RXD1
+ - RXD2
+ - RXD3
+ - RXD5
+ - RXD6
+ - RXD7
+ - RXD8
+ - RXD9
+ - RXD10
+ - RXD11
+ - SALT0
+ - SALT1
+ - SALT2
+ - SALT3
+ - SALT4
+ - SALT5
+ - SALT6
+ - SALT7
+ - SALT8
+ - SALT9
+ - SALT10
+ - SALT11
+ - SALT12
+ - SALT13
+ - SALT14
+ - SALT15
+ - SD
+ - SGMII
+ - SGPM0
+ - SGPM1
+ - SGPS
+ - SPI0
+ - SPI0CS1
+ - SPI1
+ - SPI1CS1
+ - SPI2
+ - SPI2CS1
+ - TACH0
+ - TACH1
+ - TACH2
+ - TACH3
+ - TACH4
+ - TACH5
+ - TACH6
+ - TACH7
+ - TACH8
+ - TACH9
+ - TACH10
+ - TACH11
+ - TACH12
+ - TACH13
+ - TACH14
+ - TACH15
+ - THRU0
+ - THRU1
+ - THRU2
+ - THRU3
+ - TXD0
+ - TXD1
+ - TXD2
+ - TXD3
+ - TXD5
+ - TXD6
+ - TXD7
+ - TXD8
+ - TXD9
+ - TXD10
+ - TXD11
+ - USB2CD
+ - USB2CH
+ - USB2CU
+ - USB2CUD
+ - USB2DD
+ - USB2DH
+ - VPI
+
+ pins:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ bias-disable:
+ type: boolean
+ bias-pull-down:
+ type: boolean
+ bias-pull-up:
+ type: boolean
+ drive-strength:
+ minimum: 0
+ maximum: 3
+ power-source:
+ enum: [1800, 3300]
+
+allOf:
+ - $ref: pinctrl.yaml#
+
+required:
+ - compatible
+
+examples:
+ - |
+ pinctrl1: pinctrl {
+ compatible = "aspeed,ast2700-soc1-pinctrl";
+
+ pinctrl_hvi3c0_default: hvi3c0-default {
+ function = "I3C0";
+ groups = "HVI3C0";
+ };
+
+ pinctrl_i3c0_3_hv_voltage: i3chv-voltage {
+ pins = "U25";
+ power-source = <1800>;
+ };
+
+ pinctrl_i3c0_driving: i3c0-driving {
+ pins = "U25", "U26";
+ drive-strength = <2>;
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 4/4] arm64: dts: add AST27xx pinctrl configuration nodes
2025-09-04 10:33 [PATCH v2 0/4] Add pinctrl support for AST2700 SoC Billy Tsai
2025-09-04 10:33 ` [PATCH v2 1/4] dt-bindings: mfd: aspeed,ast2x00-scu: Support ast2700 pinctrl Billy Tsai
2025-09-04 10:33 ` [PATCH v2 2/4] dt-bindings: pinctrl: aspeed: Add support for AST27xx Billy Tsai
@ 2025-09-04 10:34 ` Billy Tsai
2025-09-04 14:26 ` Rob Herring
2025-09-05 8:12 ` [PATCH v2 0/4] Add pinctrl support for AST2700 SoC Krzysztof Kozlowski
[not found] ` <20250904103401.88287-4-billy_tsai@aspeedtech.com>
4 siblings, 1 reply; 11+ messages in thread
From: Billy Tsai @ 2025-09-04 10:34 UTC (permalink / raw)
To: lee, robh, krzk+dt, conor+dt, joel, andrew, linus.walleij, brgl,
billy_tsai, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel, openbmc, linux-gpio, BMC-SW
Add pinctrl0 and pinctrl1 nodes for AST27xx SoC0 and SoC1 to configure
the pinmux settings for each ball.
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
---
.../boot/dts/aspeed/aspeed-g7-pinctrl.dtsi | 1359 +++++++++++++++++
1 file changed, 1359 insertions(+)
create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7-pinctrl.dtsi
diff --git a/arch/arm64/boot/dts/aspeed/aspeed-g7-pinctrl.dtsi b/arch/arm64/boot/dts/aspeed/aspeed-g7-pinctrl.dtsi
new file mode 100644
index 000000000000..2167db85839d
--- /dev/null
+++ b/arch/arm64/boot/dts/aspeed/aspeed-g7-pinctrl.dtsi
@@ -0,0 +1,1359 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright 2025 ASPEED Corp.
+
+&pinctrl0 {
+ pinctrl_emmc_default: emmc-default {
+ function = "EMMC";
+ groups = "EMMCG1";
+ };
+
+ pinctrl_emmcg4_default: emmc-default {
+ function = "EMMC";
+ groups = "EMMCG4";
+ };
+
+ pinctrl_emmcg8_default: emmcg8-default {
+ function = "EMMC";
+ groups = "EMMCG8";
+ };
+
+ pinctrl_emmcwpn_default: emmcwpn-default {
+ function = "EMMC";
+ groups = "EMMCWPN";
+ };
+
+ pinctrl_emmccdn_default: emmccdn-default {
+ function = "EMMC";
+ groups = "EMMCCDN";
+ };
+
+ pinctrl_vgaddc_default: vgaddc-default {
+ function = "VGADDC";
+ groups = "VGADDC";
+ };
+
+ pinctrl_usb3axhd_default: usb3axhd-default {
+ function = "USB3A";
+ groups = "USB3AXHD";
+ };
+
+ pinctrl_usb3axhpd_default: usb3axhpd-default {
+ function = "USB3A";
+ groups = "USB3AXHPD";
+ };
+
+ pinctrl_usb3axh_default: usb3axh-default {
+ function = "USB3A";
+ groups = "USB3AXH";
+ };
+
+ pinctrl_usb3axhp_default: usb3axhp-default {
+ function = "USB3A";
+ groups = "USB3AXHP";
+ };
+
+ pinctrl_usb3axh2b_default: usb3axh2b-default {
+ function = "USB3A";
+ groups = "USB3AXH2B";
+ };
+
+ pinctrl_usb3axhp2b_default: usb3axhp2b-default {
+ function = "USB3A";
+ groups = "USB3AXHP2B";
+ };
+
+ pinctrl_usb2axhd1_default: usb2axhd1-default {
+ function = "USB2A";
+ groups = "USB2AXHD1";
+ };
+
+ pinctrl_usb2axhpd1_default: usb2axhpd1-default {
+ function = "USB2A";
+ groups = "USB2AXHPD1";
+ };
+
+ pinctrl_usb2ad1_default: usb2ad1-default {
+ function = "USB2A";
+ groups = "USB2AD1";
+ };
+
+ pinctrl_usb2axh_default: usb2axh-default {
+ function = "USB2A";
+ groups = "USB2AXH";
+ };
+
+ pinctrl_usb2axhp_default: usb2axhp-default {
+ function = "USB2A";
+ groups = "USB2AXHP";
+ };
+
+ pinctrl_usb2axh2b_default: usb2axh2b-default {
+ function = "USB2A";
+ groups = "USB2AXH2B";
+ };
+
+ pinctrl_usb2axhp2b_default: usb2axhp2b-default {
+ function = "USB2A";
+ groups = "USB2AXHP2B";
+ };
+
+ pinctrl_usb2ahpd0_default: usb2ahpd0-default {
+ function = "USB2A";
+ groups = "USB2AHPD0";
+ };
+
+ pinctrl_usb2ad0_default: usb2ad0-default {
+ function = "USB2A";
+ groups = "USB2AD0";
+ };
+
+ pinctrl_usb2ah_default: usb2ah-default {
+ function = "USB2A";
+ groups = "USB2AH";
+ };
+
+ pinctrl_usb2ahp_default: usb2ahp-default {
+ function = "USB2A";
+ groups = "USB2AHP";
+ };
+
+ pinctrl_usb3bxhd_default: usb3bxhd-default {
+ function = "USB3B";
+ groups = "USB3BXHD";
+ };
+
+ pinctrl_usb3bxhpd_default: usb3bxhpd-default {
+ function = "USB3B";
+ groups = "USB3BXHPD";
+ };
+
+ pinctrl_usb3bxh_default: usb3bxh-default {
+ function = "USB3B";
+ groups = "USB3BXH";
+ };
+
+ pinctrl_usb3bxhp_default: usb3bxhp-default {
+ function = "USB3B";
+ groups = "USB3BXHP";
+ };
+
+ pinctrl_usb3bxh2a_default: usb3bxh2a-default {
+ function = "USB3B";
+ groups = "USB3BXH2A";
+ };
+
+ pinctrl_usb3bxhp2a_default: usb3bxhp2a-default {
+ function = "USB3B";
+ groups = "USB3BXHP2A";
+ };
+
+ pinctrl_usb2bxhd1_default: usb2bxhd1-default {
+ function = "USB2B";
+ groups = "USB2BXHD1";
+ };
+
+ pinctrl_usb2bxhpd1_default: usb2bxhpd1-default {
+ function = "USB2B";
+ groups = "USB2BXHPD1";
+ };
+
+ pinctrl_usb2bd1_default: usb2bd1-default {
+ function = "USB2B";
+ groups = "USB2BD1";
+ };
+
+ pinctrl_usb2bxh_default: usb2bxh-default {
+ function = "USB2B";
+ groups = "USB2BXH";
+ };
+
+ pinctrl_usb2bxhp_default: usb2bxhp-default {
+ function = "USB2B";
+ groups = "USB2BXHP";
+ };
+
+ pinctrl_usb2bxh2a_default: usb2bxh2a-default {
+ function = "USB2B";
+ groups = "USB2BXH2A";
+ };
+
+ pinctrl_usb2bxhp2a_default: usb2bxhp2a-default {
+ function = "USB2B";
+ groups = "USB2BXHP2A";
+ };
+
+ pinctrl_usb2bhpd0_default: usb2bhpd0-default {
+ function = "USB2B";
+ groups = "USB2BHPD0";
+ };
+
+ pinctrl_usb2bd0_default: usb2bd0-default {
+ function = "USB2B";
+ groups = "USB2BD0";
+ };
+
+ pinctrl_usb2bh_default: usb2bh-default {
+ function = "USB2B";
+ groups = "USB2BH";
+ };
+
+ pinctrl_usb2bhp_default: usb2bhp-default {
+ function = "USB2B";
+ groups = "USB2BHP";
+ };
+
+ pinctrl_jtagm0_default: jtagm0-default {
+ function = "JTAG0";
+ groups = "JTAGM0";
+ };
+
+ pinctrl_jtag_psp_default: jtag-psp-default {
+ function = "JTAG0";
+ groups = "PSP";
+ };
+
+ pinctrl_jtag_ssp_default: jtag-ssp-default {
+ function = "JTAG0";
+ groups = "SSP";
+ };
+
+ pinctrl_jtag_tsp_default: jtag-tsp-default {
+ function = "JTAG0";
+ groups = "TSP";
+ };
+
+ pinctrl_jtag_ddr_default: jtag-ddr-default {
+ function = "JTAG0";
+ groups = "DDR";
+ };
+
+ pinctrl_jtag_usb3a_default: jtag-usb3a-default {
+ function = "JTAG0";
+ groups = "USB3A";
+ };
+
+ pinctrl_jtag_usb3b_default: jtag-usb3b-default {
+ function = "JTAG0";
+ groups = "USB3B";
+ };
+
+ pinctrl_jtag_pciea_default: jtag-pciea-default {
+ function = "JTAG0";
+ groups = "PCIEA";
+ };
+
+ pinctrl_jtag_pcieb_default: jtag-pcieb-default {
+ function = "JTAG0";
+ groups = "PCIEB";
+ };
+
+ pinctrl_pcierc0_perst_default: pcierc0-perst-default {
+ function = "PCIERC";
+ groups = "PCIERC0PERST";
+ };
+
+ pinctrl_pcierc1_perst_default: pcierc1-perst-default {
+ function = "PCIERC";
+ groups = "PCIERC1PERST";
+ };
+};
+
+&pinctrl1 {
+ pinctrl_sgpm0_default: sgpm0-default {
+ function = "SGPM0";
+ groups = "SGPM0";
+ };
+
+ pinctrl_sgpm1_default: sgpm1-default {
+ function = "SGPM1";
+ groups = "SGPM1";
+ };
+
+ pinctrl_sgps_default: sgps-default {
+ function = "SGPS";
+ groups = "SGPS";
+ };
+
+ pinctrl_adc0_default: adc0-default {
+ function = "ADC0";
+ groups = "ADC0";
+ };
+
+ pinctrl_adc1_default: adc1-default {
+ function = "ADC1";
+ groups = "ADC1";
+ };
+
+ pinctrl_adc2_default: adc2-default {
+ function = "ADC2";
+ groups = "ADC2";
+ };
+
+ pinctrl_adc3_default: adc3-default {
+ function = "ADC3";
+ groups = "ADC3";
+ };
+
+ pinctrl_adc4_default: adc4-default {
+ function = "ADC4";
+ groups = "ADC4";
+ };
+
+ pinctrl_adc5_default: adc5-default {
+ function = "ADC5";
+ groups = "ADC5";
+ };
+
+ pinctrl_adc6_default: adc6-default {
+ function = "ADC6";
+ groups = "ADC6";
+ };
+
+ pinctrl_adc7_default: adc7-default {
+ function = "ADC7";
+ groups = "ADC7";
+ };
+
+ pinctrl_adc8_default: adc8-default {
+ function = "ADC8";
+ groups = "ADC8";
+ };
+
+ pinctrl_adc9_default: adc9-default {
+ function = "ADC9";
+ groups = "ADC9";
+ };
+
+ pinctrl_adc10_default: adc10-default {
+ function = "ADC10";
+ groups = "ADC10";
+ };
+
+ pinctrl_adc11_default: adc11-default {
+ function = "ADC11";
+ groups = "ADC11";
+ };
+
+ pinctrl_adc12_default: adc12-default {
+ function = "ADC12";
+ groups = "ADC12";
+ };
+
+ pinctrl_adc13_default: adc13-default {
+ function = "ADC13";
+ groups = "ADC13";
+ };
+
+ pinctrl_adc14_default: adc14-default {
+ function = "ADC14";
+ groups = "ADC14";
+ };
+
+ pinctrl_adc15_default: adc15-default {
+ function = "ADC15";
+ groups = "ADC15";
+ };
+
+ pinctrl_pwm0_default: pwm0-default {
+ function = "PWM0";
+ groups = "PWM0";
+ };
+
+ pinctrl_pwm1_default: pwm1-default {
+ function = "PWM1";
+ groups = "PWM1";
+ };
+
+ pinctrl_pwm2_default: pwm2-default {
+ function = "PWM2";
+ groups = "PWM2";
+ };
+
+ pinctrl_pwm3_default: pwm3-default {
+ function = "PWM3";
+ groups = "PWM3";
+ };
+
+ pinctrl_pwm4_default: pwm4-default {
+ function = "PWM4";
+ groups = "PWM4";
+ };
+
+ pinctrl_pwm5_default: pwm5-default {
+ function = "PWM5";
+ groups = "PWM5";
+ };
+
+ pinctrl_pwm6_default: pwm6-default {
+ function = "PWM6";
+ groups = "PWM6";
+ };
+
+ pinctrl_pwm7_default: pwm7-default {
+ function = "PWM7";
+ groups = "PWM7";
+ };
+
+ pinctrl_pwm8_default: pwm8-default {
+ function = "PWM8";
+ groups = "PWM8";
+ };
+
+ pinctrl_pwm9_default: pwm9-default {
+ function = "PWM9";
+ groups = "PWM9";
+ };
+
+ pinctrl_pwm10_default: pwm10-default {
+ function = "PWM10";
+ groups = "PWM10";
+ };
+
+ pinctrl_pwm11_default: pwm11-default {
+ function = "PWM11";
+ groups = "PWM11";
+ };
+
+ pinctrl_pwm12_default: pwm12-default {
+ function = "PWM12";
+ groups = "PWM12";
+ };
+
+ pinctrl_pwm13_default: pwm13-default {
+ function = "PWM13";
+ groups = "PWM13";
+ };
+
+ pinctrl_pwm14_default: pwm14-default {
+ function = "PWM14";
+ groups = "PWM14";
+ };
+
+ pinctrl_pwm15_default: pwm15-default {
+ function = "PWM15";
+ groups = "PWM15";
+ };
+
+ pinctrl_tach0_default: tach0-default {
+ function = "TACH0";
+ groups = "TACH0";
+ };
+
+ pinctrl_tach1_default: tach1-default {
+ function = "TACH1";
+ groups = "TACH1";
+ };
+
+ pinctrl_tach2_default: tach2-default {
+ function = "TACH2";
+ groups = "TACH2";
+ };
+
+ pinctrl_tach3_default: tach3-default {
+ function = "TACH3";
+ groups = "TACH3";
+ };
+
+ pinctrl_tach4_default: tach4-default {
+ function = "TACH4";
+ groups = "TACH4";
+ };
+
+ pinctrl_tach5_default: tach5-default {
+ function = "TACH5";
+ groups = "TACH5";
+ };
+
+ pinctrl_tach6_default: tach6-default {
+ function = "TACH6";
+ groups = "TACH6";
+ };
+
+ pinctrl_tach7_default: tach7-default {
+ function = "TACH7";
+ groups = "TACH7";
+ };
+
+ pinctrl_tach8_default: tach8-default {
+ function = "TACH8";
+ groups = "TACH8";
+ };
+
+ pinctrl_tach9_default: tach9-default {
+ function = "TACH9";
+ groups = "TACH9";
+ };
+
+ pinctrl_tach10_default: tach10-default {
+ function = "TACH10";
+ groups = "TACH10";
+ };
+
+ pinctrl_tach11_default: tach11-default {
+ function = "TACH11";
+ groups = "TACH11";
+ };
+
+ pinctrl_tach12_default: tach12-default {
+ function = "TACH12";
+ groups = "TACH12";
+ };
+
+ pinctrl_tach13_default: tach13-default {
+ function = "TACH13";
+ groups = "TACH13";
+ };
+
+ pinctrl_tach14_default: tach14-default {
+ function = "TACH14";
+ groups = "TACH14";
+ };
+
+ pinctrl_tach15_default: tach15-default {
+ function = "TACH15";
+ groups = "TACH15";
+ };
+
+ pinctrl_jtagm1_default: jtagm1-default {
+ function = "JTAGM1";
+ groups = "JTAGM1";
+ };
+
+ pinctrl_mdio0_default: mdio0-default {
+ function = "MDIO0";
+ groups = "MDIO0";
+ };
+
+ pinctrl_mdio1_default: mdio1-default {
+ function = "MDIO1";
+ groups = "MDIO1";
+ };
+
+ pinctrl_mdio2_default: mdio2-default {
+ function = "MDIO2";
+ groups = "MDIO2";
+ };
+
+ pinctrl_rgmii0_default: rgmii0-default {
+ function = "RGMII0";
+ groups = "RGMII0";
+ };
+
+ pinctrl_rgmii1_default: rgmii1-default {
+ function = "RGMII1";
+ groups = "RGMII1";
+ };
+
+ pinctrl_rmii0_default: rmii0-default {
+ function = "RMII0";
+ groups = "RMII0";
+ };
+
+ pinctrl_rmii0_rclko_default: rmii0-rclko-default {
+ function = "RMII0RCLKO";
+ groups = "RMII0RCLKO";
+ };
+
+ pinctrl_rmii1_default: rmii1-default {
+ function = "RMII1";
+ groups = "RMII1";
+ };
+
+ pinctrl_rmii1_rclko_default: rmii1-rclko-default {
+ function = "RMII1RCLKO";
+ groups = "RMII1RCLKO";
+ };
+
+ pinctrl_sgmii_default: sgmii-default {
+ function = "SGMII";
+ groups = "SGMII";
+ };
+
+ pinctrl_fwspi_quad_default: fwspi-quad-default {
+ function = "FWQSPI";
+ groups = "FWQSPI";
+ };
+
+ pinctrl_fsi0_default: fsi0-default {
+ function = "FSI0";
+ groups = "FSI0";
+ };
+
+ pinctrl_fsi1_default: fsi1-default {
+ function = "FSI1";
+ groups = "FSI1";
+ };
+
+ pinctrl_fsi2_default: fsi2-default {
+ function = "FSI2";
+ groups = "FSI2";
+ };
+
+ pinctrl_fsi3_default: fsi3-default {
+ function = "FSI3";
+ groups = "FSI3";
+ };
+
+ pinctrl_spi0_default: spi0-default {
+ function = "SPI0";
+ groups = "SPI0";
+ };
+
+ pinctrl_spi0_quad_default: spi0-quad-default {
+ function = "QSPI0";
+ groups = "QSPI0";
+ };
+
+ pinctrl_spi0_cs1_default: spi0-cs1-default {
+ function = "SPI0CS1";
+ groups = "SPI0CS1";
+ };
+
+ pinctrl_spi1_default: spi1-default {
+ function = "SPI1";
+ groups = "SPI1";
+ };
+
+ pinctrl_spi1_quad_default: spi1-quad-default {
+ function = "QSPI1";
+ groups = "QSPI1";
+ };
+
+ pinctrl_spi1_cs1_default: spi1-cs1-default {
+ function = "SPI1CS1";
+ groups = "SPI1CS1";
+ };
+
+ pinctrl_spi2_default: spi2-default {
+ function = "SPI2";
+ groups = "SPI2";
+ };
+
+ pinctrl_spi2_quad_default: spi2-quad-default {
+ function = "QSPI2";
+ groups = "QSPI2";
+ };
+
+ pinctrl_spi2_cs1_default: spi2-cs1-default {
+ function = "SPI2CS1";
+ groups = "SPI2CS1";
+ };
+
+ pinctrl_espi0_default: espi0-default {
+ function = "ESPI0";
+ groups = "ESPI0";
+ };
+
+ pinctrl_espi1_default: espi1-default {
+ function = "ESPI1";
+ groups = "ESPI1";
+ };
+
+ pinctrl_lpc0_default: lpc0-default {
+ function = "LPC0";
+ groups = "LPC0";
+ };
+
+ pinctrl_lpc1_default: lpc1-default {
+ function = "LPC1";
+ groups = "LPC1";
+ };
+
+ pinctrl_vpi_default: vpi-default {
+ function = "VPI";
+ groups = "VPI";
+ };
+
+ pinctrl_sd_default: sd-default {
+ function = "SD";
+ groups = "SD";
+ };
+
+ pinctrl_hvi3c0_default: hvi3c0-default {
+ function = "I3C0";
+ groups = "HVI3C0";
+ };
+
+ pinctrl_hvi3c1_default: hvi3c1-default {
+ function = "I3C1";
+ groups = "HVI3C1";
+ };
+
+ pinctrl_hvi3c2_default: hvi3c2-default {
+ function = "I3C2";
+ groups = "HVI3C2";
+ };
+
+ pinctrl_hvi3c3_default: hvi3c3-default {
+ function = "I3C3";
+ groups = "HVI3C3";
+ };
+
+ pinctrl_i3c4_default: i3c4-default {
+ function = "I3C4";
+ groups = "I3C4";
+ };
+
+ pinctrl_i3c5_default: i3c5-default {
+ function = "I3C5";
+ groups = "I3C5";
+ };
+
+ pinctrl_i3c6_default: i3c6-default {
+ function = "I3C6";
+ groups = "I3C6";
+ };
+
+ pinctrl_i3c7_default: i3c7-default {
+ function = "I3C7";
+ groups = "I3C7";
+ };
+
+ pinctrl_i3c8_default: i3c8-default {
+ function = "I3C8";
+ groups = "I3C8";
+ };
+
+ pinctrl_i3c9_default: i3c9-default {
+ function = "I3C9";
+ groups = "I3C9";
+ };
+
+ pinctrl_i3c10_default: i3c10-default {
+ function = "I3C10";
+ groups = "I3C10";
+ };
+
+ pinctrl_i3c11_default: i3c11-default {
+ function = "I3C11";
+ groups = "I3C11";
+ };
+
+ pinctrl_hvi3c12_default: hvi3c12-default {
+ function = "I3C12";
+ groups = "HVI3C12";
+ };
+
+ pinctrl_hvi3c13_default: hvi3c13-default {
+ function = "I3C13";
+ groups = "HVI3C13";
+ };
+
+ pinctrl_hvi3c14_default: hvi3c14-default {
+ function = "I3C14";
+ groups = "HVI3C14";
+ };
+
+ pinctrl_hvi3c15_default: hvi3c15-default {
+ function = "I3C15";
+ groups = "HVI3C15";
+ };
+
+ pinctrl_tach0_default: tach0-default {
+ function = "TACH0";
+ groups = "TACH0";
+ };
+
+ pinctrl_tach1_default: tach1-default {
+ function = "TACH1";
+ groups = "TACH1";
+ };
+
+ pinctrl_tach2_default: tach2-default {
+ function = "TACH2";
+ groups = "TACH2";
+ };
+
+ pinctrl_tach3_default: tach3-default {
+ function = "TACH3";
+ groups = "TACH3";
+ };
+
+ pinctrl_tach4_default: tach4-default {
+ function = "TACH4";
+ groups = "TACH4";
+ };
+
+ pinctrl_tach5_default: tach5-default {
+ function = "TACH5";
+ groups = "TACH5";
+ };
+
+ pinctrl_tach6_default: tach6-default {
+ function = "TACH6";
+ groups = "TACH6";
+ };
+
+ pinctrl_tach7_default: tach7-default {
+ function = "TACH7";
+ groups = "TACH7";
+ };
+
+ pinctrl_tach8_default: tach8-default {
+ function = "TACH8";
+ groups = "TACH8";
+ };
+
+ pinctrl_tach9_default: tach9-default {
+ function = "TACH9";
+ groups = "TACH9";
+ };
+
+ pinctrl_tach10_default: tach10-default {
+ function = "TACH10";
+ groups = "TACH10";
+ };
+
+ pinctrl_tach11_default: tach11-default {
+ function = "TACH11";
+ groups = "TACH11";
+ };
+
+ pinctrl_tach12_default: tach12-default {
+ function = "TACH12";
+ groups = "TACH12";
+ };
+
+ pinctrl_tach13_default: tach13-default {
+ function = "TACH13";
+ groups = "TACH13";
+ };
+
+ pinctrl_tach14_default: tach14-default {
+ function = "TACH14";
+ groups = "TACH14";
+ };
+
+ pinctrl_tach15_default: tach15-default {
+ function = "TACH15";
+ groups = "TACH15";
+ };
+
+ pinctrl_thru0_default: thru0-default {
+ function = "THRU0";
+ groups = "THRU0";
+ };
+
+ pinctrl_thru1_default: thru1-default {
+ function = "THRU1";
+ groups = "THRU1";
+ };
+
+ pinctrl_thru2_default: thru2-default {
+ function = "THRU2";
+ groups = "THRU2";
+ };
+
+ pinctrl_thru3_default: thru3-default {
+ function = "THRU3";
+ groups = "THRU3";
+ };
+
+ pinctrl_ncts5_default: ncts5-default {
+ function = "NCTS5";
+ groups = "NCTS5";
+ };
+
+ pinctrl_ndcd5_default: ndcd5-default {
+ function = "NDCD5";
+ groups = "NDCD5";
+ };
+
+ pinctrl_ndsr5_default: ndsr5-default {
+ function = "NDSR5";
+ groups = "NDSR5";
+ };
+
+ pinctrl_nri5_default: nri5-default {
+ function = "NRI5";
+ groups = "NRI5";
+ };
+
+ pinctrl_i2c0_default: i2c0-default {
+ function = "I2C0";
+ groups = "I2C0";
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ function = "I2C1";
+ groups = "I2C1";
+ };
+
+ pinctrl_i2c2_default: i2c2-default {
+ function = "I2C2";
+ groups = "I2C2";
+ };
+
+ pinctrl_i2c3_default: i2c3-default {
+ function = "I2C3";
+ groups = "I2C3";
+ };
+
+ pinctrl_i2c4_default: i2c4-default {
+ function = "I2C4";
+ groups = "I2C4";
+ };
+
+ pinctrl_i2c5_default: i2c5-default {
+ function = "I2C5";
+ groups = "I2C5";
+ };
+
+ pinctrl_i2c6_default: i2c6-default {
+ function = "I2C6";
+ groups = "I2C6";
+ };
+
+ pinctrl_i2c7_default: i2c7-default {
+ function = "I2C7";
+ groups = "I2C7";
+ };
+
+ pinctrl_i2c8_default: i2c8-default {
+ function = "I2C8";
+ groups = "I2C8";
+ };
+
+ pinctrl_i2c9_default: i2c9-default {
+ function = "I2C9";
+ groups = "I2C9";
+ };
+
+ pinctrl_i2c10_default: i2c10-default {
+ function = "I2C10";
+ groups = "I2C10";
+ };
+
+ pinctrl_i2c11_default: i2c11-default {
+ function = "I2C11";
+ groups = "I2C11";
+ };
+
+ pinctrl_i2c12_default: i2c12-default {
+ function = "I2C12";
+ groups = "I2C12";
+ };
+
+ pinctrl_i2c13_default: i2c13-default {
+ function = "I2C13";
+ groups = "I2C13";
+ };
+
+ pinctrl_i2c14_default: i2c14-default {
+ function = "I2C14";
+ groups = "I2C14";
+ };
+
+ pinctrl_i2c15_default: i2c15-default {
+ function = "I2C15";
+ groups = "I2C15";
+ };
+
+ pinctrl_salt0_default: salt0-default {
+ function = "SALT0";
+ groups = "SALT0";
+ };
+
+ pinctrl_salt1_default: salt1-default {
+ function = "SALT1";
+ groups = "SALT1";
+ };
+
+ pinctrl_salt2_default: salt2-default {
+ function = "SALT2";
+ groups = "SALT2";
+ };
+
+ pinctrl_salt3_default: salt3-default {
+ function = "SALT3";
+ groups = "SALT3";
+ };
+
+ pinctrl_salt4_default: salt4-default {
+ function = "SALT4";
+ groups = "SALT4";
+ };
+
+ pinctrl_salt5_default: salt5-default {
+ function = "SALT5";
+ groups = "SALT5";
+ };
+
+ pinctrl_salt6_default: salt6-default {
+ function = "SALT6";
+ groups = "SALT6";
+ };
+
+ pinctrl_salt7_default: salt7-default {
+ function = "SALT7";
+ groups = "SALT7";
+ };
+
+ pinctrl_salt8_default: salt8-default {
+ function = "SALT8";
+ groups = "SALT8";
+ };
+
+ pinctrl_salt9_default: salt9-default {
+ function = "SALT9";
+ groups = "SALT9";
+ };
+
+ pinctrl_salt10_default: salt10-default {
+ function = "SALT10";
+ groups = "SALT10";
+ };
+
+ pinctrl_salt11_default: salt11-default {
+ function = "SALT11";
+ groups = "SALT11";
+ };
+
+ pinctrl_salt12_default: salt12-default {
+ function = "SALT12";
+ groups = "SALT12";
+ };
+
+ pinctrl_salt13_default: salt13-default {
+ function = "SALT13";
+ groups = "SALT13";
+ };
+
+ pinctrl_salt14_default: salt14-default {
+ function = "SALT14";
+ groups = "SALT14";
+ };
+
+ pinctrl_salt15_default: salt15-default {
+ function = "SALT15";
+ groups = "SALT15";
+ };
+
+ pinctrl_can_default: can-default {
+ function = "CANBUS";
+ groups = "CANBUS";
+ };
+ pinctrl_di2c0_default: di2c0-default {
+ function = "I2C0";
+ groups = "DI2C0";
+ };
+
+ pinctrl_di2c1_default: di2c1-default {
+ function = "I2C1";
+ groups = "DI2C1";
+ };
+
+ pinctrl_di2c2_default: di2c2-default {
+ function = "I2C2";
+ groups = "DI2C2";
+ };
+
+ pinctrl_di2c3_default: di2c3-default {
+ function = "I2C3";
+ groups = "DI2C3";
+ };
+ pinctrl_di2c8_default: di2c8-default {
+ function = "I2C8";
+ groups = "DI2C8";
+ };
+
+ pinctrl_di2c9_default: di2c9-default {
+ function = "I2C9";
+ groups = "DI2C9";
+ };
+
+ pinctrl_di2c10_default: di2c10-default {
+ function = "I2C10";
+ groups = "DI2C10";
+ };
+
+ pinctrl_di2c11_default: di2c11-default {
+ function = "I2C11";
+ groups = "DI2C11";
+ };
+
+ pinctrl_di2c12_default: id2c12-default {
+ function = "I2C12";
+ groups = "DI2C12";
+ };
+
+ pinctrl_di2c13_default: di2c13-default {
+ function = "I2C13";
+ groups = "DI2C13";
+ };
+
+ pinctrl_di2c14_default: di2c14-default {
+ function = "I2C14";
+ groups = "DI2C14";
+ };
+
+ pinctrl_di2c15_default: di2c15-default {
+ function = "I2C15";
+ groups = "DI2C15";
+ };
+
+ pinctrl_ncts0_default: ncts0-default {
+ function = "UART0";
+ groups = "NCTS0";
+ };
+
+ pinctrl_ndcd0_default: ndcd0-default {
+ function = "UART0";
+ groups = "NDCD0";
+ };
+
+ pinctrl_ndsr0_default: ndsr0-default {
+ function = "UART0";
+ groups = "NDSR0";
+ };
+
+ pinctrl_nri0_default: nri0-default {
+ function = "UART0";
+ groups = "NRI0";
+ };
+
+ pinctrl_ndtr0_default: ndtr0-default {
+ function = "UART0";
+ groups = "NDTR0";
+ };
+
+ pinctrl_nrts0_default: nrts0-default {
+ function = "UART0";
+ groups = "NRTS0";
+ };
+
+ pinctrl_txd0_default: txd0-default {
+ function = "UART0";
+ groups = "TXD0";
+ };
+
+ pinctrl_rxd0_default: rxd0-default {
+ function = "UART0";
+ groups = "RXD0";
+ };
+
+ pinctrl_ncts1_default: ncts1-default {
+ function = "UART1";
+ groups = "NCTS1";
+ };
+
+ pinctrl_ndcd1_default: ndcd1-default {
+ function = "UART1";
+ groups = "NDCD1";
+ };
+
+ pinctrl_ndsr1_default: ndsr1-default {
+ function = "UART1";
+ groups = "NDSR1";
+ };
+
+ pinctrl_nri1_default: nri1-default {
+ function = "UART1";
+ groups = "NRI1";
+ };
+
+ pinctrl_ndtr1_default: ndtr1-default {
+ function = "UART1";
+ groups = "NDTR1";
+ };
+
+ pinctrl_nrts1_default: nrts1-default {
+ function = "UART1";
+ groups = "NRTS1";
+ };
+
+ pinctrl_txd1_default: txd1-default {
+ function = "UART1";
+ groups = "TXD1";
+ };
+
+ pinctrl_rxd1_default: rxd1-default {
+ function = "UART1";
+ groups = "RXD1";
+ };
+
+ pinctrl_txd2_default: txd2-default {
+ function = "UART2";
+ groups = "TXD2";
+ };
+
+ pinctrl_rxd2_default: rxd2-default {
+ function = "UART2";
+ groups = "RXD2";
+ };
+
+ pinctrl_txd3_default: txd3-default {
+ function = "UART3";
+ groups = "TXD3";
+ };
+
+ pinctrl_rxd3_default: rxd3-default {
+ function = "UART3";
+ groups = "RXD3";
+ };
+
+ pinctrl_ncts5_default: ncts5-default {
+ function = "UART5";
+ groups = "NCTS5";
+ };
+
+ pinctrl_ndcd5_default: ndcd5-default {
+ function = "UART5";
+ groups = "NDCD5";
+ };
+
+ pinctrl_ndsr5_default: ndsr5-default {
+ function = "UART5";
+ groups = "NDSR5";
+ };
+
+ pinctrl_nri5_default: nri5-default {
+ function = "UART5";
+ groups = "NRI5";
+ };
+
+ pinctrl_ndtr5_default: ndtr5-default {
+ function = "UART5";
+ groups = "NDTR5";
+ };
+
+ pinctrl_nrts5_default: nrts5-default {
+ function = "UART5";
+ groups = "NRTS5";
+ };
+
+ pinctrl_txd5_default: txd5-default {
+ function = "UART5";
+ groups = "TXD5";
+ };
+
+ pinctrl_rxd5_default: rxd5-default {
+ function = "UART5";
+ groups = "RXD5";
+ };
+
+ pinctrl_ncts6_default: ncts6-default {
+ function = "UART6";
+ groups = "NCTS6";
+ };
+
+ pinctrl_ndcd6_default: ndcd6-default {
+ function = "UART6";
+ groups = "NDCD6";
+ };
+
+ pinctrl_ndsr6_default: ndsr6-default {
+ function = "UART6";
+ groups = "NDSR6";
+ };
+
+ pinctrl_nri6_default: nri6-default {
+ function = "UART6";
+ groups = "NRI6";
+ };
+
+ pinctrl_ndtr6_default: ndtr6-default {
+ function = "UART6";
+ groups = "NDTR6";
+ };
+
+ pinctrl_nrts6_default: nrts6-default {
+ function = "UART6";
+ groups = "NRTS6";
+ };
+
+ pinctrl_txd6_default: txd6-default {
+ function = "UART6";
+ groups = "TXD6";
+ };
+
+ pinctrl_rxd6_default: rxd6-default {
+ function = "UART6";
+ groups = "RXD6";
+ };
+
+ pinctrl_txd7_default: txd7-default {
+ function = "UART7";
+ groups = "TXD7";
+ };
+
+ pinctrl_rxd7_default: rxd7-default {
+ function = "UART7";
+ groups = "RXD7";
+ };
+
+ pinctrl_txd8_default: txd8-default {
+ function = "UART8";
+ groups = "TXD8";
+ };
+
+ pinctrl_rxd8_default: rxd8-default {
+ function = "UART8";
+ groups = "RXD8";
+ };
+
+ pinctrl_txd9_default: txd9-default {
+ function = "UART9";
+ groups = "TXD9";
+ };
+
+ pinctrl_rxd9_default: rxd9-default {
+ function = "UART9";
+ groups = "RXD9";
+ };
+
+ pinctrl_txd10_default: txd10-default {
+ function = "UART10";
+ groups = "TXD10";
+ };
+
+ pinctrl_rxd10_default: rxd10-default {
+ function = "UART10";
+ groups = "RXD10";
+ };
+
+ pinctrl_txd11_default: txd11-default {
+ function = "UART11";
+ groups = "TXD11";
+ };
+
+ pinctrl_rxd11_default: rxd11-default {
+ function = "UART11";
+ groups = "RXD11";
+ };
+
+ pinctrl_pcierc2_perst_default: pcierc2-perst-default {
+ function = "PCIERC";
+ groups = "PE2SGRSTN";
+ };
+
+ pinctrl_usb2cud_default: usb2cud-default {
+ function = "USB2C";
+ groups = "USB2CUD";
+ };
+
+ pinctrl_usb2cd_default: usb2cd-default {
+ function = "USB2C";
+ groups = "USB2CD";
+ };
+
+ pinctrl_usb2ch_default: usb2ch-default {
+ function = "USB2C";
+ groups = "USB2CH";
+ };
+
+ pinctrl_usb2cu_default: usb2cu-default {
+ function = "USB2C";
+ groups = "USB2CU";
+ };
+
+ pinctrl_usb2dd_default: usb2dd-default {
+ function = "USB2D";
+ groups = "USB2DD";
+ };
+
+ pinctrl_usb2dh_default: usb2dh-default {
+ function = "USB2D";
+ groups = "USB2DH";
+ };
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v2 4/4] arm64: dts: add AST27xx pinctrl configuration nodes
2025-09-04 10:34 ` [PATCH v2 4/4] arm64: dts: add AST27xx pinctrl configuration nodes Billy Tsai
@ 2025-09-04 14:26 ` Rob Herring
0 siblings, 0 replies; 11+ messages in thread
From: Rob Herring @ 2025-09-04 14:26 UTC (permalink / raw)
To: Billy Tsai
Cc: lee, krzk+dt, conor+dt, joel, andrew, linus.walleij, brgl,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, openbmc,
linux-gpio, BMC-SW
On Thu, Sep 4, 2025 at 5:34 AM Billy Tsai <billy_tsai@aspeedtech.com> wrote:
>
> Add pinctrl0 and pinctrl1 nodes for AST27xx SoC0 and SoC1 to configure
> the pinmux settings for each ball.
>
> Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
> ---
> .../boot/dts/aspeed/aspeed-g7-pinctrl.dtsi | 1359 +++++++++++++++++
> 1 file changed, 1359 insertions(+)
> create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-g7-pinctrl.dtsi
This file isn't used anywhere and is therefore untestable. If there is
a dependency to apply, then please specify that using b4. But then
this would also need to be included somewhere.
Rob
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 0/4] Add pinctrl support for AST2700 SoC
2025-09-04 10:33 [PATCH v2 0/4] Add pinctrl support for AST2700 SoC Billy Tsai
` (2 preceding siblings ...)
2025-09-04 10:34 ` [PATCH v2 4/4] arm64: dts: add AST27xx pinctrl configuration nodes Billy Tsai
@ 2025-09-05 8:12 ` Krzysztof Kozlowski
[not found] ` <20250904103401.88287-4-billy_tsai@aspeedtech.com>
4 siblings, 0 replies; 11+ messages in thread
From: Krzysztof Kozlowski @ 2025-09-05 8:12 UTC (permalink / raw)
To: Billy Tsai
Cc: lee, robh, krzk+dt, conor+dt, joel, andrew, linus.walleij, brgl,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, openbmc,
linux-gpio, BMC-SW
On Thu, Sep 04, 2025 at 06:33:57PM +0800, Billy Tsai wrote:
> Document and add the pinctrl driver for AST2700 SoC.
>
> Changes since v1:
> - Update pinctrl aspeed binding files.
Anything is an update.
Really too vague and some time ago I am sure I complained about this to
Aspeed.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/4] dt-bindings: mfd: aspeed,ast2x00-scu: Support ast2700 pinctrl
2025-09-04 10:33 ` [PATCH v2 1/4] dt-bindings: mfd: aspeed,ast2x00-scu: Support ast2700 pinctrl Billy Tsai
@ 2025-09-05 8:13 ` Krzysztof Kozlowski
0 siblings, 0 replies; 11+ messages in thread
From: Krzysztof Kozlowski @ 2025-09-05 8:13 UTC (permalink / raw)
To: Billy Tsai
Cc: lee, robh, krzk+dt, conor+dt, joel, andrew, linus.walleij, brgl,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, openbmc,
linux-gpio, BMC-SW
On Thu, Sep 04, 2025 at 06:33:58PM +0800, Billy Tsai wrote:
> Add the ast2700 pinctrl compatible string.
> "aspeed,ast2700-soc0-pinctrl" and "aspeed,ast2700-soc1-pinctrl"
Nothing improved, completely redundant commit msg. We see this from the
diff.
You got comment last time and it applies everywhere.
>
> Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 2/4] dt-bindings: pinctrl: aspeed: Add support for AST27xx
2025-09-04 10:33 ` [PATCH v2 2/4] dt-bindings: pinctrl: aspeed: Add support for AST27xx Billy Tsai
@ 2025-09-05 8:16 ` Krzysztof Kozlowski
0 siblings, 0 replies; 11+ messages in thread
From: Krzysztof Kozlowski @ 2025-09-05 8:16 UTC (permalink / raw)
To: Billy Tsai
Cc: lee, robh, krzk+dt, conor+dt, joel, andrew, linus.walleij, brgl,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, openbmc,
linux-gpio, BMC-SW
On Thu, Sep 04, 2025 at 06:33:59PM +0800, Billy Tsai wrote:
> Add bindings for the pin controller found in the ASPEED AST27xx SoC.
> The ASPEED AST2700 SoC contains two separate pin controllers, each
> managed by a distinct System Control Unit (SCU).
> Because these two controllers have different register maps, control
> different sets of pins, support different pin configuration options, and
> implement different multi-function switch logic, they are not compatible.
> Therefore, two separate device tree bindings,'aspeed,ast2700-soc0-pinctrl'
> and 'aspeed,ast2700-soc1-pinctrl', are introduced.
>
> Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
> ---
> .../pinctrl/aspeed,ast2700-soc0-pinctrl.yaml | 115 +++++
> .../pinctrl/aspeed,ast2700-soc1-pinctrl.yaml | 435 ++++++++++++++++++
> 2 files changed, 550 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml
> create mode 100644 Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml
> new file mode 100644
> index 000000000000..0fee62259250
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml
> @@ -0,0 +1,115 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ASPEED AST2700 SoC0 Pin Controller
> +
> +maintainers:
> + - Billy Tsai <billy_tsai@aspeedtech.com>
> +
> +description: |
Drop |
> + Bindings for the ASPEED AST2700 SoC0 Pin Controller.
You should explain here hardware, not say what bindings are (we know
what bindings are) or copy title, either.
> +
> +properties:
> + compatible:
> + const: aspeed,ast2700-soc0-pinctrl
> +
> +additionalProperties:
You should restrict nodes with pattern to common suffix or prefix, e.g.
group, state, pins. See other pinctrl bindings for examples.
> + $ref: pinmux-node.yaml#
> + additionalProperties: false
> +
> + properties:
> + function:
> + enum:
> + - EMMC
> + - VGADDC
> + - USB3A
> + - USB2A
> + - USB3B
> + - USB2B
> + - JTAG0
> + - PCIERC
> +
> + groups:
> + enum:
> + - EMMCG1
> + - EMMCG4
> + - EMMCG8
> + - EMMCWPN
> + - EMMCCDN
> + - VGADDC
> + - USB3AXHD
> + - USB3AXHPD
> + - USB3AXH
> + - USB3AXHP
> + - USB3AXH2B
> + - USB3AXHP2B
> + - USB2AXHD1
> + - USB2AXHPD1
> + - USB2AD1
> + - USB2AXH
> + - USB2AXHP
> + - USB2AXH2B
> + - USB2AXHP2B
> + - USB2AHPD0
> + - USB2AD0
> + - USB2AH
> + - USB2AHP
> + - USB3BXHD
> + - USB3BXHPD
> + - USB3BXH
> + - USB3BXHP
> + - USB3BXH2A
> + - USB3BXHP2A
> + - USB2BXHD1
> + - USB2BXHPD1
> + - USB2BD1
> + - USB2BXH
> + - USB2BXHP
> + - USB2BXH2A
> + - USB2BXHP2A
> + - USB2BHPD0
> + - USB2BD0
> + - USB2BH
> + - USB2BHP
> + - JTAGM0
> + - PSP
> + - SSP
> + - TSP
> + - DDR
> + - USB3A
> + - USB3B
> + - PCIEA
> + - PCIEB
> + - PCIERC0PERST
> + - PCIERC1PERST
> +
> + pins:
> + $ref: /schemas/types.yaml#/definitions/string-array
> + drive-strength:
> + minimum: 0
> + maximum: 15
> +
> +allOf:
> + - $ref: pinctrl.yaml#
> +
> +required:
> + - compatible
> +
> +examples:
> + - |
> + pinctrl0: pinctrl{
DTS coding style - missing space.
Unused label.
And you did not implement Rob's comment.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 3/4] pinctrl: aspeed: Add AST2700 pinmux support
[not found] ` <20250904103401.88287-4-billy_tsai@aspeedtech.com>
@ 2025-09-06 15:59 ` kernel test robot
2025-09-25 4:48 ` Andrew Jeffery
1 sibling, 0 replies; 11+ messages in thread
From: kernel test robot @ 2025-09-06 15:59 UTC (permalink / raw)
To: Billy Tsai, lee, robh, krzk+dt, conor+dt, joel, andrew,
linus.walleij, brgl, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel, openbmc, linux-gpio, BMC-SW
Cc: oe-kbuild-all
Hi Billy,
kernel test robot noticed the following build warnings:
[auto build test WARNING on linusw-pinctrl/devel]
[also build test WARNING on linusw-pinctrl/for-next robh/for-next lee-leds/for-leds-next linus/master v6.17-rc4 next-20250905]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Billy-Tsai/dt-bindings-mfd-aspeed-ast2x00-scu-Support-ast2700-pinctrl/20250904-184115
base: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git devel
patch link: https://lore.kernel.org/r/20250904103401.88287-4-billy_tsai%40aspeedtech.com
patch subject: [PATCH v2 3/4] pinctrl: aspeed: Add AST2700 pinmux support
config: arm-allyesconfig (https://download.01.org/0day-ci/archive/20250906/202509062340.wX64fW0j-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 15.1.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250906/202509062340.wX64fW0j-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202509062340.wX64fW0j-lkp@intel.com/
All warnings (new ones prefixed by >>):
In file included from drivers/pinctrl/aspeed/pinctrl-aspeed.h:15,
from drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c:18:
>> drivers/pinctrl/aspeed/pinmux-aspeed.h:741:26: warning: 'group_pins_LTPI_I2C3' defined but not used [-Wunused-const-variable=]
741 | #define GROUP_SYM(group) group_pins_ ## group
| ^~~~~~~~~~~
drivers/pinctrl/aspeed/pinmux-aspeed.h:743:26: note: in expansion of macro 'GROUP_SYM'
743 | static const int GROUP_SYM(group)[] = { __VA_ARGS__ }
| ^~~~~~~~~
drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c:479:1: note: in expansion of macro 'GROUP_DECL'
479 | GROUP_DECL(LTPI_I2C3, J9, J10);
| ^~~~~~~~~~
>> drivers/pinctrl/aspeed/pinmux-aspeed.h:741:26: warning: 'group_pins_LTPI_I2C2' defined but not used [-Wunused-const-variable=]
741 | #define GROUP_SYM(group) group_pins_ ## group
| ^~~~~~~~~~~
drivers/pinctrl/aspeed/pinmux-aspeed.h:743:26: note: in expansion of macro 'GROUP_SYM'
743 | static const int GROUP_SYM(group)[] = { __VA_ARGS__ }
| ^~~~~~~~~
drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c:478:1: note: in expansion of macro 'GROUP_DECL'
478 | GROUP_DECL(LTPI_I2C2, H10, H11);
| ^~~~~~~~~~
>> drivers/pinctrl/aspeed/pinmux-aspeed.h:741:26: warning: 'group_pins_LTPI_I2C1' defined but not used [-Wunused-const-variable=]
741 | #define GROUP_SYM(group) group_pins_ ## group
| ^~~~~~~~~~~
drivers/pinctrl/aspeed/pinmux-aspeed.h:743:26: note: in expansion of macro 'GROUP_SYM'
743 | static const int GROUP_SYM(group)[] = { __VA_ARGS__ }
| ^~~~~~~~~
drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c:477:1: note: in expansion of macro 'GROUP_DECL'
477 | GROUP_DECL(LTPI_I2C1, H8, H9);
| ^~~~~~~~~~
>> drivers/pinctrl/aspeed/pinmux-aspeed.h:741:26: warning: 'group_pins_LTPI_I2C0' defined but not used [-Wunused-const-variable=]
741 | #define GROUP_SYM(group) group_pins_ ## group
| ^~~~~~~~~~~
drivers/pinctrl/aspeed/pinmux-aspeed.h:743:26: note: in expansion of macro 'GROUP_SYM'
743 | static const int GROUP_SYM(group)[] = { __VA_ARGS__ }
| ^~~~~~~~~
drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c:476:1: note: in expansion of macro 'GROUP_DECL'
476 | GROUP_DECL(LTPI_I2C0, G11, H7);
| ^~~~~~~~~~
vim +/group_pins_LTPI_I2C3 +741 drivers/pinctrl/aspeed/pinmux-aspeed.h
efa5623981b72f Andrew Jeffery 2019-06-28 655
7b388970816665 Andrew Jeffery 2019-07-29 656 #define PIN_DECL_(pin, ...) \
efa5623981b72f Andrew Jeffery 2019-06-28 657 static const struct aspeed_sig_expr **PIN_EXPRS_SYM(pin)[] = \
efa5623981b72f Andrew Jeffery 2019-06-28 658 { __VA_ARGS__, NULL }; \
efa5623981b72f Andrew Jeffery 2019-06-28 659 static const struct aspeed_pin_desc PIN_SYM(pin) = \
efa5623981b72f Andrew Jeffery 2019-06-28 660 { #pin, PIN_EXPRS_PTR(pin) }
efa5623981b72f Andrew Jeffery 2019-06-28 661
efa5623981b72f Andrew Jeffery 2019-06-28 662 /**
efa5623981b72f Andrew Jeffery 2019-06-28 663 * Declare a single signal pin
efa5623981b72f Andrew Jeffery 2019-06-28 664 *
efa5623981b72f Andrew Jeffery 2019-06-28 665 * @pin: The pin number
efa5623981b72f Andrew Jeffery 2019-06-28 666 * @other: Macro name for "other" functionality (subjected to stringification)
efa5623981b72f Andrew Jeffery 2019-06-28 667 * @sig: Macro name for the signal (subjected to stringification)
efa5623981b72f Andrew Jeffery 2019-06-28 668 *
efa5623981b72f Andrew Jeffery 2019-06-28 669 * For example:
efa5623981b72f Andrew Jeffery 2019-06-28 670 *
efa5623981b72f Andrew Jeffery 2019-06-28 671 * #define E3 80
efa5623981b72f Andrew Jeffery 2019-06-28 672 * SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC);
7b388970816665 Andrew Jeffery 2019-07-29 673 * PIN_DECL_1(E3, GPIOK0, SCL5);
efa5623981b72f Andrew Jeffery 2019-06-28 674 */
7b388970816665 Andrew Jeffery 2019-07-29 675 #define PIN_DECL_1(pin, other, sig) \
e7a96b0b7d1669 Andrew Jeffery 2019-07-29 676 SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
e7a96b0b7d1669 Andrew Jeffery 2019-07-29 677 PIN_DECL_(pin, SIG_EXPR_LIST_PTR(pin, sig), \
e7a96b0b7d1669 Andrew Jeffery 2019-07-29 678 SIG_EXPR_LIST_PTR(pin, other))
efa5623981b72f Andrew Jeffery 2019-06-28 679
efa5623981b72f Andrew Jeffery 2019-06-28 680 /**
efa5623981b72f Andrew Jeffery 2019-06-28 681 * Single signal, single function pin declaration
efa5623981b72f Andrew Jeffery 2019-06-28 682 *
efa5623981b72f Andrew Jeffery 2019-06-28 683 * @pin: The pin number
efa5623981b72f Andrew Jeffery 2019-06-28 684 * @other: Macro name for "other" functionality (subjected to stringification)
efa5623981b72f Andrew Jeffery 2019-06-28 685 * @sig: Macro name for the signal (subjected to stringification)
efa5623981b72f Andrew Jeffery 2019-06-28 686 * @...: Signal descriptors that define the function expression
efa5623981b72f Andrew Jeffery 2019-06-28 687 *
efa5623981b72f Andrew Jeffery 2019-06-28 688 * For example:
efa5623981b72f Andrew Jeffery 2019-06-28 689 *
efa5623981b72f Andrew Jeffery 2019-06-28 690 * SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2));
efa5623981b72f Andrew Jeffery 2019-06-28 691 */
efa5623981b72f Andrew Jeffery 2019-06-28 692 #define SSSF_PIN_DECL(pin, other, sig, ...) \
e7a96b0b7d1669 Andrew Jeffery 2019-07-29 693 SIG_EXPR_LIST_DECL_SESG(pin, sig, sig, __VA_ARGS__); \
e7a96b0b7d1669 Andrew Jeffery 2019-07-29 694 SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
e7a96b0b7d1669 Andrew Jeffery 2019-07-29 695 PIN_DECL_(pin, SIG_EXPR_LIST_PTR(pin, sig), \
e7a96b0b7d1669 Andrew Jeffery 2019-07-29 696 SIG_EXPR_LIST_PTR(pin, other)); \
efa5623981b72f Andrew Jeffery 2019-06-28 697 FUNC_GROUP_DECL(sig, pin)
27d1f73670774e Andrew Jeffery 2019-07-29 698 /**
27d1f73670774e Andrew Jeffery 2019-07-29 699 * Declare a two-signal pin
27d1f73670774e Andrew Jeffery 2019-07-29 700 *
27d1f73670774e Andrew Jeffery 2019-07-29 701 * @pin: The pin number
27d1f73670774e Andrew Jeffery 2019-07-29 702 * @other: Macro name for "other" functionality (subjected to stringification)
27d1f73670774e Andrew Jeffery 2019-07-29 703 * @high: Macro name for the highest priority signal functions
27d1f73670774e Andrew Jeffery 2019-07-29 704 * @low: Macro name for the low signal functions
27d1f73670774e Andrew Jeffery 2019-07-29 705 *
27d1f73670774e Andrew Jeffery 2019-07-29 706 * For example:
27d1f73670774e Andrew Jeffery 2019-07-29 707 *
27d1f73670774e Andrew Jeffery 2019-07-29 708 * #define A8 56
27d1f73670774e Andrew Jeffery 2019-07-29 709 * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
27d1f73670774e Andrew Jeffery 2019-07-29 710 * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
27d1f73670774e Andrew Jeffery 2019-07-29 711 * { HW_STRAP1, GENMASK(1, 0), 0, 0 });
27d1f73670774e Andrew Jeffery 2019-07-29 712 * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
27d1f73670774e Andrew Jeffery 2019-07-29 713 * SIG_EXPR_PTR(ROMD8, ROM16S));
27d1f73670774e Andrew Jeffery 2019-07-29 714 * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
27d1f73670774e Andrew Jeffery 2019-07-29 715 * PIN_DECL_2(A8, GPIOH0, ROMD8, NCTS6);
27d1f73670774e Andrew Jeffery 2019-07-29 716 */
27d1f73670774e Andrew Jeffery 2019-07-29 717 #define PIN_DECL_2(pin, other, high, low) \
e7a96b0b7d1669 Andrew Jeffery 2019-07-29 718 SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
27d1f73670774e Andrew Jeffery 2019-07-29 719 PIN_DECL_(pin, \
e7a96b0b7d1669 Andrew Jeffery 2019-07-29 720 SIG_EXPR_LIST_PTR(pin, high), \
e7a96b0b7d1669 Andrew Jeffery 2019-07-29 721 SIG_EXPR_LIST_PTR(pin, low), \
e7a96b0b7d1669 Andrew Jeffery 2019-07-29 722 SIG_EXPR_LIST_PTR(pin, other))
27d1f73670774e Andrew Jeffery 2019-07-29 723
27d1f73670774e Andrew Jeffery 2019-07-29 724 #define PIN_DECL_3(pin, other, high, medium, low) \
e7a96b0b7d1669 Andrew Jeffery 2019-07-29 725 SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
27d1f73670774e Andrew Jeffery 2019-07-29 726 PIN_DECL_(pin, \
e7a96b0b7d1669 Andrew Jeffery 2019-07-29 727 SIG_EXPR_LIST_PTR(pin, high), \
e7a96b0b7d1669 Andrew Jeffery 2019-07-29 728 SIG_EXPR_LIST_PTR(pin, medium), \
e7a96b0b7d1669 Andrew Jeffery 2019-07-29 729 SIG_EXPR_LIST_PTR(pin, low), \
e7a96b0b7d1669 Andrew Jeffery 2019-07-29 730 SIG_EXPR_LIST_PTR(pin, other))
e7a96b0b7d1669 Andrew Jeffery 2019-07-29 731
0b9714845935ae Steven Lee 2021-05-25 732 #define PIN_DECL_4(pin, other, prio1, prio2, prio3, prio4) \
0b9714845935ae Steven Lee 2021-05-25 733 SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
0b9714845935ae Steven Lee 2021-05-25 734 PIN_DECL_(pin, \
0b9714845935ae Steven Lee 2021-05-25 735 SIG_EXPR_LIST_PTR(pin, prio1), \
0b9714845935ae Steven Lee 2021-05-25 736 SIG_EXPR_LIST_PTR(pin, prio2), \
0b9714845935ae Steven Lee 2021-05-25 737 SIG_EXPR_LIST_PTR(pin, prio3), \
0b9714845935ae Steven Lee 2021-05-25 738 SIG_EXPR_LIST_PTR(pin, prio4), \
0b9714845935ae Steven Lee 2021-05-25 739 SIG_EXPR_LIST_PTR(pin, other))
0b9714845935ae Steven Lee 2021-05-25 740
e7a96b0b7d1669 Andrew Jeffery 2019-07-29 @741 #define GROUP_SYM(group) group_pins_ ## group
e7a96b0b7d1669 Andrew Jeffery 2019-07-29 742 #define GROUP_DECL(group, ...) \
e7a96b0b7d1669 Andrew Jeffery 2019-07-29 743 static const int GROUP_SYM(group)[] = { __VA_ARGS__ }
e7a96b0b7d1669 Andrew Jeffery 2019-07-29 744
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 3/4] pinctrl: aspeed: Add AST2700 pinmux support
[not found] ` <20250904103401.88287-4-billy_tsai@aspeedtech.com>
2025-09-06 15:59 ` [PATCH v2 3/4] pinctrl: aspeed: Add AST2700 pinmux support kernel test robot
@ 2025-09-25 4:48 ` Andrew Jeffery
2025-11-11 2:24 ` Billy Tsai
1 sibling, 1 reply; 11+ messages in thread
From: Andrew Jeffery @ 2025-09-25 4:48 UTC (permalink / raw)
To: Billy Tsai, lee, robh, krzk+dt, conor+dt, joel, linus.walleij,
brgl, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
openbmc, linux-gpio, BMC-SW
Hi Billy,
On Thu, 2025-09-04 at 18:34 +0800, Billy Tsai wrote:
> This patch adds pinmux support for the AST2700, which includes two SoC
> configurations:
> - SoC0 closely resembles previous generations of ASPEED BMC SoCs, allowing
> the reuse of existing macros and callback functions.
> - SoC1, however, introduces a new logic for configuring pin functions.
> Therefore, new g7_set_mux and gpio_request_enable functions are
> implemented to properly configure the pinctrl registers using the
> pin_cfg table and to resolve GPIO request errors.
Do you mind splitting support for soc0 and soc1 into separate patches?
Having taken a brief look I think we're also due for some further
separation of the code. Particularly, isolating the patch for soc0
would be nice, as the register design for soc1 is just _so_ much nicer,
and I'd like to avoid dragging the baggage of previous generations
along with it.
>
> The driver supports:
> - All 12 GPIO-capable pins in SoC0
> - All 212 GPIO-capable pins in SoC1
>
> Additionally, this patch introduces several pseudo-ball definitions for
> specific configuration purposes:
> - USB function selection
> - JTAG target selection
> - PCIe RC PERST configuration
> - SGMII PHY selection
>
> Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
> ---
> drivers/pinctrl/aspeed/Kconfig | 8 +
> drivers/pinctrl/aspeed/Makefile | 1 +
> .../pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c | 503 ++++
> .../pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c | 2523 +++++++++++++++++
> drivers/pinctrl/aspeed/pinctrl-aspeed.c | 47 +
> drivers/pinctrl/aspeed/pinctrl-aspeed.h | 11 +-
> drivers/pinctrl/aspeed/pinmux-aspeed.h | 35 +-
The impression I get from the changes to the latter three files here is
that the soc0 support might even be different enough to warrant
separation from the previous generations as well. You're defining
similar-but-different structs and macros to what we already have. If
the those are genuinely necessary (not yet resolved), I'd rather they
be their own driver.
> 7 files changed, 3123 insertions(+), 5 deletions(-)
> create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c
> create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c
>
> diff --git a/drivers/pinctrl/aspeed/Kconfig b/drivers/pinctrl/aspeed/Kconfig
> index 1a4e5b9ed471..16743091a139 100644
> --- a/drivers/pinctrl/aspeed/Kconfig
> +++ b/drivers/pinctrl/aspeed/Kconfig
> @@ -31,3 +31,11 @@ config PINCTRL_ASPEED_G6
> help
> Say Y here to enable pin controller support for Aspeed's 6th
> generation SoCs. GPIO is provided by a separate GPIO driver.
> +
> +config PINCTRL_ASPEED_G7
> + bool "Aspeed G7 SoC pin control"
> + depends on (ARCH_ASPEED || COMPILE_TEST) && OF
> + select PINCTRL_ASPEED
> + help
> + Say Y here to enable pin controller support for Aspeed's 7th
> + generation SoCs. GPIO is provided by a separate GPIO driver.
> diff --git a/drivers/pinctrl/aspeed/Makefile b/drivers/pinctrl/aspeed/Makefile
> index db2a7600ae2b..1713f678a984 100644
> --- a/drivers/pinctrl/aspeed/Makefile
> +++ b/drivers/pinctrl/aspeed/Makefile
> @@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_ASPEED) += pinctrl-aspeed.o pinmux-aspeed.o
> obj-$(CONFIG_PINCTRL_ASPEED_G4) += pinctrl-aspeed-g4.o
> obj-$(CONFIG_PINCTRL_ASPEED_G5) += pinctrl-aspeed-g5.o
> obj-$(CONFIG_PINCTRL_ASPEED_G6) += pinctrl-aspeed-g6.o
> +obj-$(CONFIG_PINCTRL_ASPEED_G7) += pinctrl-aspeed-g7-soc0.o pinctrl-aspeed-g7-soc1.o
> \ No newline at end of file
> diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c
> new file mode 100644
> index 000000000000..86da889cc010
> --- /dev/null
> +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c
> @@ -0,0 +1,503 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#include <linux/bits.h>
> +#include <linux/device.h>
> +#include <linux/gpio/driver.h>
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/pinctrl/machine.h>
> +#include <linux/pinctrl/pinconf.h>
> +#include <linux/pinctrl/pinconf-generic.h>
> +#include <linux/pinctrl/pinctrl.h>
> +#include <linux/pinctrl/pinmux.h>
> +#include <linux/platform_device.h>
> +#include <linux/property.h>
> +#include <linux/regmap.h>
> +#include "pinctrl-aspeed.h"
> +#include "../pinctrl-utils.h"
> +
> +#define SCU200 0x200 /* System Reset Control #1 */
> +
> +#define SCU400 0x400 /* Multi-function Pin Control #1 */
> +#define SCU404 0x404 /* Multi-function Pin Control #2 */
> +#define SCU408 0x408 /* Multi-function Pin Control #3 */
> +#define SCU40C 0x40C /* Multi-function Pin Control #3 */
> +#define SCU410 0x410 /* USB Multi-function Control Register */
> +#define SCU414 0x414 /* VGA Function Control Register */
> +
> +#define SCU480 0x480 /* GPIO18A0 IO Control Register */
> +#define SCU484 0x484 /* GPIO18A1 IO Control Register */
> +#define SCU488 0x488 /* GPIO18A2 IO Control Register */
> +#define SCU48C 0x48c /* GPIO18A3 IO Control Register */
> +#define SCU490 0x490 /* GPIO18A4 IO Control Register */
> +#define SCU494 0x494 /* GPIO18A5 IO Control Register */
> +#define SCU498 0x498 /* GPIO18A6 IO Control Register */
> +#define SCU49C 0x49c /* GPIO18A7 IO Control Register */
> +#define SCU4A0 0x4A0 /* GPIO18B0 IO Control Register */
> +#define SCU4A4 0x4A4 /* GPIO18B1 IO Control Register */
> +#define SCU4A8 0x4A8 /* GPIO18B2 IO Control Register */
> +#define SCU4AC 0x4AC /* GPIO18B3 IO Control Register */
> +
> +enum {
> + AC14,
> + AE15,
Are the ball enums necessary? Historically we haven't needed it as the
undefined macro symbols were just used for token-pasting or
stringification purposes.
> + AD14,
> + AE14,
> + AF14,
> + AB13,
> + AB14,
> + AF15,
> + AF13,
> + AC13,
> + AD13,
> + AE13,
> + PORTA_U3, // SCU410[1:0]
> + PORTA_U2, // SCU410[3:2]
> + PORTB_U3, // SCU410[5:4]
> + PORTB_U2, // SCU410[7:6]
> + PORTA_U3_XHCI, // SCU410[9]
> + PORTA_U2_XHCI, // SCU410[9]
> + PORTB_U3_XHCI, // SCU410[10]
> + PORTB_U2_XHCI, // SCU410[10]
> + PORTA_MODE, // SCU410[25:24]
> + PORTB_MODE, // SCU410[29:28]
> + PORTA_U2_PHY,
> + PORTA_U3_PHY,
> + PORTB_U2_PHY,
> + PORTB_U3_PHY,
> + JTAG_PORT,
> + PCIERC0_PERST,
> + PCIERC1_PERST,
> +};
> +
> +GROUP_DECL(EMMCG1, AC14, AE15, AD14);
> +GROUP_DECL(EMMCG4, AC14, AE15, AD14, AE14, AF14, AB13);
> +GROUP_DECL(EMMCG8, AC14, AE15, AD14, AE14, AF14, AB13, AF13, AC13, AD13, AE13);
> +GROUP_DECL(EMMCWPN, AF15);
> +GROUP_DECL(EMMCCDN, AB14);
> +GROUP_DECL(VGADDC, AD13, AE13);
> +GROUP_DECL(VB1, AC14, AE15, AD14, AE14);
> +GROUP_DECL(VB0, AF15, AB14, AF13, AC13);
For the previous generation drivers my philosophy was "keep things that
go together together," so signal descriptors, groups and functions were
all located around the definition for one or a set of balls.
Given I'm potentially escaping maintenance of ASPEED pinctrl drivers
for the 2700 onwards I won't complain too much, but was this a specific
choice to break from that approach? You're defining all the groups,
then all the functions, then all the configurations.
*snip*
> diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c
> new file mode 100644
> index 000000000000..7c5a5e208f63
> --- /dev/null
> +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c
>
*snip*
> +
> +FUNCFG_DESCL(C16, PIN_CFG(ESPI1, SCU400, GENMASK(2, 0), 1),
> + PIN_CFG(LPC1, SCU400, GENMASK(2, 0), 2),
> + PIN_CFG(SD, SCU400, GENMASK(2, 0), 3),
> + PIN_CFG(DI2C0, SCU400, GENMASK(2, 0), 4),
> + PIN_CFG(VPI, SCU400, GENMASK(2, 0), 5));
> +FUNCFG_DESCL(C14, PIN_CFG(ESPI1, SCU400, GENMASK(6, 4), (1 << 4)),
> + PIN_CFG(LPC1, SCU400, GENMASK(6, 4), (2 << 4)),
> + PIN_CFG(SD, SCU400, GENMASK(6, 4), (3 << 4)),
> + PIN_CFG(DI2C1, SCU400, GENMASK(6, 4), (4 << 4)),
> + PIN_CFG(VPI, SCU400, GENMASK(6, 4), (5 << 4)));
> +FUNCFG_DESCL(C11, PIN_CFG(ESPI1, SCU400, GENMASK(10, 8), (1 << 8)),
> + PIN_CFG(LPC1, SCU400, GENMASK(10, 8), (2 << 8)),
> + PIN_CFG(SD, SCU400, GENMASK(10, 8), (3 << 8)),
> + PIN_CFG(DI2C3, SCU400, GENMASK(10, 8), (4 << 8)),
> + PIN_CFG(VPI, SCU400, GENMASK(10, 8), (5 << 8)));
If we're going to continue the macro soup we need to take the
opportunity to clean this up. You shouldn't need to open-code the
shifts like this, the data model needs more thought.
*snip*
> +
> +static const struct aspeed_g7_pincfg pin_cfg[] = {
> + PINCFG_PIN(C16), PINCFG_PIN(C14), PINCFG_PIN(C11),
> + PINCFG_PIN(D9), PINCFG_PIN(F14), PINCFG_PIN(D10),
My preference is that this array definition be one entry per line,
sorted, that way we don't get weird alignment or reflow affecting the
remainder of the struct if we change things in the middle.
Cheers,
Andrew
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 3/4] pinctrl: aspeed: Add AST2700 pinmux support
2025-09-25 4:48 ` Andrew Jeffery
@ 2025-11-11 2:24 ` Billy Tsai
0 siblings, 0 replies; 11+ messages in thread
From: Billy Tsai @ 2025-11-11 2:24 UTC (permalink / raw)
To: Andrew Jeffery, lee@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, joel@jms.id.au,
linus.walleij@linaro.org, brgl@bgdev.pl,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org,
openbmc@lists.ozlabs.org, linux-gpio@vger.kernel.org, BMC-SW
> > This patch adds pinmux support for the AST2700, which includes two SoC
> > configurations:
> > - SoC0 closely resembles previous generations of ASPEED BMC SoCs, allowing
> > the reuse of existing macros and callback functions.
> > - SoC1, however, introduces a new logic for configuring pin functions.
> > Therefore, new g7_set_mux and gpio_request_enable functions are
> > implemented to properly configure the pinctrl registers using the
> > pin_cfg table and to resolve GPIO request errors.
> Do you mind splitting support for soc0 and soc1 into separate patches?
> Having taken a brief look I think we're also due for some further
> separation of the code. Particularly, isolating the patch for soc0
> would be nice, as the register design for soc1 is just _so_ much nicer,
> and I'd like to avoid dragging the baggage of previous generations
> along with it.
Okay, I will split the support for SoC0 and SoC1 into separate patches.
SoC0 will follow the existing design closely, while SoC1 will introduce
a new logic for configuring pin functions.
> >
> > The driver supports:
> > - All 12 GPIO-capable pins in SoC0
> > - All 212 GPIO-capable pins in SoC1
> >
> > Additionally, this patch introduces several pseudo-ball definitions for
> > specific configuration purposes:
> > - USB function selection
> > - JTAG target selection
> > - PCIe RC PERST configuration
> > - SGMII PHY selection
> >
> > Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
> > ---
> > drivers/pinctrl/aspeed/Kconfig | 8 +
> > drivers/pinctrl/aspeed/Makefile | 1 +
> > .../pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c | 503 ++++
> > .../pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c | 2523 +++++++++++++++++
> > drivers/pinctrl/aspeed/pinctrl-aspeed.c | 47 +
> > drivers/pinctrl/aspeed/pinctrl-aspeed.h | 11 +-
> > drivers/pinctrl/aspeed/pinmux-aspeed.h | 35 +-
> The impression I get from the changes to the latter three files here is
> that the soc0 support might even be different enough to warrant
> separation from the previous generations as well. You're defining
> similar-but-different structs and macros to what we already have. If
> the those are genuinely necessary (not yet resolved), I'd rather they
> be their own driver.
Understood. I will modify the patch of the SoC0 to meet the concept with previous
generations. If the differences are significant, I will consider creating a
separate driver for it. But, at this moment, I believe the existing driver and macro can
be adapted to support SoC0 with minimal changes.
> > 7 files changed, 3123 insertions(+), 5 deletions(-)
> > create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c
> > create mode 100644 drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c
> >
> > diff --git a/drivers/pinctrl/aspeed/Kconfig b/drivers/pinctrl/aspeed/Kconfig
> > index 1a4e5b9ed471..16743091a139 100644
> > --- a/drivers/pinctrl/aspeed/Kconfig
> > +++ b/drivers/pinctrl/aspeed/Kconfig
> > @@ -31,3 +31,11 @@ config PINCTRL_ASPEED_G6
> > help
> > Say Y here to enable pin controller support for Aspeed's 6th
> > generation SoCs. GPIO is provided by a separate GPIO driver.
> > +
> > +config PINCTRL_ASPEED_G7
> > + bool "Aspeed G7 SoC pin control"
> > + depends on (ARCH_ASPEED || COMPILE_TEST) && OF
> > + select PINCTRL_ASPEED
> > + help
> > + Say Y here to enable pin controller support for Aspeed's 7th
> > + generation SoCs. GPIO is provided by a separate GPIO driver.
> > diff --git a/drivers/pinctrl/aspeed/Makefile b/drivers/pinctrl/aspeed/Makefile
> > index db2a7600ae2b..1713f678a984 100644
> > --- a/drivers/pinctrl/aspeed/Makefile
> > +++ b/drivers/pinctrl/aspeed/Makefile
> > @@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_ASPEED) += pinctrl-aspeed.o pinmux-aspeed.o
> > obj-$(CONFIG_PINCTRL_ASPEED_G4) += pinctrl-aspeed-g4.o
> > obj-$(CONFIG_PINCTRL_ASPEED_G5) += pinctrl-aspeed-g5.o
> > obj-$(CONFIG_PINCTRL_ASPEED_G6) += pinctrl-aspeed-g6.o
> > +obj-$(CONFIG_PINCTRL_ASPEED_G7) += pinctrl-aspeed-g7-soc0.o pinctrl-aspeed-g7-soc1.o
> > \ No newline at end of file
> > diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c
> > new file mode 100644
> > index 000000000000..86da889cc010
> > --- /dev/null
> > +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c
> > @@ -0,0 +1,503 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +
> > +#include <linux/bits.h>
> > +#include <linux/device.h>
> > +#include <linux/gpio/driver.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/irq.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/module.h>
> > +#include <linux/mod_devicetable.h>
> > +#include <linux/pinctrl/machine.h>
> > +#include <linux/pinctrl/pinconf.h>
> > +#include <linux/pinctrl/pinconf-generic.h>
> > +#include <linux/pinctrl/pinctrl.h>
> > +#include <linux/pinctrl/pinmux.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/property.h>
> > +#include <linux/regmap.h>
> > +#include "pinctrl-aspeed.h"
> > +#include "../pinctrl-utils.h"
> > +
> > +#define SCU200 0x200 /* System Reset Control #1 */
> > +
> > +#define SCU400 0x400 /* Multi-function Pin Control #1 */
> > +#define SCU404 0x404 /* Multi-function Pin Control #2 */
> > +#define SCU408 0x408 /* Multi-function Pin Control #3 */
> > +#define SCU40C 0x40C /* Multi-function Pin Control #3 */
> > +#define SCU410 0x410 /* USB Multi-function Control Register */
> > +#define SCU414 0x414 /* VGA Function Control Register */
> > +
> > +#define SCU480 0x480 /* GPIO18A0 IO Control Register */
> > +#define SCU484 0x484 /* GPIO18A1 IO Control Register */
> > +#define SCU488 0x488 /* GPIO18A2 IO Control Register */
> > +#define SCU48C 0x48c /* GPIO18A3 IO Control Register */
> > +#define SCU490 0x490 /* GPIO18A4 IO Control Register */
> > +#define SCU494 0x494 /* GPIO18A5 IO Control Register */
> > +#define SCU498 0x498 /* GPIO18A6 IO Control Register */
> > +#define SCU49C 0x49c /* GPIO18A7 IO Control Register */
> > +#define SCU4A0 0x4A0 /* GPIO18B0 IO Control Register */
> > +#define SCU4A4 0x4A4 /* GPIO18B1 IO Control Register */
> > +#define SCU4A8 0x4A8 /* GPIO18B2 IO Control Register */
> > +#define SCU4AC 0x4AC /* GPIO18B3 IO Control Register */
> > +
> > +enum {
> > + AC14,
> > + AE15,
> Are the ball enums necessary? Historically we haven't needed it as the
> undefined macro symbols were just used for token-pasting or
> stringification purposes.
The enums are used to replace the #define M24 0, #define M25 1, … definitions in
the G6 pinctrl driver. Additionally, the number assigned to each ball name must
follow the sequence of GPIO numbering. In other words, the number assigned to each
ball name is meaningful, and the order should not be changed. Therefore, I believe
that using enums is a better approach than using #define macros.
> > + AD14,
> > + AE14,
> > + AF14,
> > + AB13,
> > + AB14,
> > + AF15,
> > + AF13,
> > + AC13,
> > + AD13,
> > + AE13,
> > + PORTA_U3, // SCU410[1:0]
> > + PORTA_U2, // SCU410[3:2]
> > + PORTB_U3, // SCU410[5:4]
> > + PORTB_U2, // SCU410[7:6]
> > + PORTA_U3_XHCI, // SCU410[9]
> > + PORTA_U2_XHCI, // SCU410[9]
> > + PORTB_U3_XHCI, // SCU410[10]
> > + PORTB_U2_XHCI, // SCU410[10]
> > + PORTA_MODE, // SCU410[25:24]
> > + PORTB_MODE, // SCU410[29:28]
> > + PORTA_U2_PHY,
> > + PORTA_U3_PHY,
> > + PORTB_U2_PHY,
> > + PORTB_U3_PHY,
> > + JTAG_PORT,
> > + PCIERC0_PERST,
> > + PCIERC1_PERST,
> > +};
> > +
> > +GROUP_DECL(EMMCG1, AC14, AE15, AD14);
> > +GROUP_DECL(EMMCG4, AC14, AE15, AD14, AE14, AF14, AB13);
> > +GROUP_DECL(EMMCG8, AC14, AE15, AD14, AE14, AF14, AB13, AF13, AC13, AD13, AE13);
> > +GROUP_DECL(EMMCWPN, AF15);
> > +GROUP_DECL(EMMCCDN, AB14);
> > +GROUP_DECL(VGADDC, AD13, AE13);
> > +GROUP_DECL(VB1, AC14, AE15, AD14, AE14);
> > +GROUP_DECL(VB0, AF15, AB14, AF13, AC13);
> For the previous generation drivers my philosophy was "keep things that
> go together together," so signal descriptors, groups and functions were
> all located around the definition for one or a set of balls.
> Given I'm potentially escaping maintenance of ASPEED pinctrl drivers
> for the 2700 onwards I won't complain too much, but was this a specific
> choice to break from that approach? You're defining all the groups,
> then all the functions, then all the configurations.
The groups and the functions can be put together, but the ball define
as the above reasons. So, I will keep the ball defines at the top with the enums.
> > diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c
> > new file mode 100644
> > index 000000000000..7c5a5e208f63
> > --- /dev/null
> > +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c
> >
> *snip*
> > +
> > +FUNCFG_DESCL(C16, PIN_CFG(ESPI1, SCU400, GENMASK(2, 0), 1),
> > + PIN_CFG(LPC1, SCU400, GENMASK(2, 0), 2),
> > + PIN_CFG(SD, SCU400, GENMASK(2, 0), 3),
> > + PIN_CFG(DI2C0, SCU400, GENMASK(2, 0), 4),
> > + PIN_CFG(VPI, SCU400, GENMASK(2, 0), 5));
> > +FUNCFG_DESCL(C14, PIN_CFG(ESPI1, SCU400, GENMASK(6, 4), (1 << 4)),
> > + PIN_CFG(LPC1, SCU400, GENMASK(6, 4), (2 << 4)),
> > + PIN_CFG(SD, SCU400, GENMASK(6, 4), (3 << 4)),
> > + PIN_CFG(DI2C1, SCU400, GENMASK(6, 4), (4 << 4)),
> > + PIN_CFG(VPI, SCU400, GENMASK(6, 4), (5 << 4)));
> > +FUNCFG_DESCL(C11, PIN_CFG(ESPI1, SCU400, GENMASK(10, 8), (1 << 8)),
> > + PIN_CFG(LPC1, SCU400, GENMASK(10, 8), (2 << 8)),
> > + PIN_CFG(SD, SCU400, GENMASK(10, 8), (3 << 8)),
> > + PIN_CFG(DI2C3, SCU400, GENMASK(10, 8), (4 << 8)),
> > + PIN_CFG(VPI, SCU400, GENMASK(10, 8), (5 << 8)));
> If we're going to continue the macro soup we need to take the
> opportunity to clean this up. You shouldn't need to open-code the
> shifts like this, the data model needs more thought.
Got it. I will improve the macros to avoid open-coding shifts.
> > +
> > +static const struct aspeed_g7_pincfg pin_cfg[] = {
> > + PINCFG_PIN(C16), PINCFG_PIN(C14), PINCFG_PIN(C11),
> > + PINCFG_PIN(D9), PINCFG_PIN(F14), PINCFG_PIN(D10),
> My preference is that this array definition be one entry per line,
> sorted, that way we don't get weird alignment or reflow affecting the
> remainder of the struct if we change things in the middle.
Okay, I will format the array definition to have one entry per line and sorted.
Thanks
Best regards,
Billy Tsai
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2025-11-11 2:24 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-09-04 10:33 [PATCH v2 0/4] Add pinctrl support for AST2700 SoC Billy Tsai
2025-09-04 10:33 ` [PATCH v2 1/4] dt-bindings: mfd: aspeed,ast2x00-scu: Support ast2700 pinctrl Billy Tsai
2025-09-05 8:13 ` Krzysztof Kozlowski
2025-09-04 10:33 ` [PATCH v2 2/4] dt-bindings: pinctrl: aspeed: Add support for AST27xx Billy Tsai
2025-09-05 8:16 ` Krzysztof Kozlowski
2025-09-04 10:34 ` [PATCH v2 4/4] arm64: dts: add AST27xx pinctrl configuration nodes Billy Tsai
2025-09-04 14:26 ` Rob Herring
2025-09-05 8:12 ` [PATCH v2 0/4] Add pinctrl support for AST2700 SoC Krzysztof Kozlowski
[not found] ` <20250904103401.88287-4-billy_tsai@aspeedtech.com>
2025-09-06 15:59 ` [PATCH v2 3/4] pinctrl: aspeed: Add AST2700 pinmux support kernel test robot
2025-09-25 4:48 ` Andrew Jeffery
2025-11-11 2:24 ` Billy Tsai
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