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Wed, 8 Jul 2026 16:10:22 +0800 (CST) Received: from kwepemq500001.china.huawei.com (7.202.195.224) by dggemv705-chm.china.huawei.com (10.3.19.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 8 Jul 2026 16:10:20 +0800 Received: from [10.67.146.137] (10.67.146.137) by kwepemq500001.china.huawei.com (7.202.195.224) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 8 Jul 2026 16:10:19 +0800 Subject: Re: Question about the "TLBs and I-cache are private to each vCPU" guarantee with VTTBR_EL2.CnP To: Oliver Upton CC: Mark Rutland , Marc Zyngier , Wei-Lin Chang , , , , , , , , , , "guoyang (C)" , "huanglingyan (A)" , "Wangzhou (B)" References: <292b5734-9005-6db0-da08-3da04628e620@huawei.com> <86o6gkpokm.wl-maz@kernel.org> <21eb51aa-443c-4d08-b4dd-3f813bbc9880@huawei.com> <86jyr8pkw8.wl-maz@kernel.org> <5685cdb9-95d8-9ead-4d24-d6ad06dd9547@huawei.com> <7d97b19a-ef56-dea1-cd99-056e0e34a7fa@huawei.com> From: Tangnianyao Message-ID: <007d69fe-9554-b9c1-dd89-23856d78571b@huawei.com> Date: Wed, 8 Jul 2026 16:10:18 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Language: en-US X-Originating-IP: [10.67.146.137] X-ClientProxiedBy: kwepems500001.china.huawei.com (7.221.188.70) To kwepemq500001.china.huawei.com (7.202.195.224) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260708_011237_377575_BF5186D9 X-CRM114-Status: GOOD ( 18.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 7/7/2026 14:36, Oliver Upton wrote: > On Tue, Jul 07, 2026 at 10:41:35AM +0800, Tangnianyao wrote: >> On 7/6/2026 23:33, Mark Rutland wrote: >>> If *both* of the vCPUs set TTBRn_EL1.CnP, then surely that is >>> indistinguishable from physical CPUs: >>> >>> PE0(core0,smt0) PE1(core0,smt1) >>> cpu0 va->pa0 >>> cpu1 flush local tlb >>> cpu1 modify desc to va->pa1 >>> cpu0 hit *va->pa1* >>> >>> Mark. >>> >>> . >>> >> Thanks for the clarification. >> Stage-1 CnP determines whether Stage-1 translation entries may be shared >> across vCPUs, and the hardware is responsible for enforcing the >> architectural semantics. >> >> Given that, why does KVM still need to guarantee that TLBs are private to >> each vCPU? >> >> Assuming VTTBR_EL2.CnP == 1: >> If TTBRx_EL1.CnP == 1, the guest is responsible for ensuring that the >> translations referenced by TTBRx_EL1 are shareable, as required by the >> architecture. >> If TTBRx_EL1.CnP == 0, the hardware must ensure that Stage-1 translations >> are not shared, again according to the architectural definition. >> >> The reason I'm asking is the potential performance impact. In a scenario >> where multiple vCPUs of the same VM are scheduled onto a single PE, this >> TLB flush may prevent a vCPU from reusing its previously populated >> translation entries, potentially increasing TLB misses. > The problem is you can't infer the state of the TLB based on the current > value of CnP at stage-1. CnP only applies to the current TTBR; > nothing stops the guest from using a mix of CnP=0/1 for different TTBRs. > > KVM still needs to invalidate in the case that the PE retained a CnP=0 > TLB entry for a different stage-1 context than the one configured at > the time of vcpu_load(). > > Thanks, > Oliver > . > Thanks for the explanation. When the guest uses `Stage-1 CnP = 0`, kvm does need the flush to maintain the "private to each vCPU" guarantee. Thanks, Nianyao Tang