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The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --8323328-1307680798-1720456008=:1343 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE On Mon, 8 Jul 2024, Marek Beh=C3=BAn wrote: > Some register constants have the _OFFS suffix and some do not. Drop it > to be more consistent. >=20 > Signed-off-by: Marek Beh=C3=BAn Reviewed-by: Ilpo J=C3=A4rvinen --=20 i. > --- > drivers/irqchip/irq-armada-370-xp.c | 105 +++++++++++++--------------- > 1 file changed, 48 insertions(+), 57 deletions(-) >=20 > diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-ar= mada-370-xp.c > index dce2b80bf439..66d6a2ebc8a5 100644 > --- a/drivers/irqchip/irq-armada-370-xp.c > +++ b/drivers/irqchip/irq-armada-370-xp.c > @@ -66,15 +66,14 @@ > * device > * > * The "global interrupt mask/unmask" is modified using the > - * ARMADA_370_XP_INT_SET_ENABLE_OFFS and > - * ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS registers, which are relative > - * to "main_int_base". > + * ARMADA_370_XP_INT_SET_ENABLE and ARMADA_370_XP_INT_CLEAR_ENABLE > + * registers, which are relative to "main_int_base". > * > * The "per-CPU mask/unmask" is modified using the > - * ARMADA_370_XP_INT_SET_MASK_OFFS and > - * ARMADA_370_XP_INT_CLEAR_MASK_OFFS registers, which are relative to > - * "per_cpu_int_base". This base address points to a special address, > - * which automatically accesses the registers of the current CPU. > + * ARMADA_370_XP_INT_SET_MASK and ARMADA_370_XP_INT_CLEAR_MASK > + * registers, which are relative to "per_cpu_int_base". This base > + * address points to a special address, which automatically accesses > + * the registers of the current CPU. > * > * The per-CPU mask/unmask can also be adjusted using the global > * per-interrupt ARMADA_370_XP_INT_SOURCE_CTL register, which we use > @@ -118,21 +117,21 @@ > =20 > /* Registers relative to main_int_base */ > #define ARMADA_370_XP_INT_CONTROL=09=09(0x00) > -#define ARMADA_370_XP_SW_TRIG_INT_OFFS=09=09(0x04) > -#define ARMADA_370_XP_INT_SET_ENABLE_OFFS=09(0x30) > -#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS=09(0x34) > +#define ARMADA_370_XP_SW_TRIG_INT=09=09(0x04) > +#define ARMADA_370_XP_INT_SET_ENABLE=09=09(0x30) > +#define ARMADA_370_XP_INT_CLEAR_ENABLE=09=09(0x34) > #define ARMADA_370_XP_INT_SOURCE_CTL(irq)=09(0x100 + irq*4) > #define ARMADA_370_XP_INT_SOURCE_CPU_MASK=090xF > #define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)=09((BIT(0) | BIT(8)) << cp= uid) > =20 > /* Registers relative to per_cpu_int_base */ > -#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS=09(0x08) > -#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS=09=09(0x0c) > +#define ARMADA_370_XP_IN_DRBEL_CAUSE=09=09(0x08) > +#define ARMADA_370_XP_IN_DRBEL_MSK=09=09(0x0c) > #define ARMADA_375_PPI_CAUSE=09=09=09(0x10) > -#define ARMADA_370_XP_CPU_INTACK_OFFS=09=09(0x44) > -#define ARMADA_370_XP_INT_SET_MASK_OFFS=09=09(0x48) > -#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS=09(0x4C) > -#define ARMADA_370_XP_INT_FABRIC_MASK_OFFS=09(0x54) > +#define ARMADA_370_XP_CPU_INTACK=09=09(0x44) > +#define ARMADA_370_XP_INT_SET_MASK=09=09(0x48) > +#define ARMADA_370_XP_INT_CLEAR_MASK=09=09(0x4C) > +#define ARMADA_370_XP_INT_FABRIC_MASK=09=09(0x54) > #define ARMADA_370_XP_INT_CAUSE_PERF(cpu)=09(1 << cpu) > =20 > #define ARMADA_370_XP_MAX_PER_CPU_IRQS=09=09(28) > @@ -220,11 +219,9 @@ static void armada_370_xp_irq_mask(struct irq_data *= d) > =09irq_hw_number_t hwirq =3D irqd_to_hwirq(d); > =20 > =09if (!is_percpu_irq(hwirq)) > -=09=09writel(hwirq, main_int_base + > -=09=09=09=09ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS); > +=09=09writel(hwirq, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE); > =09else > -=09=09writel(hwirq, per_cpu_int_base + > -=09=09=09=09ARMADA_370_XP_INT_SET_MASK_OFFS); > +=09=09writel(hwirq, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK); > } > =20 > static void armada_370_xp_irq_unmask(struct irq_data *d) > @@ -232,11 +229,9 @@ static void armada_370_xp_irq_unmask(struct irq_data= *d) > =09irq_hw_number_t hwirq =3D irqd_to_hwirq(d); > =20 > =09if (!is_percpu_irq(hwirq)) > -=09=09writel(hwirq, main_int_base + > -=09=09=09=09ARMADA_370_XP_INT_SET_ENABLE_OFFS); > +=09=09writel(hwirq, main_int_base + ARMADA_370_XP_INT_SET_ENABLE); > =09else > -=09=09writel(hwirq, per_cpu_int_base + > -=09=09=09=09ARMADA_370_XP_INT_CLEAR_MASK_OFFS); > +=09=09writel(hwirq, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK); > } > =20 > #ifdef CONFIG_PCI_MSI > @@ -329,19 +324,18 @@ static void armada_370_xp_msi_reenable_percpu(void) > =09u32 reg; > =20 > =09/* Enable MSI doorbell mask and combined cpu local interrupt */ > -=09reg =3D readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); > +=09reg =3D readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK); > =09reg |=3D msi_doorbell_mask(); > -=09writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); > +=09writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK); > =20 > =09/* Unmask local doorbell interrupt */ > -=09writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); > +=09writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK); > } > =20 > static int armada_370_xp_msi_init(struct device_node *node, > =09=09=09=09 phys_addr_t main_int_phys_base) > { > -=09msi_doorbell_addr =3D main_int_phys_base + > -=09=09ARMADA_370_XP_SW_TRIG_INT_OFFS; > +=09msi_doorbell_addr =3D main_int_phys_base + ARMADA_370_XP_SW_TRIG_INT; > =20 > =09armada_370_xp_msi_inner_domain =3D > =09=09irq_domain_add_linear(NULL, msi_doorbell_size(), > @@ -362,7 +356,7 @@ static int armada_370_xp_msi_init(struct device_node = *node, > =20 > =09/* Unmask low 16 MSI irqs on non-IPI platforms */ > =09if (!is_ipi_available()) > -=09=09writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); > +=09=09writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK); > =20 > =09return 0; > } > @@ -391,7 +385,7 @@ static void armada_xp_mpic_perf_init(void) > =20 > =09/* Enable Performance Counter Overflow interrupts */ > =09writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid), > -=09 per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS); > +=09 per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK); > } > =20 > #ifdef CONFIG_SMP > @@ -400,17 +394,17 @@ static struct irq_domain *ipi_domain; > static void armada_370_xp_ipi_mask(struct irq_data *d) > { > =09u32 reg; > -=09reg =3D readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); > +=09reg =3D readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK); > =09reg &=3D ~BIT(d->hwirq); > -=09writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); > +=09writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK); > } > =20 > static void armada_370_xp_ipi_unmask(struct irq_data *d) > { > =09u32 reg; > -=09reg =3D readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); > +=09reg =3D readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK); > =09reg |=3D BIT(d->hwirq); > -=09writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); > +=09writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK); > } > =20 > static void armada_370_xp_ipi_send_mask(struct irq_data *d, > @@ -431,12 +425,12 @@ static void armada_370_xp_ipi_send_mask(struct irq_= data *d, > =20 > =09/* submit softirq */ > =09writel((map << 8) | d->hwirq, main_int_base + > -=09=09ARMADA_370_XP_SW_TRIG_INT_OFFS); > +=09=09ARMADA_370_XP_SW_TRIG_INT); > } > =20 > static void armada_370_xp_ipi_ack(struct irq_data *d) > { > -=09writel(~BIT(d->hwirq), per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUS= E_OFFS); > +=09writel(~BIT(d->hwirq), per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUS= E); > } > =20 > static struct irq_chip ipi_irqchip =3D { > @@ -539,19 +533,19 @@ static void armada_xp_mpic_smp_cpu_init(void) > =09nr_irqs =3D (control >> 2) & 0x3ff; > =20 > =09for (i =3D 0; i < nr_irqs; i++) > -=09=09writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS); > +=09=09writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK); > =20 > =09if (!is_ipi_available()) > =09=09return; > =20 > =09/* Disable all IPIs */ > -=09writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); > +=09writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK); > =20 > =09/* Clear pending IPIs */ > -=09writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); > +=09writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE); > =20 > =09/* Unmask IPI interrupt */ > -=09writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); > +=09writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK); > } > =20 > static void armada_xp_mpic_reenable_percpu(void) > @@ -622,9 +616,9 @@ static int armada_370_xp_mpic_irq_map(struct irq_doma= in *h, > =09armada_370_xp_irq_mask(irq_get_irq_data(virq)); > =09if (!is_percpu_irq(hw)) > =09=09writel(hw, per_cpu_int_base + > -=09=09=09ARMADA_370_XP_INT_CLEAR_MASK_OFFS); > +=09=09=09ARMADA_370_XP_INT_CLEAR_MASK); > =09else > -=09=09writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); > +=09=09writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE); > =09irq_set_status_flags(virq, IRQ_LEVEL); > =20 > =09if (is_percpu_irq(hw)) { > @@ -651,12 +645,10 @@ static void armada_370_xp_handle_msi_irq(struct pt_= regs *regs, bool is_chained) > { > =09u32 msimask, msinr; > =20 > -=09msimask =3D readl_relaxed(per_cpu_int_base + > -=09=09=09=09ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); > +=09msimask =3D readl_relaxed(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_C= AUSE); > =09msimask &=3D msi_doorbell_mask(); > =20 > -=09writel(~msimask, per_cpu_int_base + > -=09 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); > +=09writel(~msimask, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE); > =20 > =09for (msinr =3D msi_doorbell_start(); > =09 msinr < msi_doorbell_end(); msinr++) { > @@ -712,7 +704,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs) > =20 > =09do { > =09=09irqstat =3D readl_relaxed(per_cpu_int_base + > -=09=09=09=09=09ARMADA_370_XP_CPU_INTACK_OFFS); > +=09=09=09=09=09ARMADA_370_XP_CPU_INTACK); > =09=09irqnr =3D irqstat & 0x3FF; > =20 > =09=09if (irqnr > 1022) > @@ -735,7 +727,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs) > =09=09=09int ipi; > =20 > =09=09=09ipimask =3D readl_relaxed(per_cpu_int_base + > -=09=09=09=09=09=09ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS) > +=09=09=09=09=09=09ARMADA_370_XP_IN_DRBEL_CAUSE) > =09=09=09=09& IPI_DOORBELL_MASK; > =20 > =09=09=09for_each_set_bit(ipi, &ipimask, IPI_DOORBELL_END) > @@ -748,8 +740,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs) > =20 > static int armada_370_xp_mpic_suspend(void) > { > -=09doorbell_mask_reg =3D readl(per_cpu_int_base + > -=09=09=09=09 ARMADA_370_XP_IN_DRBEL_MSK_OFFS); > +=09doorbell_mask_reg =3D readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL= _MSK); > =09return 0; > } > =20 > @@ -774,13 +765,13 @@ static void armada_370_xp_mpic_resume(void) > =09=09if (!is_percpu_irq(irq)) { > =09=09=09/* Non per-CPU interrupts */ > =09=09=09writel(irq, per_cpu_int_base + > -=09=09=09 ARMADA_370_XP_INT_CLEAR_MASK_OFFS); > +=09=09=09 ARMADA_370_XP_INT_CLEAR_MASK); > =09=09=09if (!irqd_irq_disabled(data)) > =09=09=09=09armada_370_xp_irq_unmask(data); > =09=09} else { > =09=09=09/* Per-CPU interrupts */ > =09=09=09writel(irq, main_int_base + > -=09=09=09 ARMADA_370_XP_INT_SET_ENABLE_OFFS); > +=09=09=09 ARMADA_370_XP_INT_SET_ENABLE); > =20 > =09=09=09/* > =09=09=09 * Re-enable on the current CPU, > @@ -794,7 +785,7 @@ static void armada_370_xp_mpic_resume(void) > =20 > =09/* Reconfigure doorbells for IPIs and MSIs */ > =09writel(doorbell_mask_reg, > -=09 per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); > +=09 per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK); > =20 > =09if (is_ipi_available()) { > =09=09src0 =3D doorbell_mask_reg & IPI_DOORBELL_MASK; > @@ -805,9 +796,9 @@ static void armada_370_xp_mpic_resume(void) > =09} > =20 > =09if (src0) > -=09=09writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); > +=09=09writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK); > =09if (src1) > -=09=09writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); > +=09=09writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK); > =20 > =09if (is_ipi_available()) > =09=09ipi_resume(); > @@ -847,7 +838,7 @@ static int __init armada_370_xp_mpic_of_init(struct d= evice_node *node, > =09nr_irqs =3D (control >> 2) & 0x3ff; > =20 > =09for (i =3D 0; i < nr_irqs; i++) > -=09=09writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS); > +=09=09writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE); > =20 > =09armada_370_xp_mpic_domain =3D > =09=09irq_domain_add_linear(node, nr_irqs, >=20 --8323328-1307680798-1720456008=:1343--