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The phyCORE-AM62Px SoM > uses the TI AM62Px SoC and can come with different sizes and models of > DDR, eMMC, and SPI NOR Flash. > > Supported features: > * Audio playback and recording > * CAN > * Debug UART > * eMMC > * Ethernet > * GPIO buttons > * Heartbeat LED > * I2C EEPROM > * I2C RTC > * Micro SD card > * SPI NOR flash > * SPI Accelerometer > * USB > > [1] https://www.phytec.com/product/phycore-am62px/ > [2] https://www.phytec.com/product/phyboard-am62px-development-kit/ > > Test results: > https://gist.github.com/jma-phytec/fd7911a834e39b3fac0104690668882e > > Signed-off-by: John Ma > --- > v2: > - added bootph-all in cpsw3g_phy1 node > - fixed ti,fifo-depth property deprecated issue > - update ospi vcc-supply label from SoM > - added bootph-all in wkup_i2c0 node > - sorted nodes in alphabetical order > - sorted vendor property > - removed unsed leds from phyboard lynx dts > - added chosen/stdout-path > - update usb0_connector node with proper name > - fixed missing space > - removed unused pinmux > - removed bootph-all from rgmii2 pinmux > - added interrupt-names for adxl345 node > - sorted status property in main_uart1 > > arch/arm64/boot/dts/ti/Makefile | 1 + > .../boot/dts/ti/k3-am62p-phycore-som.dtsi | 340 ++++++++++++ > .../boot/dts/ti/k3-am62p5-phyboard-lynx.dts | 522 ++++++++++++++++++ > 3 files changed, 863 insertions(+) > create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-phycore-som.dtsi > create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-phyboard-lynx.dts > > diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile > index 371f9a043fe5..b223681cdfbf 100644 > --- a/arch/arm64/boot/dts/ti/Makefile > +++ b/arch/arm64/boot/dts/ti/Makefile > @@ -76,6 +76,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62d2-evm.dtb > dtb-$(CONFIG_ARCH_K3) += k3-am62l3-evm.dtb > > # Boards with AM62Px SoC > +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-phyboard-lynx.dtb > dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb > dtb-$(CONFIG_ARCH_K3) += k3-am62p5-var-som-symphony.dtb > dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-dahlia.dtb > diff --git a/arch/arm64/boot/dts/ti/k3-am62p-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-phycore-som.dtsi > new file mode 100644 > index 000000000000..4f273f3dc2ad > --- /dev/null > +++ b/arch/arm64/boot/dts/ti/k3-am62p-phycore-som.dtsi > @@ -0,0 +1,340 @@ > +// SPDX-License-Identifier: GPL-2.0-only OR MIT > +/* > + * Copyright (C) 2026 PHYTEC America LLC > + * Author: John Ma > + * > + */ > + > +#include > +#include > +#include > + > +/ { > + model = "PHYTEC phyCORE-AM62P5"; > + compatible = "phytec,am62p-phycore-som", "ti,am62p5"; > + > + aliases { > + ethernet0 = &cpsw_port1; > + gpio0 = &main_gpio0; > + gpio1 = &main_gpio1; > + i2c0 = &wkup_i2c0; > + mmc0 = &sdhci0; > + rtc0 = &i2c_som_rtc; > + rtc1 = &wkup_rtc0; > + spi0 = &ospi0; > + }; > + > + memory@80000000 { > + /* 2G RAM */ > + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; > + device_type = "memory"; > + bootph-all; > + }; > + > + reserved_memory: reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { > + compatible = "shared-dma-pool"; > + reg = <0x00 0x9c800000 0x00 0x100000>; > + no-map; > + }; > + > + wkup_r5fss0_core0_memory_region: memory@9c900000 { > + compatible = "shared-dma-pool"; > + reg = <0x00 0x9c900000 0x00 0x1e00000>; > + no-map; > + }; > + > + secure_tfa_ddr: tfa@9e780000 { > + reg = <0x00 0x9e780000 0x00 0x80000>; > + no-map; > + }; > + > + secure_ddr: optee@9e800000 { > + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ > + no-map; > + }; > + }; > + > + vcc_5v0_som: regulator-vcc-5v0-som { > + compatible = "regulator-fixed"; > + regulator-name = "VCC_5V0_SOM"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + regulator-always-on; > + regulator-boot-on; > + }; > + > + leds { > + compatible = "gpio-leds"; > + pinctrl-names = "default"; > + pinctrl-0 = <&leds_pins_default>; > + > + led-0 { > + color = ; > + gpios = <&main_gpio0 13 GPIO_ACTIVE_HIGH>; > + linux,default-trigger = "heartbeat"; > + function = LED_FUNCTION_HEARTBEAT; > + }; > + }; > + > + opp-table { > + /* Requires VDD_CORE at 0v85 */ > + opp-1400000000 { > + opp-hz = /bits/ 64 <1400000000>; > + opp-supported-hw = <0x01 0x0004>; > + clock-latency-ns = <6000000>; > + }; > + }; > +}; > + > +&main_pmx0 { > + leds_pins_default: leds-default-pins { > + pinctrl-single,pins = < > + AM62PX_IOPAD(0x0034, PIN_OUTPUT, 7) /* (L22) OSPI0_CSn2.GPIO0_13 */ > + >; > + }; > + > + main_mdio0_pins_default: main-mdio0-default-pins { > + pinctrl-single,pins = < > + AM62PX_IOPAD(0x0160, PIN_OUTPUT_PULLUP, 0) /* (F17) MDIO0_MDC */ > + AM62PX_IOPAD(0x015c, PIN_INPUT_PULLUP, 0) /* (F16) MDIO0_MDIO */ > + >; > + bootph-all; > + }; > + > + main_rgmii1_pins_default: main-rgmii1-default-pins { > + pinctrl-single,pins = < > + AM62PX_IOPAD(0x014c, PIN_INPUT, 0) /* (B15) RGMII1_RD0 */ > + AM62PX_IOPAD(0x0150, PIN_INPUT, 0) /* (B16) RGMII1_RD1 */ > + AM62PX_IOPAD(0x0154, PIN_INPUT, 0) /* (A14) RGMII1_RD2 */ > + AM62PX_IOPAD(0x0158, PIN_INPUT, 0) /* (B14) RGMII1_RD3 */ > + AM62PX_IOPAD(0x0148, PIN_INPUT, 0) /* (A16) RGMII1_RXC */ > + AM62PX_IOPAD(0x0144, PIN_INPUT, 0) /* (A15) RGMII1_RX_CTL */ > + AM62PX_IOPAD(0x0134, PIN_INPUT, 0) /* (A18) RGMII1_TD0 */ > + AM62PX_IOPAD(0x0138, PIN_INPUT, 0) /* (C17) RGMII1_TD1 */ > + AM62PX_IOPAD(0x013c, PIN_INPUT, 0) /* (A17) RGMII1_TD2 */ > + AM62PX_IOPAD(0x0140, PIN_INPUT, 0) /* (C16) RGMII1_TD3 */ > + AM62PX_IOPAD(0x0130, PIN_INPUT, 0) /* (B17) RGMII1_TXC */ > + AM62PX_IOPAD(0x012c, PIN_INPUT, 0) /* (B18) RGMII1_TX_CTL */ > + >; > + bootph-all; > + }; > + > + ospi0_pins_default: ospi0-default-pins { > + pinctrl-single,pins = < > + AM62PX_IOPAD(0x0000, PIN_OUTPUT, 0) /* (P23) OSPI0_CLK */ > + AM62PX_IOPAD(0x002c, PIN_OUTPUT, 0) /* (M25) OSPI0_CSn0 */ > + AM62PX_IOPAD(0x000c, PIN_INPUT, 0) /* (L25) OSPI0_D0 */ > + AM62PX_IOPAD(0x0010, PIN_INPUT, 0) /* (N24) OSPI0_D1 */ > + AM62PX_IOPAD(0x0014, PIN_INPUT, 0) /* (N25) OSPI0_D2 */ > + AM62PX_IOPAD(0x0018, PIN_INPUT, 0) /* (M24) OSPI0_D3 */ > + AM62PX_IOPAD(0x001c, PIN_INPUT, 0) /* (N21) OSPI0_D4 */ > + AM62PX_IOPAD(0x0020, PIN_INPUT, 0) /* (N22) OSPI0_D5 */ > + AM62PX_IOPAD(0x0024, PIN_INPUT, 0) /* (P21) OSPI0_D6 */ > + AM62PX_IOPAD(0x0028, PIN_INPUT, 0) /* (N20) OSPI0_D7 */ > + AM62PX_IOPAD(0x0008, PIN_INPUT, 0) /* (P22) OSPI0_DQS */ > + >; > + bootph-all; > + }; > + > + pmic_irq_pins_default: pmic-irq-default-pins { > + pinctrl-single,pins = < ^ I think you use spaces here instead of tabs > + AM62PX_IOPAD(0x01f4, PIN_INPUT, 7) /* (C23) EXTINTn.GPIO1_31 */ Use the dedicated EXTINTn, mux 0 here. > + >; and here as well. > + }; > +}; > + > +&mcu_pmx0 { > + wkup_i2c0_pins_default: wkup-i2c0-default-pins { > + pinctrl-single,pins = < > + AM62PX_MCU_IOPAD(0x04c, PIN_INPUT_PULLUP, 0) /* (A13) WKUP_I2C0_SCL */ > + AM62PX_MCU_IOPAD(0x050, PIN_INPUT_PULLUP, 0) /* (C11) WKUP_I2C0_SDA */ > + >; > + bootph-all; > + }; > +}; > + > +&cpsw3g { > + pinctrl-names = "default"; > + pinctrl-0 = <&main_rgmii1_pins_default>; > + bootph-all; > + status = "okay"; > +}; > + > +&cpsw3g_mdio { > + pinctrl-names = "default"; > + pinctrl-0 = <&main_mdio0_pins_default>; > + status = "okay"; > + > + cpsw3g_phy1: ethernet-phy@1 { > + reg = <1>; > + bootph-all; > + tx-fifo-depth = ; > + ti,min-output-impedance; > + ti,rx-internal-delay = ; > + }; > +}; > + > +&cpsw_port1 { > + phy-mode = "rgmii-id"; > + phy-handle = <&cpsw3g_phy1>; > + bootph-all; > + status = "okay"; > +}; > + > +&fss { > + bootph-all; > +}; > + > +&ospi0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&ospi0_pins_default>; > + status = "okay"; > + > + serial_flash: flash@0 { > + compatible = "jedec,spi-nor"; > + reg = <0x0>; > + spi-tx-bus-width = <8>; > + spi-rx-bus-width = <8>; > + spi-max-frequency = <25000000>; > + vcc-supply = <&vdd_1v8_som>; > + cdns,tshsl-ns = <60>; > + cdns,tsd2d-ns = <60>; > + cdns,tchsh-ns = <60>; > + cdns,tslch-ns = <60>; > + cdns,read-delay = <0>; > + bootph-all; > + }; > +}; > + > +&sdhci0 { > + non-removable; > + bootph-all; > + ti,driver-strength-ohm = <50>; > + status = "okay"; > +}; > + > +&wkup_i2c0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&wkup_i2c0_pins_default>; > + clock-frequency = <400000>; > + bootph-all; > + status = "okay"; > + > + pmic@30 { > + compatible = "ti,tps65219"; > + reg = <0x30>; > + buck1-supply = <&vcc_5v0_som>; > + buck2-supply = <&vcc_5v0_som>; > + buck3-supply = <&vcc_5v0_som>; > + ldo1-supply = <&vdd_3v3_som>; > + ldo2-supply = <&vdd_1v8_som>; > + ldo3-supply = <&vdd_3v3_som>; > + ldo4-supply = <&vdd_3v3_som>; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&pmic_irq_pins_default>; > + interrupt-parent = <&main_gpio1>; > + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; Update here accordingly to use GIC_SPI. With that changed, Reviewed-by: Wadim Egorov Regards, Wadim