From: John Garry <john.g.garry@oracle.com>
To: Jing Zhang <renyu.zj@linux.alibaba.com>,
Ian Rogers <irogers@google.com>,
Xing Zhengjun <zhengjun.xing@linux.intel.com>,
Will Deacon <will@kernel.org>, James Clark <james.clark@arm.com>,
Mike Leach <mike.leach@linaro.org>, Leo Yan <leo.yan@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org,
linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Namhyung Kim <namhyung@kernel.org>,
Andrew Kilroy <andrew.kilroy@arm.com>,
Shuai Xue <xueshuai@linux.alibaba.com>,
Zhuo Song <zhuo.song@linux.alibaba.com>
Subject: Re: [PATCH v5 1/6] perf vendor events arm64: Add topdown L1 metrics for neoverse-n2
Date: Thu, 5 Jan 2023 10:13:21 +0000 [thread overview]
Message-ID: <00bf227a-75ce-c63c-c740-89b8d2b27e1c@oracle.com> (raw)
In-Reply-To: <d4d132d9-1513-6a4e-981f-aa4bc4ebbcbb@linux.alibaba.com>
On 05/01/2023 10:05, Jing Zhang wrote:
>> However, for this value of slot, isn't this discoverable from a system register per core? Quoting the sbsa: "The IMPLEMENTATION DEFINED constant SLOTS is discoverable from the system register PMMIR_EL1.SLOTS." Did you consider how this could be used?
>>
>
> This may be a feasible idea. The value of slots comes from the register PMMIR_EL1, which I can read in
> /sys/bus/event_source/device/armv8_pmuv3_*/caps/slots. But how do I replace the slots in MetricExpr with the
> read slots values? Currently I understand that parameters in metricExpr only support events and constants.
>
Maybe during runtime we could create a pseudo metric/event for SLOT.
This metric would be created during init, and it always just returns the
value which was read from PMMIR_EL1.
I'm not sure how well that would play will trying to resolve metrics
when building generated pmu-events.c, but I don't think it's all too
difficult to achieve.
Have you actually read this value for the n2 core? Does look correct?
Thanks,
John
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next prev parent reply other threads:[~2023-01-05 20:11 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-03 11:39 [PATCH v5 0/6] Add metrics for neoverse-n2 Jing Zhang
2023-01-03 11:39 ` [PATCH v5 1/6] perf vendor events arm64: Add topdown L1 " Jing Zhang
2023-01-03 11:52 ` John Garry
2023-01-04 5:05 ` Jing Zhang
2023-01-04 17:26 ` John Garry
2023-01-05 10:05 ` Jing Zhang
2023-01-05 10:13 ` John Garry [this message]
2023-01-05 11:02 ` Jing Zhang
2023-01-05 21:13 ` Ian Rogers
2023-01-06 10:14 ` John Garry
2023-01-06 10:34 ` Jing Zhang
2023-01-09 15:34 ` James Clark
2023-01-11 6:14 ` Ian Rogers
2023-01-03 11:39 ` [PATCH v5 2/6] perf vendor events arm64: Add TLB " Jing Zhang
2023-01-03 17:14 ` Ian Rogers
2023-01-04 5:21 ` Jing Zhang
2023-01-04 8:40 ` Jing Zhang
2023-01-04 16:57 ` Ian Rogers
2023-01-03 11:39 ` [PATCH v5 3/6] perf vendor events arm64: Add cache " Jing Zhang
2023-01-03 11:39 ` [PATCH v5 4/6] perf vendor events arm64: Add branch " Jing Zhang
2023-01-03 11:39 ` [PATCH v5 5/6] perf vendor events arm64: Add PE utilization " Jing Zhang
2023-01-03 11:39 ` [PATCH v5 6/6] perf vendor events arm64: Add instruction mix " Jing Zhang
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