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Thu, 16 Apr 2020 16:17:36 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 9E08DC4478C; Thu, 16 Apr 2020 16:17:35 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan) by smtp.codeaurora.org (Postfix) with ESMTPSA id 4130BC433F2; Thu, 16 Apr 2020 16:17:34 +0000 (UTC) MIME-Version: 1.0 Date: Thu, 16 Apr 2020 21:47:34 +0530 From: Sai Prakash Ranjan To: Mathieu Poirier Subject: Re: [PATCH] coresight: tmc: Read TMC mode only when TMC hw is enabled In-Reply-To: References: <20200409113538.5008-1-saiprakash.ranjan@codeaurora.org> <9a792e3e-5a17-156d-4b59-4a3ec8f9993e@arm.com> <1751aeabd22bee18d2eef0f643883265@codeaurora.org> <20200413171418.GB28804@xps15> <75ef334a7e2cc6d87deecadd12c74f59@codeaurora.org> Message-ID: <00cd8a8e124ada16f36937c4a1b173b9@codeaurora.org> X-Sender: saiprakash.ranjan@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200416_091748_266181_B1E06AE4 X-CRM114-Status: GOOD ( 24.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Suzuki K Poulose , linux-arm-msm , Linux Kernel Mailing List , Stephen Boyd , linux-arm-msm-owner@vger.kernel.org, linux-arm-kernel , Mike Leach Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Mathieu, On 2020-04-15 21:26, Mathieu Poirier wrote: > On Tue, 14 Apr 2020 at 09:47, Sai Prakash Ranjan > wrote: >> >> Hi Mathieu, >> >> On 2020-04-13 22:44, Mathieu Poirier wrote: >> > On Mon, Apr 13, 2020 at 01:55:30PM +0530, Sai Prakash Ranjan wrote: >> >> Hi Suzuki, >> >> >> >> On 2020-04-13 04:47, Suzuki K Poulose wrote: >> >> > Hi Sai, >> >> > >> >> > On 04/09/2020 12:35 PM, Sai Prakash Ranjan wrote: >> >> > > Reading TMC mode register in tmc_read_prepare_etb without >> >> > > enabling the TMC hardware leads to async exceptions like >> >> > > the one in the call trace below. This can happen if the >> >> > > user tries to read the TMC etf data via device node without >> >> > > setting up source and the sink first which enables the TMC >> >> > > hardware in the path. So make sure that the TMC is enabled >> >> > > before we try to read TMC data. >> >> > >> >> > So, one can trigger the same SError by simply : >> >> > >> >> > $ cat /sys/bus/coresight/device/tmc_etb0/mgmt/mode >> >> > >> >> >> >> I do not see any SError when I run the above command. >> >> >> >> localhost ~ # cat /sys/bus/coresight/devices/tmc_etf0/mgmt/mode >> >> 0x0 >> >> >> >> And this is most likely due to >> >> >> >> commit cd9e3474bb793dc ("coresight: add PM runtime calls to >> >> coresight_simple_func()") >> > >> > Ok, so this is related to power management (you can ignore my question >> > in the >> > previous email). >> > >> > Regarding function tmc_read_prepare_etb(), the best way to deal with >> > this is >> > probably make sure drvdata->mode != CS_MODE_DISABLED before reading >> > TMC_MODE. >> > If there is a buffer to read it will have been copied when the ETB was >> > disabled >> > and there won't be a need to access the HW. >> > >> >> This works as well, thanks. >> >> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c >> b/drivers/hwtracing/coresight/coresight-tmc-etf.c >> index d0cc3985b72a..7ffe05930984 100644 >> --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c >> +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c >> @@ -596,6 +596,11 @@ int tmc_read_prepare_etb(struct tmc_drvdata >> *drvdata) >> goto out; >> } >> >> + if (drvdata->mode == CS_MODE_DISABLED) { >> + ret = -EINVAL; >> + goto out; >> + } >> + > > We are back to your original solution where the ETB buffer can't be > read if the ETB itself is not enabled. It _is_ possible to read the > buffer of an ETB that has been disabled. > > To fix this consider the following [1]. Take the block at line 607 > and move it to line 598. As part of the if() condition at line 619, > read the value of the TMC_MODE register and exit if not in circular > mode. If it is in circular mode continue with disabling the hardware. > > [1]. > https://elixir.bootlin.com/linux/v5.7-rc1/source/drivers/hwtracing/coresight/coresight-tmc-etf.c > Thanks, got it now. Posted v2 - https://lore.kernel.org/patchwork/patch/1226022/ -Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel