[PATCH 0/7] ARM: EXYNOS4: Update PM

[PATCH 0/7] ARM: EXYNOS4: Update PM

[Kukjin Kim]

Note: This depends on external GIC of EXYNOS4.

[PATCH 1/7] ARM: EXYNOS4: Support system level power down configuration
[PATCH 2/7] ARM: EXYNOS4: Remove PMU configuration for S2RAM
[PATCH 3/7] ARM: EXYNOS4: Add support PM with external GIC
[PATCH 4/7] ARM: EXYNOS4: Support early wakeup while entering sleep mode
[PATCH 5/7] ARM: EXYNOS4: Add save/restore function for PLL
[PATCH 6/7] ARM: EXYNOS4: Add save/restore for more ARM registers
[PATCH 7/7] ARM: EXYNOS4: Move S5P_CENTRAL_SEQ_CONFIGURATION setting for PM

[PATCH 1/7] ARM: EXYNOS4: Support system level power down configuration

[Kukjin Kim]

From: Jaecheol Lee <jc.lee@samsung.com>

EXYNOS4 supports 3 different system level power down mode by PMU (Power
Management Unit). Each power down mode need to configure many PMU registers
with different value. This patch supports function to configure PMU registers
with pre-defined values in PMU code. This function may be used by PM code and
AFTR/LPA support driver.

Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/mach-exynos4/Makefile           |    2 +-
 arch/arm/mach-exynos4/include/mach/pmu.h |   27 +++++
 arch/arm/mach-exynos4/pmu.c              |  175 ++++++++++++++++++++++++++++++
 3 files changed, 203 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-exynos4/include/mach/pmu.h
 create mode 100644 arch/arm/mach-exynos4/pmu.c

diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index 60fe5ec..880f902 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -13,7 +13,7 @@ obj-				:=
 # Core support for EXYNOS4 system
 
 obj-$(CONFIG_CPU_EXYNOS4210)	+= cpu.o init.o clock.o irq-combiner.o
-obj-$(CONFIG_CPU_EXYNOS4210)	+= setup-i2c0.o irq-eint.o dma.o
+obj-$(CONFIG_CPU_EXYNOS4210)	+= setup-i2c0.o irq-eint.o dma.o pmu.o
 obj-$(CONFIG_PM)		+= pm.o sleep.o
 obj-$(CONFIG_CPU_FREQ)		+= cpufreq.o
 obj-$(CONFIG_CPU_IDLE)		+= cpuidle.o
diff --git a/arch/arm/mach-exynos4/include/mach/pmu.h b/arch/arm/mach-exynos4/include/mach/pmu.h
new file mode 100644
index 0000000..4f9c976
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/pmu.h
@@ -0,0 +1,27 @@
+/* linux/arch/arm/mach-exynos4/include/mach/pmu.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS4210 - PMU(Power Management Unit) support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_PMU_H
+#define __ASM_ARCH_PMU_H __FILE__
+
+enum sys_powerdown {
+	SYS_AFTR,
+	SYS_LPA,
+	SYS_SLEEP,
+	NUM_SYS_POWERDOWN,
+};
+
+extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
+extern int exynos4_enter_lp(unsigned long *saveblk, long);
+extern void exynos4_idle_resume(void);
+
+#endif /* __ASM_ARCH_PMU_H */
diff --git a/arch/arm/mach-exynos4/pmu.c b/arch/arm/mach-exynos4/pmu.c
new file mode 100644
index 0000000..7ea9eb2
--- /dev/null
+++ b/arch/arm/mach-exynos4/pmu.c
@@ -0,0 +1,175 @@
+/* linux/arch/arm/mach-exynos4/pmu.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * EXYNOS4210 - CPU PMU(Power Management Unit) support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+
+#include <mach/regs-clock.h>
+#include <mach/pmu.h>
+
+static void __iomem *sys_powerdown_reg[] = {
+	S5P_ARM_CORE0_LOWPWR,
+	S5P_DIS_IRQ_CORE0,
+	S5P_DIS_IRQ_CENTRAL0,
+	S5P_ARM_CORE1_LOWPWR,
+	S5P_DIS_IRQ_CORE1,
+	S5P_DIS_IRQ_CENTRAL1,
+	S5P_ARM_COMMON_LOWPWR,
+	S5P_L2_0_LOWPWR,
+	S5P_L2_1_LOWPWR,
+	S5P_CMU_ACLKSTOP_LOWPWR,
+	S5P_CMU_SCLKSTOP_LOWPWR,
+	S5P_CMU_RESET_LOWPWR,
+	S5P_APLL_SYSCLK_LOWPWR,
+	S5P_MPLL_SYSCLK_LOWPWR,
+	S5P_VPLL_SYSCLK_LOWPWR,
+	S5P_EPLL_SYSCLK_LOWPWR,
+	S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,
+	S5P_CMU_RESET_GPSALIVE_LOWPWR,
+	S5P_CMU_CLKSTOP_CAM_LOWPWR,
+	S5P_CMU_CLKSTOP_TV_LOWPWR,
+	S5P_CMU_CLKSTOP_MFC_LOWPWR,
+	S5P_CMU_CLKSTOP_G3D_LOWPWR,
+	S5P_CMU_CLKSTOP_LCD0_LOWPWR,
+	S5P_CMU_CLKSTOP_LCD1_LOWPWR,
+	S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,
+	S5P_CMU_CLKSTOP_GPS_LOWPWR,
+	S5P_CMU_RESET_CAM_LOWPWR,
+	S5P_CMU_RESET_TV_LOWPWR,
+	S5P_CMU_RESET_MFC_LOWPWR,
+	S5P_CMU_RESET_G3D_LOWPWR,
+	S5P_CMU_RESET_LCD0_LOWPWR,
+	S5P_CMU_RESET_LCD1_LOWPWR,
+	S5P_CMU_RESET_MAUDIO_LOWPWR,
+	S5P_CMU_RESET_GPS_LOWPWR,
+	S5P_TOP_BUS_LOWPWR,
+	S5P_TOP_RETENTION_LOWPWR,
+	S5P_TOP_PWR_LOWPWR,
+	S5P_LOGIC_RESET_LOWPWR,
+	S5P_ONENAND_MEM_LOWPWR,
+	S5P_MODIMIF_MEM_LOWPWR,
+	S5P_G2D_ACP_MEM_LOWPWR,
+	S5P_USBOTG_MEM_LOWPWR,
+	S5P_HSMMC_MEM_LOWPWR,
+	S5P_CSSYS_MEM_LOWPWR,
+	S5P_SECSS_MEM_LOWPWR,
+	S5P_PCIE_MEM_LOWPWR,
+	S5P_SATA_MEM_LOWPWR,
+	S5P_PAD_RETENTION_DRAM_LOWPWR,
+	S5P_PAD_RETENTION_MAUDIO_LOWPWR,
+	S5P_PAD_RETENTION_GPIO_LOWPWR,
+	S5P_PAD_RETENTION_UART_LOWPWR,
+	S5P_PAD_RETENTION_MMCA_LOWPWR,
+	S5P_PAD_RETENTION_MMCB_LOWPWR,
+	S5P_PAD_RETENTION_EBIA_LOWPWR,
+	S5P_PAD_RETENTION_EBIB_LOWPWR,
+	S5P_PAD_RETENTION_ISOLATION_LOWPWR,
+	S5P_PAD_RETENTION_ALV_SEL_LOWPWR,
+	S5P_XUSBXTI_LOWPWR,
+	S5P_XXTI_LOWPWR,
+	S5P_EXT_REGULATOR_LOWPWR,
+	S5P_GPIO_MODE_LOWPWR,
+	S5P_GPIO_MODE_MAUDIO_LOWPWR,
+	S5P_CAM_LOWPWR,
+	S5P_TV_LOWPWR,
+	S5P_MFC_LOWPWR,
+	S5P_G3D_LOWPWR,
+	S5P_LCD0_LOWPWR,
+	S5P_LCD1_LOWPWR,
+	S5P_MAUDIO_LOWPWR,
+	S5P_GPS_LOWPWR,
+	S5P_GPS_ALIVE_LOWPWR,
+};
+
+static const unsigned int sys_powerdown_val[][NUM_SYS_POWERDOWN] = {
+	/* { AFTR, LPA, SLEEP }*/
+	{ 0, 0, 2 },	/* ARM_CORE0 */
+	{ 0, 0, 0 },	/* ARM_DIS_IRQ_CORE0 */
+	{ 0, 0, 0 },	/* ARM_DIS_IRQ_CENTRAL0 */
+	{ 0, 0, 2 },	/* ARM_CORE1 */
+	{ 0, 0, 0 },	/* ARM_DIS_IRQ_CORE1 */
+	{ 0, 0, 0 },	/* ARM_DIS_IRQ_CENTRAL1 */
+	{ 0, 0, 2 },	/* ARM_COMMON */
+	{ 2, 2, 3 },	/* ARM_CPU_L2_0 */
+	{ 2, 2, 3 },	/* ARM_CPU_L2_1 */
+	{ 1, 0, 0 },	/* CMU_ACLKSTOP */
+	{ 1, 0, 0 },	/* CMU_SCLKSTOP */
+	{ 1, 1, 0 },	/* CMU_RESET */
+	{ 1, 0, 0 },	/* APLL_SYSCLK */
+	{ 1, 0, 0 },	/* MPLL_SYSCLK */
+	{ 1, 0, 0 },	/* VPLL_SYSCLK */
+	{ 1, 1, 0 },	/* EPLL_SYSCLK */
+	{ 1, 1, 0 },	/* CMU_CLKSTOP_GPS_ALIVE */
+	{ 1, 1, 0 },	/* CMU_RESET_GPS_ALIVE */
+	{ 1, 1, 0 },	/* CMU_CLKSTOP_CAM */
+	{ 1, 1, 0 },	/* CMU_CLKSTOP_TV */
+	{ 1, 1, 0 },	/* CMU_CLKSTOP_MFC */
+	{ 1, 1, 0 },	/* CMU_CLKSTOP_G3D */
+	{ 1, 1, 0 },	/* CMU_CLKSTOP_LCD0 */
+	{ 1, 1, 0 },	/* CMU_CLKSTOP_LCD1 */
+	{ 1, 1, 0 },	/* CMU_CLKSTOP_MAUDIO */
+	{ 1, 1, 0 },	/* CMU_CLKSTOP_GPS */
+	{ 1, 1, 0 },	/* CMU_RESET_CAM */
+	{ 1, 1, 0 },	/* CMU_RESET_TV */
+	{ 1, 1, 0 },	/* CMU_RESET_MFC */
+	{ 1, 1, 0 },	/* CMU_RESET_G3D */
+	{ 1, 1, 0 },	/* CMU_RESET_LCD0 */
+	{ 1, 1, 0 },	/* CMU_RESET_LCD1 */
+	{ 1, 1, 0 },	/* CMU_RESET_MAUDIO */
+	{ 1, 1, 0 },	/* CMU_RESET_GPS */
+	{ 3, 0, 0 },	/* TOP_BUS */
+	{ 1, 0, 1 },	/* TOP_RETENTION */
+	{ 3, 0, 3 },	/* TOP_PWR */
+	{ 1, 1, 0 },	/* LOGIC_RESET */
+	{ 3, 0, 0 },	/* ONENAND_MEM */
+	{ 3, 0, 0 },	/* MODIMIF_MEM */
+	{ 3, 0, 0 },	/* G2D_ACP_MEM */
+	{ 3, 0, 0 },	/* USBOTG_MEM */
+	{ 3, 0, 0 },	/* HSMMC_MEM */
+	{ 3, 0, 0 },	/* CSSYS_MEM */
+	{ 3, 0, 0 },	/* SECSS_MEM */
+	{ 3, 0, 0 },	/* PCIE_MEM */
+	{ 3, 0, 0 },	/* SATA_MEM */
+	{ 1, 0, 0 },	/* PAD_RETENTION_DRAM */
+	{ 1, 1, 0 },	/* PAD_RETENTION_MAUDIO */
+	{ 1, 0, 0 },	/* PAD_RETENTION_GPIO */
+	{ 1, 0, 0 },	/* PAD_RETENTION_UART */
+	{ 1, 0, 0 },	/* PAD_RETENTION_MMCA */
+	{ 1, 0, 0 },	/* PAD_RETENTION_MMCB */
+	{ 1, 0, 0 },	/* PAD_RETENTION_EBIA */
+	{ 1, 0, 0 },	/* PAD_RETENTION_EBIB */
+	{ 1, 0, 0 },	/* PAD_RETENTION_ISOLATION */
+	{ 1, 0, 0 },	/* PAD_RETENTION_ALV_SEL */
+	{ 1, 1, 0 },	/* XUSBXTI */
+	{ 1, 1, 0 },	/* XXTI */
+	{ 1, 1, 0 },	/* EXT_REGULATOR */
+	{ 1, 0, 0 },	/* GPIO_MODE */
+	{ 1, 1, 0 },	/* GPIO_MODE_MAUDIO */
+	{ 7, 0, 0 },	/* CAM */
+	{ 7, 0, 0 },	/* TV */
+	{ 7, 0, 0 },	/* MFC */
+	{ 7, 0, 0 },	/* G3D */
+	{ 7, 0, 0 },	/* LCD0 */
+	{ 7, 0, 0 },	/* LCD1 */
+	{ 7, 7, 0 },	/* MAUDIO */
+	{ 7, 0, 0 },	/* GPS */
+	{ 7, 0, 0 },	/* GPS_ALIVE */
+};
+
+void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
+{
+	unsigned int count = ARRAY_SIZE(sys_powerdown_reg);
+
+	for (; count > 0; count--)
+		__raw_writel(sys_powerdown_val[count - 1][mode],
+				sys_powerdown_reg[count - 1]);
+}
-- 
1.7.1

[PATCH 2/7] ARM: EXYNOS4: Remove PMU configuration for S2RAM

[Kukjin Kim]

From: Jaecheol Lee <jc.lee@samsung.com>

PMU(Power Management Unit) configuraion for S2RAM(SLEEP) is removed
and using function which provided by PMU support code to configure
PMU register.

Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/mach-exynos4/pm.c |   77 +------------------------------------------
 1 files changed, 2 insertions(+), 75 deletions(-)

diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index 8755ca8..a073a01 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -30,80 +30,7 @@
 #include <mach/regs-clock.h>
 #include <mach/regs-pmu.h>
 #include <mach/pm-core.h>
-
-static struct sleep_save exynos4_sleep[] = {
-	{ .reg = S5P_ARM_CORE0_LOWPWR			, .val = 0x2, },
-	{ .reg = S5P_DIS_IRQ_CORE0			, .val = 0x0, },
-	{ .reg = S5P_DIS_IRQ_CENTRAL0			, .val = 0x0, },
-	{ .reg = S5P_ARM_CORE1_LOWPWR			, .val = 0x2, },
-	{ .reg = S5P_DIS_IRQ_CORE1			, .val = 0x0, },
-	{ .reg = S5P_DIS_IRQ_CENTRAL1			, .val = 0x0, },
-	{ .reg = S5P_ARM_COMMON_LOWPWR			, .val = 0x2, },
-	{ .reg = S5P_L2_0_LOWPWR			, .val = 0x3, },
-	{ .reg = S5P_L2_1_LOWPWR			, .val = 0x3, },
-	{ .reg = S5P_CMU_ACLKSTOP_LOWPWR		, .val = 0x0, },
-	{ .reg = S5P_CMU_SCLKSTOP_LOWPWR		, .val = 0x0, },
-	{ .reg = S5P_CMU_RESET_LOWPWR			, .val = 0x0, },
-	{ .reg = S5P_APLL_SYSCLK_LOWPWR			, .val = 0x0, },
-	{ .reg = S5P_MPLL_SYSCLK_LOWPWR			, .val = 0x0, },
-	{ .reg = S5P_VPLL_SYSCLK_LOWPWR			, .val = 0x0, },
-	{ .reg = S5P_EPLL_SYSCLK_LOWPWR			, .val = 0x0, },
-	{ .reg = S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR	, .val = 0x0, },
-	{ .reg = S5P_CMU_RESET_GPSALIVE_LOWPWR		, .val = 0x0, },
-	{ .reg = S5P_CMU_CLKSTOP_CAM_LOWPWR		, .val = 0x0, },
-	{ .reg = S5P_CMU_CLKSTOP_TV_LOWPWR		, .val = 0x0, },
-	{ .reg = S5P_CMU_CLKSTOP_MFC_LOWPWR		, .val = 0x0, },
-	{ .reg = S5P_CMU_CLKSTOP_G3D_LOWPWR		, .val = 0x0, },
-	{ .reg = S5P_CMU_CLKSTOP_LCD0_LOWPWR		, .val = 0x0, },
-	{ .reg = S5P_CMU_CLKSTOP_LCD1_LOWPWR		, .val = 0x0, },
-	{ .reg = S5P_CMU_CLKSTOP_MAUDIO_LOWPWR		, .val = 0x0, },
-	{ .reg = S5P_CMU_CLKSTOP_GPS_LOWPWR		, .val = 0x0, },
-	{ .reg = S5P_CMU_RESET_CAM_LOWPWR		, .val = 0x0, },
-	{ .reg = S5P_CMU_RESET_TV_LOWPWR		, .val = 0x0, },
-	{ .reg = S5P_CMU_RESET_MFC_LOWPWR		, .val = 0x0, },
-	{ .reg = S5P_CMU_RESET_G3D_LOWPWR		, .val = 0x0, },
-	{ .reg = S5P_CMU_RESET_LCD0_LOWPWR		, .val = 0x0, },
-	{ .reg = S5P_CMU_RESET_LCD1_LOWPWR		, .val = 0x0, },
-	{ .reg = S5P_CMU_RESET_MAUDIO_LOWPWR		, .val = 0x0, },
-	{ .reg = S5P_CMU_RESET_GPS_LOWPWR		, .val = 0x0, },
-	{ .reg = S5P_TOP_BUS_LOWPWR			, .val = 0x0, },
-	{ .reg = S5P_TOP_RETENTION_LOWPWR		, .val = 0x1, },
-	{ .reg = S5P_TOP_PWR_LOWPWR			, .val = 0x3, },
-	{ .reg = S5P_LOGIC_RESET_LOWPWR			, .val = 0x0, },
-	{ .reg = S5P_ONENAND_MEM_LOWPWR			, .val = 0x0, },
-	{ .reg = S5P_MODIMIF_MEM_LOWPWR			, .val = 0x0, },
-	{ .reg = S5P_G2D_ACP_MEM_LOWPWR			, .val = 0x0, },
-	{ .reg = S5P_USBOTG_MEM_LOWPWR			, .val = 0x0, },
-	{ .reg = S5P_HSMMC_MEM_LOWPWR			, .val = 0x0, },
-	{ .reg = S5P_CSSYS_MEM_LOWPWR			, .val = 0x0, },
-	{ .reg = S5P_SECSS_MEM_LOWPWR			, .val = 0x0, },
-	{ .reg = S5P_PCIE_MEM_LOWPWR			, .val = 0x0, },
-	{ .reg = S5P_SATA_MEM_LOWPWR			, .val = 0x0, },
-	{ .reg = S5P_PAD_RETENTION_DRAM_LOWPWR		, .val = 0x0, },
-	{ .reg = S5P_PAD_RETENTION_MAUDIO_LOWPWR	, .val = 0x0, },
-	{ .reg = S5P_PAD_RETENTION_GPIO_LOWPWR		, .val = 0x0, },
-	{ .reg = S5P_PAD_RETENTION_UART_LOWPWR		, .val = 0x0, },
-	{ .reg = S5P_PAD_RETENTION_MMCA_LOWPWR		, .val = 0x0, },
-	{ .reg = S5P_PAD_RETENTION_MMCB_LOWPWR		, .val = 0x0, },
-	{ .reg = S5P_PAD_RETENTION_EBIA_LOWPWR		, .val = 0x0, },
-	{ .reg = S5P_PAD_RETENTION_EBIB_LOWPWR		, .val = 0x0, },
-	{ .reg = S5P_PAD_RETENTION_ISOLATION_LOWPWR	, .val = 0x0, },
-	{ .reg = S5P_PAD_RETENTION_ALV_SEL_LOWPWR	, .val = 0x0, },
-	{ .reg = S5P_XUSBXTI_LOWPWR			, .val = 0x0, },
-	{ .reg = S5P_XXTI_LOWPWR			, .val = 0x0, },
-	{ .reg = S5P_EXT_REGULATOR_LOWPWR		, .val = 0x0, },
-	{ .reg = S5P_GPIO_MODE_LOWPWR			, .val = 0x0, },
-	{ .reg = S5P_GPIO_MODE_MAUDIO_LOWPWR		, .val = 0x0, },
-	{ .reg = S5P_CAM_LOWPWR				, .val = 0x0, },
-	{ .reg = S5P_TV_LOWPWR				, .val = 0x0, },
-	{ .reg = S5P_MFC_LOWPWR				, .val = 0x0, },
-	{ .reg = S5P_G3D_LOWPWR				, .val = 0x0, },
-	{ .reg = S5P_LCD0_LOWPWR			, .val = 0x0, },
-	{ .reg = S5P_LCD1_LOWPWR			, .val = 0x0, },
-	{ .reg = S5P_MAUDIO_LOWPWR			, .val = 0x0, },
-	{ .reg = S5P_GPS_LOWPWR				, .val = 0x0, },
-	{ .reg = S5P_GPS_ALIVE_LOWPWR			, .val = 0x0, },
-};
+#include <mach/pmu.h>
 
 static struct sleep_save exynos4_set_clksrc[] = {
 	{ .reg = S5P_CLKSRC_MASK_TOP			, .val = 0x00000001, },
@@ -331,7 +258,7 @@ static void exynos4_pm_prepare(void)
 
 	/* Set value of power down register for sleep mode */
 
-	s3c_pm_do_restore_core(exynos4_sleep, ARRAY_SIZE(exynos4_sleep));
+	exynos4_sys_powerdown_conf(SYS_SLEEP);
 	__raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
 
 	/* ensure at least INFORM0 has the resume address */
-- 
1.7.1

[PATCH 3/7] ARM: EXYNOS4: Add support PM with external GIC

[Kukjin Kim]

From: Jaecheol Lee <jc.lee@samsung.com>

Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/mach-exynos4/pm.c |   43 +++++++++++++++++++++++++++++++++++++------
 1 files changed, 37 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index a073a01..bf53588 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -154,6 +154,22 @@ static struct sleep_save exynos4_core_save[] = {
 	SAVE_ITEM(S5P_VA_GIC_DIST + 0x454),
 	SAVE_ITEM(S5P_VA_GIC_DIST + 0x458),
 	SAVE_ITEM(S5P_VA_GIC_DIST + 0x45C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x460),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x464),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x468),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x46C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x470),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x474),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x478),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x47C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x480),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x484),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x488),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x48C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x490),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x494),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x498),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x49C),
 
 	SAVE_ITEM(S5P_VA_GIC_DIST + 0x800),
 	SAVE_ITEM(S5P_VA_GIC_DIST + 0x804),
@@ -179,6 +195,22 @@ static struct sleep_save exynos4_core_save[] = {
 	SAVE_ITEM(S5P_VA_GIC_DIST + 0x854),
 	SAVE_ITEM(S5P_VA_GIC_DIST + 0x858),
 	SAVE_ITEM(S5P_VA_GIC_DIST + 0x85C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x860),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x864),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x868),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x86C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x870),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x874),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x878),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x87C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x880),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x884),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x888),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x88C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x890),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x894),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x898),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0x89C),
 
 	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC00),
 	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC04),
@@ -186,17 +218,16 @@ static struct sleep_save exynos4_core_save[] = {
 	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC0C),
 	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC10),
 	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC14),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC18),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC1C),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC20),
+	SAVE_ITEM(S5P_VA_GIC_DIST + 0xC24),
+
 
 	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x000),
 	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x010),
 	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x020),
 	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x030),
-	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x040),
-	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x050),
-	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x060),
-	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070),
-	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080),
-	SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090),
 };
 
 static struct sleep_save exynos4_l2cc_save[] = {
-- 
1.7.1

[PATCH 4/7] ARM: EXYNOS4: Support early wakeup while entering sleep mode

[Kukjin Kim]

From: Jaecheol Lee <jc.lee@samsung.com>

We don't need to masking GIC with external GIC and changed in handling
early wakeup interrupt situation. In case of early wakeup situation,
PMU dosen't enter sleep mode by WFI wihch will be ignored.
This patch can handle this abnormal situation by early wakeup interrupt.

Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/mach-exynos4/pm.c    |   43 ++++++++++++++++++----------------------
 arch/arm/mach-exynos4/sleep.S |   15 +++++++++++--
 2 files changed, 31 insertions(+), 27 deletions(-)

diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index bf53588..f4d52b5 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -241,7 +241,6 @@ static struct sleep_save exynos4_l2cc_save[] = {
 void exynos4_cpu_suspend(void)
 {
 	unsigned long tmp;
-	unsigned long mask = 0xFFFFFFFF;
 
 	/* Setting Central Sequence Register for power down mode */
 
@@ -249,33 +248,10 @@ void exynos4_cpu_suspend(void)
 	tmp &= ~(S5P_CENTRAL_LOWPWR_CFG);
 	__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 
-	/* Setting Central Sequence option Register */
-
-	tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
-	tmp &= ~(S5P_USE_MASK);
-	tmp |= S5P_USE_STANDBY_WFI0;
-	__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
-
-	/* Clear all interrupt pending to avoid early wakeup */
-
-	__raw_writel(mask, (S5P_VA_GIC_DIST + 0x280));
-	__raw_writel(mask, (S5P_VA_GIC_DIST + 0x284));
-	__raw_writel(mask, (S5P_VA_GIC_DIST + 0x288));
-
-	/* Disable all interrupt */
-
-	__raw_writel(0x0, (S5P_VA_GIC_CPU + 0x000));
-	__raw_writel(0x0, (S5P_VA_GIC_DIST + 0x000));
-	__raw_writel(mask, (S5P_VA_GIC_DIST + 0x184));
-	__raw_writel(mask, (S5P_VA_GIC_DIST + 0x188));
-
 	outer_flush_all();
 
 	/* issue the standby signal into the pm unit. */
 	cpu_do_idle();
-
-	/* we should never get past here */
-	panic("sleep resumed to originator?");
 }
 
 static void exynos4_pm_prepare(void)
@@ -353,6 +329,22 @@ arch_initcall(exynos4_pm_drvinit);
 
 static void exynos4_pm_resume(void)
 {
+	unsigned long tmp;
+
+	/*
+	 * If PMU failed while entering sleep mode, WFI will be
+	 * ignored by PMU and then exiting cpu_do_idle().
+	 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
+	 * in this situation.
+	 */
+	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+	if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
+		tmp |= S5P_CENTRAL_LOWPWR_CFG;
+		__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+		/* No need to perform below restore code */
+		goto early_wakeup;
+	}
+
 	/* For release retention */
 
 	__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
@@ -373,6 +365,9 @@ static void exynos4_pm_resume(void)
 	/* enable L2X0*/
 	writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
 #endif
+
+early_wakeup:
+	return;
 }
 
 static struct syscore_ops exynos4_pm_syscore_ops = {
diff --git a/arch/arm/mach-exynos4/sleep.S b/arch/arm/mach-exynos4/sleep.S
index 6b62425..d55d38c 100644
--- a/arch/arm/mach-exynos4/sleep.S
+++ b/arch/arm/mach-exynos4/sleep.S
@@ -45,11 +45,20 @@ ENTRY(s3c_cpu_save)
 	ldr	r3, =resume_with_mmu
 	bl	cpu_suspend
 
-	ldr	r0, =pm_cpu_sleep
-	ldr	r0, [ r0 ]
-	mov	pc, r0
+	bl	exynos4_cpu_suspend
+
+	/* Restore original sp */
+	mov	r0, sp
+	add	r0, r0, #4
+	ldr	sp, [r0]
+
+	mov	r0, #0
+	b	early_wakeup
 
 resume_with_mmu:
+	mov	r0, #1
+
+early_wakeup:
 	ldmfd	sp!, { r3 - r12, pc }
 
 	.ltorg
-- 
1.7.1

[PATCH 4/7] ARM: EXYNOS4: Support early wakeup while entering sleep mode

[Russell King - ARM Linux]

On Wed, Jun 22, 2011 at 05:46:42PM +0900, Kukjin Kim wrote:
> diff --git a/arch/arm/mach-exynos4/sleep.S b/arch/arm/mach-exynos4/sleep.S
> index 6b62425..d55d38c 100644
> --- a/arch/arm/mach-exynos4/sleep.S
> +++ b/arch/arm/mach-exynos4/sleep.S
> @@ -45,11 +45,20 @@ ENTRY(s3c_cpu_save)
>  	ldr	r3, =resume_with_mmu
>  	bl	cpu_suspend
>  
> -	ldr	r0, =pm_cpu_sleep
> -	ldr	r0, [ r0 ]
> -	mov	pc, r0
> +	bl	exynos4_cpu_suspend
> +
> +	/* Restore original sp */
> +	mov	r0, sp
> +	add	r0, r0, #4
> +	ldr	sp, [r0]
> +
> +	mov	r0, #0
> +	b	early_wakeup
>  
>  resume_with_mmu:
> +	mov	r0, #1
> +
> +early_wakeup:
>  	ldmfd	sp!, { r3 - r12, pc }

NAK.

If we want to return from cpu_suspend() stuff then we need to solve this
properly, as per my patch sent around 13th June to the hibernate thread.

Stop bodging stuff (like you have for the SCU stuff.) and start _talking_
to people if the code doesn't do what you need it to do.

[PATCH 4/7] ARM: EXYNOS4: Support early wakeup while entering sleep mode

[Kukjin Kim]

Russell King - ARM Linux wrote:

> Stop bodging stuff (like you have for the SCU stuff.) and start _talking_
> to people if the code doesn't do what you need it to do.

Hi Russell and all,

I'd like to share requirement of EXYNOS4210 PM.

Now if there is wakeup source which is pending before entering suspend mode,
PMU(Power Management Unit) handles WFI instruction as NOP on EXYNOS4210. But
it seems that current cpu_suspend() cannot support this. So how can/should
we handle this case?

And this is another case. For example, assume that ARM is power down mode
and outer cache(L2 cache) data is retention state to use L2 cache data after
wakeup. In this case, according to wakeup sequence, firstly L1 cache is
enabled in cpu_resume() then L2 cache will be enabled which is implemented
in Samsung SoC specific code. So how can be handled the coherency problem
between L1 cache and L2 cache?

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH 4/7] ARM: EXYNOS4: Support early wakeup while entering sleep mode

[Russell King - ARM Linux]

On Fri, Jun 24, 2011 at 04:42:26PM +0900, Kukjin Kim wrote:
> Russell King - ARM Linux wrote:
> 
> > Stop bodging stuff (like you have for the SCU stuff.) and start _talking_
> > to people if the code doesn't do what you need it to do.
> 
> Hi Russell and all,
> 
> I'd like to share requirement of EXYNOS4210 PM.
> 
> Now if there is wakeup source which is pending before entering suspend mode,
> PMU(Power Management Unit) handles WFI instruction as NOP on EXYNOS4210. But
> it seems that current cpu_suspend() cannot support this. So how can/should
> we handle this case?

See patch from June 13th posted to the hibernate thread.  This allows
the finisher function to return, though it should only return if it is
certain that the system will not enter suspend.

Is this true of the current exynos4 code?  It seems that the current
code will panic() if the WFI is executed as a NOP.

> And this is another case. For example, assume that ARM is power down mode
> and outer cache(L2 cache) data is retention state to use L2 cache data after
> wakeup. In this case, according to wakeup sequence, firstly L1 cache is
> enabled in cpu_resume() then L2 cache will be enabled which is implemented
> in Samsung SoC specific code. So how can be handled the coherency problem
> between L1 cache and L2 cache?

You could ensure that L2 is ready to be re-enabled before calling
cpu_resume.  As the C bit in the control register will be cleared,
L2 should not be used at that point, until after the MMU is re-
initialized.

[PATCH 4/7] ARM: EXYNOS4: Support early wakeup while entering sleep mode

[Russell King - ARM Linux]

On Fri, Jun 24, 2011 at 10:37:50AM +0100, Russell King - ARM Linux wrote:
> On Fri, Jun 24, 2011 at 04:42:26PM +0900, Kukjin Kim wrote:
> > Russell King - ARM Linux wrote:
> > 
> > > Stop bodging stuff (like you have for the SCU stuff.) and start _talking_
> > > to people if the code doesn't do what you need it to do.
> > 
> > Hi Russell and all,
> > 
> > I'd like to share requirement of EXYNOS4210 PM.
> > 
> > Now if there is wakeup source which is pending before entering suspend mode,
> > PMU(Power Management Unit) handles WFI instruction as NOP on EXYNOS4210. But
> > it seems that current cpu_suspend() cannot support this. So how can/should
> > we handle this case?
> 
> See patch from June 13th posted to the hibernate thread.  This allows
> the finisher function to return, though it should only return if it is
> certain that the system will not enter suspend.
> 
> Is this true of the current exynos4 code?  It seems that the current
> code will panic() if the WFI is executed as a NOP.

Here's an updated patch for it against the v3 set of patches.

 arch/arm/include/asm/suspend.h |    9 +++++----
 arch/arm/kernel/sleep.S        |   11 +++++++++--
 2 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/asm/suspend.h b/arch/arm/include/asm/suspend.h
index f8db9d0..54821b5 100644
--- a/arch/arm/include/asm/suspend.h
+++ b/arch/arm/include/asm/suspend.h
@@ -10,12 +10,13 @@ extern void cpu_resume(void);
  * Hide the first two arguments to __cpu_suspend - these are an implementation
  * detail which platform code shouldn't have to know about.
  */
-static inline void cpu_suspend(unsigned long arg, void (*fn)(unsigned long))
+static inline int cpu_suspend(unsigned long arg, void (*fn)(unsigned long))
 {
-	extern void __cpu_suspend(int, long, unsigned long,
-				  void (*)(unsigned long));
-	__cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, arg, fn);
+	extern int __cpu_suspend(int, long, unsigned long,
+				 void (*)(unsigned long));
+	int ret = __cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, arg, fn);
 	flush_tlb_all();
+	return ret;
 }
 
 #endif
diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index c156d0e..dc902f2 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -12,7 +12,6 @@
  *  r1 = v:p offset
  *  r2 = suspend function arg0
  *  r3 = suspend function
- * Note: does not return until system resumes
  */
 ENTRY(__cpu_suspend)
 	stmfd	sp!, {r4 - r11, lr}
@@ -26,7 +25,7 @@ ENTRY(__cpu_suspend)
 #endif
 	mov	r6, sp			@ current virtual SP
 	sub	sp, sp, r5		@ allocate CPU state on stack
-	mov	r0, sp			@ save pointer
+	mov	r0, sp			@ save pointer to CPU save block
 	add	ip, ip, r1		@ convert resume fn to phys
 	stmfd	sp!, {r1, r6, ip}	@ save v:p, virt SP, phys resume fn
 	ldr	r5, =sleep_save_sp
@@ -55,10 +54,17 @@ ENTRY(__cpu_suspend)
 #else
 	bl	__cpuc_flush_kern_all
 #endif
+	adr	lr, BSYM(cpu_suspend_abort)
 	ldmfd	sp!, {r0, pc}		@ call suspend fn
 ENDPROC(__cpu_suspend)
 	.ltorg
 
+cpu_suspend_abort:
+	ldmia	sp!, {r1 - r3}		@ pop v:p, virt SP, phys resume fn
+	mov	sp, r2
+	ldmfd	sp!, {r4 - r11, pc}
+ENDPROC(cpu_suspend_abort)
+
 /*
  * r0 = control register value
  * r1 = v:p offset (preserved by cpu_do_resume)
@@ -89,6 +95,7 @@ cpu_resume_after_mmu:
 	str	r5, [r2, r4, lsl #2]	@ restore old mapping
 	mcr	p15, 0, r0, c1, c0, 0	@ turn on D-cache
 	bl	cpu_init		@ restore the und/abt/irq banked regs
+	mov	r0, #0			@ return zero on success
 	ldmfd	sp!, {r4 - r11, pc}
 ENDPROC(cpu_resume_after_mmu)
 

[PATCH 4/7] ARM: EXYNOS4: Support early wakeup while entering sleep mode

[Kukjin Kim]

Russell King - ARM Linux wrote:
> 
> On Fri, Jun 24, 2011 at 10:37:50AM +0100, Russell King - ARM Linux wrote:
> > On Fri, Jun 24, 2011 at 04:42:26PM +0900, Kukjin Kim wrote:
> > > Russell King - ARM Linux wrote:
> > >

(snip)

> 
> Here's an updated patch for it against the v3 set of patches.
> 
>  arch/arm/include/asm/suspend.h |    9 +++++----
>  arch/arm/kernel/sleep.S        |   11 +++++++++--
>  2 files changed, 14 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/include/asm/suspend.h
b/arch/arm/include/asm/suspend.h
> index f8db9d0..54821b5 100644
> --- a/arch/arm/include/asm/suspend.h
> +++ b/arch/arm/include/asm/suspend.h
> @@ -10,12 +10,13 @@ extern void cpu_resume(void);
>   * Hide the first two arguments to __cpu_suspend - these are an
implementation
>   * detail which platform code shouldn't have to know about.
>   */
> -static inline void cpu_suspend(unsigned long arg, void (*fn)(unsigned
long))
> +static inline int cpu_suspend(unsigned long arg, void (*fn)(unsigned
long))
>  {
> -	extern void __cpu_suspend(int, long, unsigned long,
> -				  void (*)(unsigned long));
> -	__cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, arg, fn);
> +	extern int __cpu_suspend(int, long, unsigned long,
> +				 void (*)(unsigned long));
> +	int ret = __cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, arg, fn);
>  	flush_tlb_all();
> +	return ret;
>  }
> 
>  #endif
> diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
> index c156d0e..dc902f2 100644
> --- a/arch/arm/kernel/sleep.S
> +++ b/arch/arm/kernel/sleep.S
> @@ -12,7 +12,6 @@
>   *  r1 = v:p offset
>   *  r2 = suspend function arg0
>   *  r3 = suspend function
> - * Note: does not return until system resumes
>   */
>  ENTRY(__cpu_suspend)
>  	stmfd	sp!, {r4 - r11, lr}
> @@ -26,7 +25,7 @@ ENTRY(__cpu_suspend)
>  #endif
>  	mov	r6, sp			@ current virtual SP
>  	sub	sp, sp, r5		@ allocate CPU state on stack
> -	mov	r0, sp			@ save pointer
> +	mov	r0, sp			@ save pointer to CPU save block
>  	add	ip, ip, r1		@ convert resume fn to phys
>  	stmfd	sp!, {r1, r6, ip}	@ save v:p, virt SP, phys resume fn
>  	ldr	r5, =sleep_save_sp
> @@ -55,10 +54,17 @@ ENTRY(__cpu_suspend)
>  #else
>  	bl	__cpuc_flush_kern_all
>  #endif
> +	adr	lr, BSYM(cpu_suspend_abort)
>  	ldmfd	sp!, {r0, pc}		@ call suspend fn
>  ENDPROC(__cpu_suspend)
>  	.ltorg
> 
> +cpu_suspend_abort:
> +	ldmia	sp!, {r1 - r3}		@ pop v:p, virt SP, phys resume fn
> +	mov	sp, r2

Russell thanks.

How do you think to add following for handling failure of cpu_suspend?

+	mov	r0, #-1

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

> +	ldmfd	sp!, {r4 - r11, pc}
> +ENDPROC(cpu_suspend_abort)
> +
>  /*
>   * r0 = control register value
>   * r1 = v:p offset (preserved by cpu_do_resume)
> @@ -89,6 +95,7 @@ cpu_resume_after_mmu:
>  	str	r5, [r2, r4, lsl #2]	@ restore old mapping
>  	mcr	p15, 0, r0, c1, c0, 0	@ turn on D-cache
>  	bl	cpu_init		@ restore the und/abt/irq banked
regs
> +	mov	r0, #0			@ return zero on success
>  	ldmfd	sp!, {r4 - r11, pc}
>  ENDPROC(cpu_resume_after_mmu)
> 

[PATCH 4/7] ARM: EXYNOS4: Support early wakeup while entering sleep mode

[Russell King - ARM Linux]

On Fri, Jul 01, 2011 at 10:03:48AM +0900, Kukjin Kim wrote:
> Russell thanks.
> 
> How do you think to add following for handling failure of cpu_suspend?
> 
> +	mov	r0, #-1

No.  -1 is not an error code, and I refuse to create functions which
use an explicit -1 as a return code to indicate failure.

The code is designed so that the called finisher function can return
a valid errno value.

[PATCH 4/7] ARM: EXYNOS4: Support early wakeup while entering sleep mode

[Kukjin Kim]

Russell King - ARM Linux wrote:
> 
> On Fri, Jul 01, 2011 at 10:03:48AM +0900, Kukjin Kim wrote:
> > Russell thanks.
> >
> > How do you think to add following for handling failure of cpu_suspend?
> >
> > +	mov	r0, #-1
> 
> No.  -1 is not an error code, and I refuse to create functions which
> use an explicit -1 as a return code to indicate failure.
> 
I used wrong words, 'handling failure' :(

Actually, it means handling other case, like early wakeup but we will
address comments from you :)

> The code is designed so that the called finisher function can return
> a valid errno value.

OK, I see.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH 4/7] ARM: EXYNOS4: Support early wakeup while entering sleep mode

[Russell King - ARM Linux]

On Mon, Jul 04, 2011 at 06:42:08PM +0900, Kukjin Kim wrote:
> Russell King - ARM Linux wrote:
> > 
> > On Fri, Jul 01, 2011 at 10:03:48AM +0900, Kukjin Kim wrote:
> > > Russell thanks.
> > >
> > > How do you think to add following for handling failure of cpu_suspend?
> > >
> > > +	mov	r0, #-1
> > 
> > No.  -1 is not an error code, and I refuse to create functions which
> > use an explicit -1 as a return code to indicate failure.
> > 
> I used wrong words, 'handling failure' :(
> 
> Actually, it means handling other case, like early wakeup but we will
> address comments from you :)

Bear in mind that others may wish to return negative errno codes
through this, so if you want to indicate 'no need to resume and
restore state' then I guess using a small positive number would be
acceptable to distinguish it from a real error.

[PATCH 4/7] ARM: EXYNOS4: Support early wakeup while entering sleep mode

[Kukjin Kim]

Russell King - ARM Linux wrote:
> >
> > Hi Russell and all,
> >
> > I'd like to share requirement of EXYNOS4210 PM.
> >
> > Now if there is wakeup source which is pending before entering suspend
mode,
> > PMU(Power Management Unit) handles WFI instruction as NOP on EXYNOS4210.
> But
> > it seems that current cpu_suspend() cannot support this. So how
can/should
> > we handle this case?
> 
> See patch from June 13th posted to the hibernate thread.  This allows
> the finisher function to return, though it should only return if it is
> certain that the system will not enter suspend.
> 
> Is this true of the current exynos4 code?  It seems that the current
> code will panic() if the WFI is executed as a NOP.
> 
Yes, you're right, current code cannot control it. Supporting this case will
be scheduled in next patch.

> > And this is another case. For example, assume that ARM is power down
mode
> > and outer cache(L2 cache) data is retention state to use L2 cache data
after
> > wakeup. In this case, according to wakeup sequence, firstly L1 cache is
> > enabled in cpu_resume() then L2 cache will be enabled which is
implemented
> > in Samsung SoC specific code. So how can be handled the coherency
problem
> > between L1 cache and L2 cache?
> 
> You could ensure that L2 is ready to be re-enabled before calling
> cpu_resume.  As the C bit in the control register will be cleared,
> L2 should not be used at that point, until after the MMU is re-
> initialized.

Russell, thanks for your kindly explanation :)

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH 5/7] ARM: EXYNOS4: Add save/restore function for PLL

[Kukjin Kim]

From: Jaecheol Lee <jc.lee@samsung.com>

The PLL restore routine supports waiting pll locking. If PLL is
enabled in restoring sequence, it should wait until PLL is locked.

Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/mach-exynos4/include/mach/regs-clock.h |    9 ++
 arch/arm/mach-exynos4/pm.c                      |   96 ++++++++++++++++++++++-
 2 files changed, 101 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h
index 6e311c1..64bdd24 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h
@@ -25,6 +25,9 @@
 #define S5P_CLKDIV_STAT_RIGHTBUS	S5P_CLKREG(0x08600)
 #define S5P_CLKGATE_IP_RIGHTBUS		S5P_CLKREG(0x08800)
 
+#define S5P_EPLL_LOCK			S5P_CLKREG(0x0C010)
+#define S5P_VPLL_LOCK			S5P_CLKREG(0x0C020)
+
 #define S5P_EPLL_CON0			S5P_CLKREG(0x0C110)
 #define S5P_EPLL_CON1			S5P_CLKREG(0x0C114)
 #define S5P_VPLL_CON0			S5P_CLKREG(0x0C120)
@@ -120,6 +123,12 @@
 #define S5P_APLL_VAL_1000		((250 << 16) | (6 << 8) | 1)
 #define S5P_APLL_VAL_800		((200 << 16) | (6 << 8) | 1)
 
+#define S5P_EPLLCON0_ENABLE_SHIFT	(31)
+#define S5P_EPLLCON0_LOCKED_SHIFT	(29)
+
+#define S5P_VPLLCON0_ENABLE_SHIFT	(31)
+#define S5P_VPLLCON0_LOCKED_SHIFT	(29)
+
 #define S5P_CLKSRC_CPU_MUXCORE_SHIFT	(16)
 #define S5P_CLKMUX_STATCPU_MUXCORE_MASK	(0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
 
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index f4d52b5..b037fba 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -18,12 +18,15 @@
 #include <linux/suspend.h>
 #include <linux/syscore_ops.h>
 #include <linux/io.h>
+#include <linux/err.h>
+#include <linux/clk.h>
 
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
 
 #include <plat/cpu.h>
 #include <plat/pm.h>
+#include <plat/pll.h>
 
 #include <mach/regs-irq.h>
 #include <mach/regs-gpio.h>
@@ -45,16 +48,22 @@ static struct sleep_save exynos4_set_clksrc[] = {
 	{ .reg = S5P_CLKSRC_MASK_DMC			, .val = 0x00010000, },
 };
 
+static struct sleep_save exynos4_epll_save[] = {
+	SAVE_ITEM(S5P_EPLL_CON0),
+	SAVE_ITEM(S5P_EPLL_CON1),
+};
+
+static struct sleep_save exynos4_vpll_save[] = {
+	SAVE_ITEM(S5P_VPLL_CON0),
+	SAVE_ITEM(S5P_VPLL_CON1),
+};
+
 static struct sleep_save exynos4_core_save[] = {
 	/* CMU side */
 	SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
 	SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
 	SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
 	SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
-	SAVE_ITEM(S5P_EPLL_CON0),
-	SAVE_ITEM(S5P_EPLL_CON1),
-	SAVE_ITEM(S5P_VPLL_CON0),
-	SAVE_ITEM(S5P_VPLL_CON1),
 	SAVE_ITEM(S5P_CLKSRC_TOP0),
 	SAVE_ITEM(S5P_CLKSRC_TOP1),
 	SAVE_ITEM(S5P_CLKSRC_CAM),
@@ -260,6 +269,8 @@ static void exynos4_pm_prepare(void)
 
 	s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
 	s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
+	s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
+	s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
 
 	tmp = __raw_readl(S5P_INFORM1);
 
@@ -307,12 +318,80 @@ void exynos4_scu_enable(void __iomem *scu_base)
 	flush_cache_all();
 }
 
+static unsigned long pll_base_rate;
+
+static void exynos4_restore_pll(void)
+{
+	unsigned long pll_con, locktime, lockcnt;
+	unsigned long pll_in_rate;
+	unsigned int p_div, epll_wait = 0, vpll_wait = 0;
+
+	if (pll_base_rate == 0)
+		return;
+
+	pll_in_rate = pll_base_rate;
+
+	/* EPLL */
+	pll_con = exynos4_epll_save[0].val;
+
+	if (pll_con & (1 << 31)) {
+		pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT);
+		p_div = (pll_con >> PLL46XX_PDIV_SHIFT);
+
+		pll_in_rate /= 1000000;
+
+		locktime = (3000 / pll_in_rate) * p_div;
+		lockcnt = locktime * 10000 / (10000 / pll_in_rate);
+
+		__raw_writel(lockcnt, S5P_EPLL_LOCK);
+
+		s3c_pm_do_restore_core(exynos4_epll_save,
+					ARRAY_SIZE(exynos4_epll_save));
+		epll_wait = 1;
+	}
+
+	pll_in_rate = pll_base_rate;
+
+	/* VPLL */
+	pll_con = exynos4_vpll_save[0].val;
+
+	if (pll_con & (1 << 31)) {
+		pll_in_rate /= 1000000;
+		/* 750us */
+		locktime = 750;
+		lockcnt = locktime * 10000 / (10000 / pll_in_rate);
+
+		__raw_writel(lockcnt, S5P_VPLL_LOCK);
+
+		s3c_pm_do_restore_core(exynos4_vpll_save,
+					ARRAY_SIZE(exynos4_vpll_save));
+		vpll_wait = 1;
+	}
+
+	/* Wait PLL locking */
+
+	do {
+		if (epll_wait) {
+			pll_con = __raw_readl(S5P_EPLL_CON0);
+			if (pll_con & (1 << S5P_EPLLCON0_LOCKED_SHIFT))
+				epll_wait = 0;
+		}
+
+		if (vpll_wait) {
+			pll_con = __raw_readl(S5P_VPLL_CON0);
+			if (pll_con & (1 << S5P_VPLLCON0_LOCKED_SHIFT))
+				vpll_wait = 0;
+		}
+	} while (epll_wait || vpll_wait);
+}
+
 static struct sysdev_driver exynos4_pm_driver = {
 	.add		= exynos4_pm_add,
 };
 
 static __init int exynos4_pm_drvinit(void)
 {
+	struct clk *pll_base;
 	unsigned int tmp;
 
 	s3c_pm_init();
@@ -323,6 +402,13 @@ static __init int exynos4_pm_drvinit(void)
 	tmp |= ((0xFF << 8) | (0x1F << 1));
 	__raw_writel(tmp, S5P_WAKEUP_MASK);
 
+	pll_base = clk_get(NULL, "xtal");
+
+	if (!IS_ERR(pll_base)) {
+		pll_base_rate = clk_get_rate(pll_base);
+		clk_put(pll_base);
+	}
+
 	return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver);
 }
 arch_initcall(exynos4_pm_drvinit);
@@ -357,6 +443,8 @@ static void exynos4_pm_resume(void)
 
 	s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
 
+	exynos4_restore_pll();
+
 	exynos4_scu_enable(S5P_VA_SCU);
 
 #ifdef CONFIG_CACHE_L2X0
-- 
1.7.1

[PATCH 6/7] ARM: EXYNOS4: Add save/restore for more ARM registers

[Kukjin Kim]

From: Jaecheol Lee <jc.lee@samsung.com>

This patch adds save/restore for Power Control Register and
Diagnostic Register.

Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/mach-exynos4/sleep.S |   22 ++++++++++++++++++++++
 1 files changed, 22 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos4/sleep.S b/arch/arm/mach-exynos4/sleep.S
index d55d38c..4fe13fc 100644
--- a/arch/arm/mach-exynos4/sleep.S
+++ b/arch/arm/mach-exynos4/sleep.S
@@ -42,6 +42,15 @@
 ENTRY(s3c_cpu_save)
 
 	stmfd	sp!, { r3 - r12, lr }
+
+	adr	r0, sleep_save_misc
+
+	mrc	p15, 0, r2, c15, c0, 0	@ read power control register
+	str	r2, [r0], #4
+
+	mrc	p15, 0, r2, c15, c0, 1	@ read diagnostic register
+	str	r2, [r0], #4
+
 	ldr	r3, =resume_with_mmu
 	bl	cpu_suspend
 
@@ -56,6 +65,14 @@ ENTRY(s3c_cpu_save)
 	b	early_wakeup
 
 resume_with_mmu:
+	adr	r0, sleep_save_misc
+
+	ldr	r1, [r0], #4
+	mcr	p15, 0, r1, c15, c0, 0	@ write power control register
+
+	ldr	r1, [r0], #4
+	mcr	p15, 0, r1, c15, c0, 1	@ write diagnostic register
+
 	mov	r0, #1
 
 early_wakeup:
@@ -71,6 +88,11 @@ early_wakeup:
 
 	.word	0x2bedf00d
 
+	 /* To save more cpu register */
+sleep_save_misc:
+	.long	0
+	.long	0
+
 	/*
 	 * s3c_cpu_resume
 	 *
-- 
1.7.1

[PATCH 6/7] ARM: EXYNOS4: Add save/restore for more ARM registers

[Russell King - ARM Linux]

On Wed, Jun 22, 2011 at 05:46:44PM +0900, Kukjin Kim wrote:
> From: Jaecheol Lee <jc.lee@samsung.com>
> 
> This patch adds save/restore for Power Control Register and
> Diagnostic Register.

NAK.  Please see my further suspend consolidation patches posted earlier.
I've also recently (last few days) moved these further forward and this
code no longer exists in this file (all it contains is the early
resume stuff.)

My guess is that these two registers are samsung specific, and so they
should be saved and restored by higher level code (eg, a syscore_ops
for exynos4 specific stuff.)

[PATCH 6/7] ARM: EXYNOS4: Add save/restore for more ARM registers

[Kukjin Kim]

Russell King - ARM Linux wrote:
> 
> On Wed, Jun 22, 2011 at 05:46:44PM +0900, Kukjin Kim wrote:
> > From: Jaecheol Lee <jc.lee@samsung.com>
> >
> > This patch adds save/restore for Power Control Register and
> > Diagnostic Register.
> 
> NAK.  Please see my further suspend consolidation patches posted earlier.
> I've also recently (last few days) moved these further forward and this
> code no longer exists in this file (all it contains is the early
> resume stuff.)
> 
Oops :(
OK, will re-work based on latest rmk/for-next :)

> My guess is that these two registers are samsung specific, and so they
> should be saved and restored by higher level code (eg, a syscore_ops
> for exynos4 specific stuff.)

Let me think again.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH 6/7] ARM: EXYNOS4: Add save/restore for more ARM registers

[Russell King - ARM Linux]

On Thu, Jun 23, 2011 at 03:39:02PM +0900, Kukjin Kim wrote:
> Russell King - ARM Linux wrote:
> > 
> > On Wed, Jun 22, 2011 at 05:46:44PM +0900, Kukjin Kim wrote:
> > > From: Jaecheol Lee <jc.lee@samsung.com>
> > >
> > > This patch adds save/restore for Power Control Register and
> > > Diagnostic Register.
> > 
> > NAK.  Please see my further suspend consolidation patches posted earlier.
> > I've also recently (last few days) moved these further forward and this
> > code no longer exists in this file (all it contains is the early
> > resume stuff.)
> > 
> Oops :(
> OK, will re-work based on latest rmk/for-next :)

The entire series is not in for-next yet, it's still being worked on.
That's why I posted the patches again yesterday.

[PATCH 6/7] ARM: EXYNOS4: Add save/restore for more ARM registers

[Kukjin Kim]

Russell King - ARM Linux wrote:
> 
> On Thu, Jun 23, 2011 at 03:39:02PM +0900, Kukjin Kim wrote:
> > Russell King - ARM Linux wrote:
> > >
> > Oops :(
> > OK, will re-work based on latest rmk/for-next :)
> 
> The entire series is not in for-next yet, it's still being worked on.
> That's why I posted the patches again yesterday.

OK, first of all, will test your yesterday patches on Samsung boards then
will re-work this based on it.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH 7/7] ARM: EXYNOS4: Move S5P_CENTRAL_SEQ_CONFIGURATION setting for PM

[Kukjin Kim]

From: Jaecheol Lee <jc.lee@samsung.com>

We need to balance between set and check S5P_CENTRAL_SEQ_CONFIGURATION
register in syscore_ops suspend/resume function when failure in enter
suspend mode. Moved this register setting for PM for the purpose of balancing.

Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
---
 arch/arm/mach-exynos4/pm.c |   22 ++++++++++++++--------
 1 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index b037fba..a103c13 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -249,14 +249,6 @@ static struct sleep_save exynos4_l2cc_save[] = {
 
 void exynos4_cpu_suspend(void)
 {
-	unsigned long tmp;
-
-	/* Setting Central Sequence Register for power down mode */
-
-	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
-	tmp &= ~(S5P_CENTRAL_LOWPWR_CFG);
-	__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
-
 	outer_flush_all();
 
 	/* issue the standby signal into the pm unit. */
@@ -413,6 +405,19 @@ static __init int exynos4_pm_drvinit(void)
 }
 arch_initcall(exynos4_pm_drvinit);
 
+static int exynos4_pm_suspend(void)
+{
+	unsigned long tmp;
+
+	/* Setting Central Sequence Register for power down mode */
+
+	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+	tmp &= ~(S5P_CENTRAL_LOWPWR_CFG);
+	__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+
+	return 0;
+}
+
 static void exynos4_pm_resume(void)
 {
 	unsigned long tmp;
@@ -459,6 +464,7 @@ early_wakeup:
 }
 
 static struct syscore_ops exynos4_pm_syscore_ops = {
+	.suspend	= exynos4_pm_suspend,
 	.resume		= exynos4_pm_resume,
 };
 
-- 
1.7.1

[PATCH 7/7] ARM: EXYNOS4: Move S5P_CENTRAL_SEQ_CONFIGURATION setting for PM

[Sergei Shtylyov]

Hello.

On 22-06-2011 12:46, Kukjin Kim wrote:

> From: Jaecheol Lee<jc.lee@samsung.com>

> We need to balance between set and check S5P_CENTRAL_SEQ_CONFIGURATION
> register in syscore_ops suspend/resume function when failure in enter
> suspend mode. Moved this register setting for PM for the purpose of balancing.

> Signed-off-by: Jaecheol Lee<jc.lee@samsung.com>
> Signed-off-by: Kukjin Kim<kgene.kim@samsung.com>
> ---
>   arch/arm/mach-exynos4/pm.c |   22 ++++++++++++++--------
>   1 files changed, 14 insertions(+), 8 deletions(-)

> diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
> index b037fba..a103c13 100644
> --- a/arch/arm/mach-exynos4/pm.c
> +++ b/arch/arm/mach-exynos4/pm.c
[...]
> @@ -413,6 +405,19 @@ static __init int exynos4_pm_drvinit(void)
>   }
>   arch_initcall(exynos4_pm_drvinit);
>
> +static int exynos4_pm_suspend(void)
> +{
> +	unsigned long tmp;
> +
> +	/* Setting Central Sequence Register for power down mode */
> +
> +	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
> +	tmp &= ~(S5P_CENTRAL_LOWPWR_CFG);

    Could drop useless parens, while at it.

WBR, Sergei

[PATCH 7/7] ARM: EXYNOS4: Move S5P_CENTRAL_SEQ_CONFIGURATION setting for PM

[Kukjin Kim]

Sergei Shtylyov wrote:
> 
> Hello.
> 
Hi :)

> On 22-06-2011 12:46, Kukjin Kim wrote:
> 
> > From: Jaecheol Lee<jc.lee@samsung.com>
> 
> > We need to balance between set and check
> S5P_CENTRAL_SEQ_CONFIGURATION
> > register in syscore_ops suspend/resume function when failure in enter
> > suspend mode. Moved this register setting for PM for the purpose of
balancing.
> 
> > Signed-off-by: Jaecheol Lee<jc.lee@samsung.com>
> > Signed-off-by: Kukjin Kim<kgene.kim@samsung.com>
> > ---
> >   arch/arm/mach-exynos4/pm.c |   22 ++++++++++++++--------
> >   1 files changed, 14 insertions(+), 8 deletions(-)
> 
> > diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
> > index b037fba..a103c13 100644
> > --- a/arch/arm/mach-exynos4/pm.c
> > +++ b/arch/arm/mach-exynos4/pm.c
> [...]
> > @@ -413,6 +405,19 @@ static __init int exynos4_pm_drvinit(void)
> >   }
> >   arch_initcall(exynos4_pm_drvinit);
> >
> > +static int exynos4_pm_suspend(void)
> > +{
> > +	unsigned long tmp;
> > +
> > +	/* Setting Central Sequence Register for power down mode */
> > +
> > +	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
> > +	tmp &= ~(S5P_CENTRAL_LOWPWR_CFG);
> 
>     Could drop useless parens, while at it.
> 
Sergei, thanks ;)

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.