[PATCH v4 0/5] Add support to enable ARM PMU for EXYNOS

[PATCH v4 0/5] Add support to enable ARM PMU for EXYNOS

[Chanho Park]

This patchset fixes irq numbers of ARM Performance Monitoring unit and enable
it for Perf(Performance Counter) on the exynos 4 and 5. The exynos4 and 5 have 2
more cpu cores which has its own pmu.

The exynos uses combiner-irq type for arm-pmu. Especially, the exynos4412 has 4
extra combined irq groups. So, we need to change a max combiner number and to
retreive it according to each soc types.

To enable perf, we need also to implement a set_irq_affinity function for the
combiner-irq. After applying this patch, we can use the perf for the exynos
machine.

Changes from v3:
 - Define max_combiner_nr according to soc types
 - Add armpmu dt binding for exynos4210
 - Clean up soc types comparison from v2

Changes from v2:
 - Convert to dt binding of exynos5250

Changes from v1:
 - Split arm-pmu init of exynos from plat-samsung
 - Correct combined irqs of exynos4412
 - Use soc_is_xxx function instead of CONFIG_XXX to identify dynamically

Chanho Park (5):
  ARM: EXYNOS: Add set_irq_affinity function for combiner_irq
  ARM: EXYNOS: Correct combined IRQs for exynos4
  ARM: EXYNOS: Enable PMUs for exynos4
  ARM: EXYNOS: Add arm-pmu DT binding for exynos5250
  ARM: EXYNOS: Add arm-pmu DT binding for exynos421x

 arch/arm/boot/dts/exynos4210.dtsi        |    6 ++
 arch/arm/boot/dts/exynos5250.dtsi        |    6 ++
 arch/arm/mach-exynos/common.c            |  100 ++++++++++++++++++++++++++----
 arch/arm/mach-exynos/include/mach/irqs.h |   12 +++-
 arch/arm/plat-samsung/devs.c             |    2 +-
 5 files changed, 111 insertions(+), 15 deletions(-)

-- 
1.7.9.5

[PATCH v4 1/5] ARM: EXYNOS: Add set_irq_affinity function for combiner_irq

[Chanho Park]

This patch adds set_irq_affinity function for combiner_irq. We need this
function to enable a arm-pmu because the pmu of exynos has combined type irqs.

Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/mach-exynos/common.c |   30 +++++++++++++++++++++++++-----
 1 file changed, 25 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 715b690..709245e 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -405,6 +405,7 @@ struct combiner_chip_data {
 	unsigned int irq_offset;
 	unsigned int irq_mask;
 	void __iomem *base;
+	unsigned int parent_irq;
 };
 
 static struct irq_domain *combiner_irq_domain;
@@ -461,10 +462,28 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 	chained_irq_exit(chip, desc);
 }
 
+#ifdef CONFIG_SMP
+static int combiner_set_affinity(struct irq_data *d,
+				 const struct cpumask *mask_val, bool force)
+{
+	struct combiner_chip_data *chip_data = irq_data_get_irq_chip_data(d);
+	struct irq_chip *chip = irq_get_chip(chip_data->parent_irq);
+	struct irq_data *data = irq_get_irq_data(chip_data->parent_irq);
+
+	if (chip && chip->irq_set_affinity)
+		return chip->irq_set_affinity(data, mask_val, force);
+	else
+		return -EINVAL;
+}
+#endif
+
 static struct irq_chip combiner_chip = {
-	.name		= "COMBINER",
-	.irq_mask	= combiner_mask_irq,
-	.irq_unmask	= combiner_unmask_irq,
+	.name			= "COMBINER",
+	.irq_mask		= combiner_mask_irq,
+	.irq_unmask		= combiner_unmask_irq,
+#ifdef CONFIG_SMP
+	.irq_set_affinity	= combiner_set_affinity,
+#endif
 };
 
 static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
@@ -484,12 +503,13 @@ static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int i
 }
 
 static void __init combiner_init_one(unsigned int combiner_nr,
-				     void __iomem *base)
+				     void __iomem *base, unsigned int irq)
 {
 	combiner_data[combiner_nr].base = base;
 	combiner_data[combiner_nr].irq_offset = irq_find_mapping(
 		combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
 	combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
+	combiner_data[combiner_nr].parent_irq = irq;
 
 	/* Disable all interrupts */
 	__raw_writel(combiner_data[combiner_nr].irq_mask,
@@ -573,12 +593,12 @@ static void __init combiner_init(void __iomem *combiner_base,
 	}
 
 	for (i = 0; i < max_nr; i++) {
-		combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
 		irq = IRQ_SPI(i);
 #ifdef CONFIG_OF
 		if (np)
 			irq = irq_of_parse_and_map(np, i);
 #endif
+		combiner_init_one(i, combiner_base + (i >> 2) * 0x10, irq);
 		combiner_cascade_irq(i, irq);
 	}
 }
-- 
1.7.9.5

[PATCH v4 1/5] ARM: EXYNOS: Add set_irq_affinity function for combiner_irq

[Kukjin Kim]

Chanho Park wrote:
> 
> This patch adds set_irq_affinity function for combiner_irq. We need this
> function to enable a arm-pmu because the pmu of exynos has combined type
> irqs.
> 
> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
>  arch/arm/mach-exynos/common.c |   30 +++++++++++++++++++++++++-----
>  1 file changed, 25 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
> index 715b690..709245e 100644
> --- a/arch/arm/mach-exynos/common.c
> +++ b/arch/arm/mach-exynos/common.c
> @@ -405,6 +405,7 @@ struct combiner_chip_data {
>  	unsigned int irq_offset;
>  	unsigned int irq_mask;
>  	void __iomem *base;
> +	unsigned int parent_irq;
>  };
> 
>  static struct irq_domain *combiner_irq_domain;
> @@ -461,10 +462,28 @@ static void combiner_handle_cascade_irq(unsigned int
> irq, struct irq_desc *desc)
>  	chained_irq_exit(chip, desc);
>  }
> 
> +#ifdef CONFIG_SMP
> +static int combiner_set_affinity(struct irq_data *d,
> +				 const struct cpumask *mask_val, bool force)
> +{
> +	struct combiner_chip_data *chip_data =
> irq_data_get_irq_chip_data(d);
> +	struct irq_chip *chip = irq_get_chip(chip_data->parent_irq);
> +	struct irq_data *data = irq_get_irq_data(chip_data->parent_irq);
> +
> +	if (chip && chip->irq_set_affinity)
> +		return chip->irq_set_affinity(data, mask_val, force);
> +	else
> +		return -EINVAL;
> +}
> +#endif
> +
>  static struct irq_chip combiner_chip = {
> -	.name		= "COMBINER",
> -	.irq_mask	= combiner_mask_irq,
> -	.irq_unmask	= combiner_unmask_irq,
> +	.name			= "COMBINER",
> +	.irq_mask		= combiner_mask_irq,
> +	.irq_unmask		= combiner_unmask_irq,
> +#ifdef CONFIG_SMP
> +	.irq_set_affinity	= combiner_set_affinity,
> +#endif
>  };
> 
>  static void __init combiner_cascade_irq(unsigned int combiner_nr,
> unsigned int irq)
> @@ -484,12 +503,13 @@ static void __init combiner_cascade_irq(unsigned int
> combiner_nr, unsigned int i
>  }
> 
>  static void __init combiner_init_one(unsigned int combiner_nr,
> -				     void __iomem *base)
> +				     void __iomem *base, unsigned int irq)
>  {
>  	combiner_data[combiner_nr].base = base;
>  	combiner_data[combiner_nr].irq_offset = irq_find_mapping(
>  		combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
>  	combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) <<
> 3);
> +	combiner_data[combiner_nr].parent_irq = irq;
> 
>  	/* Disable all interrupts */
>  	__raw_writel(combiner_data[combiner_nr].irq_mask,
> @@ -573,12 +593,12 @@ static void __init combiner_init(void __iomem
> *combiner_base,
>  	}
> 
>  	for (i = 0; i < max_nr; i++) {
> -		combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
>  		irq = IRQ_SPI(i);
>  #ifdef CONFIG_OF
>  		if (np)
>  			irq = irq_of_parse_and_map(np, i);
>  #endif
> +		combiner_init_one(i, combiner_base + (i >> 2) * 0x10, irq);
>  		combiner_cascade_irq(i, irq);
>  	}
>  }
> --
> 1.7.9.5

Looks good to me, applied.
Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH v4 2/5] ARM: EXYNOS: Correct combined IRQs for exynos4

[Chanho Park]

This patch corrects combined IRQs for exynos4 series platform. The exynos4412
has four extra combined irq group and the exynos4212 has two more combined irqs
than exynos4210. Each irq is mapped to IRQ_SPI(xx). Unfortunately, extra 4
combined IRQs isn't sequential. So, we need to map the irqs manually.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/mach-exynos/common.c            |   42 +++++++++++++++++++++++++-----
 arch/arm/mach-exynos/include/mach/irqs.h |    4 ++-
 2 files changed, 39 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 709245e..fdd582a 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -560,23 +560,50 @@ static struct irq_domain_ops combiner_irq_domain_ops = {
 	.map	= combiner_irq_domain_map,
 };
 
+static unsigned int combiner_extra_irq(int group)
+{
+	switch (group) {
+	case 16:
+		return IRQ_SPI(107);
+	case 17:
+		return IRQ_SPI(108);
+	case 18:
+		return IRQ_SPI(48);
+	case 19:
+		return IRQ_SPI(42);
+	default:
+		return 0;
+	}
+}
+
+static unsigned int max_combiner_nr(void)
+{
+	if (soc_is_exynos5250())
+		return EXYNOS5_MAX_COMBINER_NR;
+	else if (soc_is_exynos4412())
+		return EXYNOS4_MAX_COMBINER_NR;
+	else if (soc_is_exynos4212())
+		return EXYNOS4212_MAX_COMBINER_NR;
+	else
+		return EXYNOS4210_MAX_COMBINER_NR;
+}
+
 static void __init combiner_init(void __iomem *combiner_base,
 				 struct device_node *np)
 {
 	int i, irq, irq_base;
 	unsigned int max_nr, nr_irq;
 
+	max_nr = max_combiner_nr();
+
 	if (np) {
 		if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
 			pr_warning("%s: number of combiners not specified, "
 				"setting default as %d.\n",
-				__func__, EXYNOS4_MAX_COMBINER_NR);
-			max_nr = EXYNOS4_MAX_COMBINER_NR;
+				__func__, max_nr);
 		}
-	} else {
-		max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
-						EXYNOS4_MAX_COMBINER_NR;
 	}
+
 	nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
 
 	irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
@@ -593,7 +620,10 @@ static void __init combiner_init(void __iomem *combiner_base,
 	}
 
 	for (i = 0; i < max_nr; i++) {
-		irq = IRQ_SPI(i);
+		if (i < EXYNOS4210_MAX_COMBINER_NR || soc_is_exynos5250())
+			irq = IRQ_SPI(i);
+		else
+			irq = combiner_extra_irq(i);
 #ifdef CONFIG_OF
 		if (np)
 			irq = irq_of_parse_and_map(np, i);
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 35bced6..3a83546 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -165,7 +165,9 @@
 #define EXYNOS4_IRQ_FIMD0_VSYNC		COMBINER_IRQ(11, 1)
 #define EXYNOS4_IRQ_FIMD0_SYSTEM	COMBINER_IRQ(11, 2)
 
-#define EXYNOS4_MAX_COMBINER_NR		16
+#define EXYNOS4210_MAX_COMBINER_NR	16
+#define EXYNOS4212_MAX_COMBINER_NR	18
+#define EXYNOS4_MAX_COMBINER_NR		20
 
 #define EXYNOS4_IRQ_GPIO1_NR_GROUPS	16
 #define EXYNOS4_IRQ_GPIO2_NR_GROUPS	9
-- 
1.7.9.5

[PATCH v4 2/5] ARM: EXYNOS: Correct combined IRQs for exynos4

[Kukjin Kim]

Chanho Park wrote:
> 
> This patch corrects combined IRQs for exynos4 series platform. The
> exynos4412
> has four extra combined irq group and the exynos4212 has two more combined
> irqs
> than exynos4210. Each irq is mapped to IRQ_SPI(xx). Unfortunately, extra 4
> combined IRQs isn't sequential. So, we need to map the irqs manually.
> 
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
>  arch/arm/mach-exynos/common.c            |   42
+++++++++++++++++++++++++----
> -
>  arch/arm/mach-exynos/include/mach/irqs.h |    4 ++-
>  2 files changed, 39 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
> index 709245e..fdd582a 100644
> --- a/arch/arm/mach-exynos/common.c
> +++ b/arch/arm/mach-exynos/common.c
> @@ -560,23 +560,50 @@ static struct irq_domain_ops combiner_irq_domain_ops
> = {
>  	.map	= combiner_irq_domain_map,
>  };
> 
> +static unsigned int combiner_extra_irq(int group)

This is only for exynos4212 and exynos4412 so how about to use
exynos4x12_combiner_extra_irq()?

> +{
> +	switch (group) {
> +	case 16:
> +		return IRQ_SPI(107);
> +	case 17:
> +		return IRQ_SPI(108);
> +	case 18:
> +		return IRQ_SPI(48);
> +	case 19:
> +		return IRQ_SPI(42);
> +	default:
> +		return 0;
> +	}
> +}
> +
> +static unsigned int max_combiner_nr(void)
> +{
> +	if (soc_is_exynos5250())
> +		return EXYNOS5_MAX_COMBINER_NR;
> +	else if (soc_is_exynos4412())
> +		return EXYNOS4_MAX_COMBINER_NR;

EXYNOS4412_MAX_COMBINER_NR is more clear?

> +	else if (soc_is_exynos4212())
> +		return EXYNOS4212_MAX_COMBINER_NR;
> +	else
> +		return EXYNOS4210_MAX_COMBINER_NR;
> +}
> +
>  static void __init combiner_init(void __iomem *combiner_base,
>  				 struct device_node *np)
>  {
>  	int i, irq, irq_base;
>  	unsigned int max_nr, nr_irq;
> 
> +	max_nr = max_combiner_nr();
> +
>  	if (np) {
>  		if (of_property_read_u32(np, "samsung,combiner-nr",
&max_nr))
> {
>  			pr_warning("%s: number of combiners not specified, "

Hmm...the message should be changed, because it is just defined by checking
SoC with this changes not property of device tree...So how about just using
pr_info() with proper message?

>  				"setting default as %d.\n",
> -				__func__, EXYNOS4_MAX_COMBINER_NR);
> -			max_nr = EXYNOS4_MAX_COMBINER_NR;
> +				__func__, max_nr);
>  		}
> -	} else {
> -		max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
> -						EXYNOS4_MAX_COMBINER_NR;
>  	}
> +
>  	nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
> 
>  	irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
> @@ -593,7 +620,10 @@ static void __init combiner_init(void __iomem
> *combiner_base,
>  	}
> 
>  	for (i = 0; i < max_nr; i++) {
> -		irq = IRQ_SPI(i);
> +		if (i < EXYNOS4210_MAX_COMBINER_NR || soc_is_exynos5250())
> +			irq = IRQ_SPI(i);
> +		else
> +			irq = combiner_extra_irq(i);
>  #ifdef CONFIG_OF
>  		if (np)
>  			irq = irq_of_parse_and_map(np, i);
> diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-
> exynos/include/mach/irqs.h
> index 35bced6..3a83546 100644
> --- a/arch/arm/mach-exynos/include/mach/irqs.h
> +++ b/arch/arm/mach-exynos/include/mach/irqs.h
> @@ -165,7 +165,9 @@
>  #define EXYNOS4_IRQ_FIMD0_VSYNC		COMBINER_IRQ(11, 1)
>  #define EXYNOS4_IRQ_FIMD0_SYSTEM	COMBINER_IRQ(11, 2)
> 
> -#define EXYNOS4_MAX_COMBINER_NR		16
> +#define EXYNOS4210_MAX_COMBINER_NR	16
> +#define EXYNOS4212_MAX_COMBINER_NR	18
> +#define EXYNOS4_MAX_COMBINER_NR		20

EXYNOS4412_MAX_COMBINER_NR ?

> 
>  #define EXYNOS4_IRQ_GPIO1_NR_GROUPS	16
>  #define EXYNOS4_IRQ_GPIO2_NR_GROUPS	9
> --
> 1.7.9.5



Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH v4 2/5] ARM: EXYNOS: Correct combined IRQs for exynos4

[Chanho Park]

> -----Original Message-----
> From: linux-arm-kernel-bounces at lists.infradead.org [mailto:linux-arm-
> kernel-bounces at lists.infradead.org] On Behalf Of Kukjin Kim
> Sent: Tuesday, October 23, 2012 10:59 PM
> To: 'Chanho Park'; ben-linux at fluff.org; linux-arm-kernel at lists.infradead.org;
> linux-samsung-soc at vger.kernel.org
> Cc: sachin.kamat at linaro.org; will.deacon at arm.com;
> kyungmin.park at samsung.com; linux at arm.linux.org.uk;
> thomas.abraham at linaro.org
> Subject: RE: [PATCH v4 2/5] ARM: EXYNOS: Correct combined IRQs for
> exynos4
> 
> Chanho Park wrote:
> >
> > This patch corrects combined IRQs for exynos4 series platform. The
> > exynos4412
> > has four extra combined irq group and the exynos4212 has two more
> > combined irqs than exynos4210. Each irq is mapped to IRQ_SPI(xx).
> > Unfortunately, extra 4 combined IRQs isn't sequential. So, we need to
> > map the irqs manually.
> >
> > Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> > ---
> >  arch/arm/mach-exynos/common.c            |   42
> +++++++++++++++++++++++++----
> > -
> >  arch/arm/mach-exynos/include/mach/irqs.h |    4 ++-
> >  2 files changed, 39 insertions(+), 7 deletions(-)
> >
> > diff --git a/arch/arm/mach-exynos/common.c
> > b/arch/arm/mach-exynos/common.c index 709245e..fdd582a 100644
> > --- a/arch/arm/mach-exynos/common.c
> > +++ b/arch/arm/mach-exynos/common.c
> > @@ -560,23 +560,50 @@ static struct irq_domain_ops
> > combiner_irq_domain_ops = {
> >  	.map	= combiner_irq_domain_map,
> >  };
> >
> > +static unsigned int combiner_extra_irq(int group)
> 
> This is only for exynos4212 and exynos4412 so how about to use
> exynos4x12_combiner_extra_irq()?

I agree with you. I'll change it in next patchset.

> 
> > +{
> > +	switch (group) {
> > +	case 16:
> > +		return IRQ_SPI(107);
> > +	case 17:
> > +		return IRQ_SPI(108);
> > +	case 18:
> > +		return IRQ_SPI(48);
> > +	case 19:
> > +		return IRQ_SPI(42);
> > +	default:
> > +		return 0;
> > +	}
> > +}
> > +
> > +static unsigned int max_combiner_nr(void) {
> > +	if (soc_is_exynos5250())
> > +		return EXYNOS5_MAX_COMBINER_NR;
> > +	else if (soc_is_exynos4412())
> > +		return EXYNOS4_MAX_COMBINER_NR;
> 
> EXYNOS4412_MAX_COMBINER_NR is more clear?

EXYNOS4_MAX_COMBINER_NR is defined for MAX_COMBINER_NR which determines maximum combined irq number.
In this situation, EXYNOS4_MAX_COMBINER_NR is more clear than EXYNOS4412_xx.
How about this? I think it's more clearer in all cases.

-#define EXYNOS4_MAX_COMBINER_NR		16
+#define EXYNOS4210_MAX_COMBINER_NR		16
+#define EXYNOS4212_MAX_COMBINER_NR		18
+#define EXYNOS4412_MAX_COMBINER_NR		20
+#define EXYNOS4_MAX_COMBINER_NR		EXYNOS4412_MAX_COMBINER_NR

> 
> > +	else if (soc_is_exynos4212())
> > +		return EXYNOS4212_MAX_COMBINER_NR;
> > +	else
> > +		return EXYNOS4210_MAX_COMBINER_NR;
> > +}
> > +
> >  static void __init combiner_init(void __iomem *combiner_base,
> >  				 struct device_node *np)
> >  {
> >  	int i, irq, irq_base;
> >  	unsigned int max_nr, nr_irq;
> >
> > +	max_nr = max_combiner_nr();
> > +
> >  	if (np) {
> >  		if (of_property_read_u32(np, "samsung,combiner-nr",
> &max_nr))
> > {
> >  			pr_warning("%s: number of combiners not specified,
> "
> 
> Hmm...the message should be changed, because it is just defined by
> checking SoC with this changes not property of device tree...So how about
> just using
> pr_info() with proper message?

I agree with you. I'll fix it.

> 
> >  				"setting default as %d.\n",
> > -				__func__, EXYNOS4_MAX_COMBINER_NR);
> > -			max_nr = EXYNOS4_MAX_COMBINER_NR;
> > +				__func__, max_nr);
> >  		}
> > -	} else {
> > -		max_nr = soc_is_exynos5250() ?
> EXYNOS5_MAX_COMBINER_NR :
> > -
> 	EXYNOS4_MAX_COMBINER_NR;
> >  	}
> > +
> >  	nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
> >
> >  	irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0); @@
> > -593,7 +620,10 @@ static void __init combiner_init(void __iomem
> > *combiner_base,
> >  	}
> >
> >  	for (i = 0; i < max_nr; i++) {
> > -		irq = IRQ_SPI(i);
> > +		if (i < EXYNOS4210_MAX_COMBINER_NR ||
> soc_is_exynos5250())
> > +			irq = IRQ_SPI(i);
> > +		else
> > +			irq = combiner_extra_irq(i);
> >  #ifdef CONFIG_OF
> >  		if (np)
> >  			irq = irq_of_parse_and_map(np, i); diff --git
> > a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-
> > exynos/include/mach/irqs.h index 35bced6..3a83546 100644
> > --- a/arch/arm/mach-exynos/include/mach/irqs.h
> > +++ b/arch/arm/mach-exynos/include/mach/irqs.h
> > @@ -165,7 +165,9 @@
> >  #define EXYNOS4_IRQ_FIMD0_VSYNC		COMBINER_IRQ(11, 1)
> >  #define EXYNOS4_IRQ_FIMD0_SYSTEM	COMBINER_IRQ(11, 2)
> >
> > -#define EXYNOS4_MAX_COMBINER_NR		16
> > +#define EXYNOS4210_MAX_COMBINER_NR	16
> > +#define EXYNOS4212_MAX_COMBINER_NR	18
> > +#define EXYNOS4_MAX_COMBINER_NR		20
> 
> EXYNOS4412_MAX_COMBINER_NR ?
> 
> >
> >  #define EXYNOS4_IRQ_GPIO1_NR_GROUPS	16
> >  #define EXYNOS4_IRQ_GPIO2_NR_GROUPS	9
> > --
> > 1.7.9.5
> 
> 
> 
> Thanks.
> 
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer, SW Solution
> Development Team, Samsung Electronics Co., Ltd.
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v4 3/5] ARM: EXYNOS: Enable PMUs for exynos4

[Chanho Park]

This patch defines irq numbers of ARM performance monitoring unit for exynos4.
Firs of all, we need to fix IRQ_PMU correctly and to split pmu initialization
of exynos from plat-samsung for easily defining it.

The number of CPU cores and PMU irq numbers are vary according to soc types.
So, we need to identify each soc type using soc_is_xxx function and to define
the pmu irqs dynamically. For example, the exynos4412 has 4 cpu cores and pmus.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/mach-exynos/common.c            |   28 ++++++++++++++++++++++++++++
 arch/arm/mach-exynos/include/mach/irqs.h |    8 ++++++--
 arch/arm/plat-samsung/devs.c             |    2 +-
 3 files changed, 35 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index fdd582a..5183426 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -35,6 +35,7 @@
 #include <mach/regs-pmu.h>
 #include <mach/regs-gpio.h>
 #include <mach/pmu.h>
+#include <mach/irqs.h>
 
 #include <plat/cpu.h>
 #include <plat/clock.h>
@@ -1093,3 +1094,30 @@ static int __init exynos_init_irq_eint(void)
 	return 0;
 }
 arch_initcall(exynos_init_irq_eint);
+
+static struct resource exynos4_pmu_resource[] = {
+	DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
+	DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
+#if defined(CONFIG_SOC_EXYNOS4412)
+	DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2),
+	DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3),
+#endif
+};
+
+static struct platform_device exynos4_device_pmu = {
+	.name		= "arm-pmu",
+	.num_resources	= ARRAY_SIZE(exynos4_pmu_resource),
+	.resource	= exynos4_pmu_resource,
+};
+
+static int __init exynos_armpmu_init(void)
+{
+	if (!of_have_populated_dt()) {
+		if (soc_is_exynos4210() || soc_is_exynos4212())
+			exynos4_device_pmu.num_resources = 2;
+		platform_device_register(&exynos4_device_pmu);
+	}
+
+	return 0;
+}
+arch_initcall(exynos_armpmu_init);
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 3a83546..c67a54e 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -128,7 +128,7 @@
 #define EXYNOS4_IRQ_ADC1		IRQ_SPI(107)
 #define EXYNOS4_IRQ_PEN1		IRQ_SPI(108)
 #define EXYNOS4_IRQ_KEYPAD		IRQ_SPI(109)
-#define EXYNOS4_IRQ_PMU			IRQ_SPI(110)
+#define EXYNOS4_IRQ_POWER_PMU		IRQ_SPI(110)
 #define EXYNOS4_IRQ_GPS			IRQ_SPI(111)
 #define EXYNOS4_IRQ_INTFEEDCTRL_SSS	IRQ_SPI(112)
 #define EXYNOS4_IRQ_SLIMBUS		IRQ_SPI(113)
@@ -136,6 +136,11 @@
 #define EXYNOS4_IRQ_TSI			IRQ_SPI(115)
 #define EXYNOS4_IRQ_SATA		IRQ_SPI(116)
 
+#define EXYNOS4_IRQ_PMU			COMBINER_IRQ(2, 2)
+#define EXYNOS4_IRQ_PMU_CPU1		COMBINER_IRQ(3, 2)
+#define EXYNOS4_IRQ_PMU_CPU2		COMBINER_IRQ(18, 2)
+#define EXYNOS4_IRQ_PMU_CPU3		COMBINER_IRQ(19, 2)
+
 #define EXYNOS4_IRQ_SYSMMU_MDMA0_0	COMBINER_IRQ(4, 0)
 #define EXYNOS4_IRQ_SYSMMU_SSS_0	COMBINER_IRQ(4, 1)
 #define EXYNOS4_IRQ_SYSMMU_FIMC0_0	COMBINER_IRQ(4, 2)
@@ -232,7 +237,6 @@
 #define IRQ_TC				EXYNOS4_IRQ_PEN0
 
 #define IRQ_KEYPAD			EXYNOS4_IRQ_KEYPAD
-#define IRQ_PMU				EXYNOS4_IRQ_PMU
 
 #define IRQ_FIMD0_FIFO			EXYNOS4_IRQ_FIMD0_FIFO
 #define IRQ_FIMD0_VSYNC			EXYNOS4_IRQ_FIMD0_VSYNC
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 03f654d..ace76b4 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -1125,7 +1125,7 @@ struct platform_device s5p_device_onenand = {
 
 /* PMU */
 
-#ifdef CONFIG_PLAT_S5P
+#if defined(CONFIG_PLAT_S5P) && !defined(CONFIG_ARCH_EXYNOS)
 static struct resource s5p_pmu_resource[] = {
 	DEFINE_RES_IRQ(IRQ_PMU)
 };
-- 
1.7.9.5

[PATCH v4 3/5] ARM: EXYNOS: Enable PMUs for exynos4

[Kukjin Kim]

Chanho Park wrote:
> 
> This patch defines irq numbers of ARM performance monitoring unit for
> exynos4.
> Firs of all, we need to fix IRQ_PMU correctly and to split pmu
> initialization
> of exynos from plat-samsung for easily defining it.
> 
> The number of CPU cores and PMU irq numbers are vary according to soc
> types.
> So, we need to identify each soc type using soc_is_xxx function and to
> define
> the pmu irqs dynamically. For example, the exynos4412 has 4 cpu cores and
> pmus.
> 
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
>  arch/arm/mach-exynos/common.c            |   28
++++++++++++++++++++++++++++
>  arch/arm/mach-exynos/include/mach/irqs.h |    8 ++++++--
>  arch/arm/plat-samsung/devs.c             |    2 +-
>  3 files changed, 35 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
> index fdd582a..5183426 100644
> --- a/arch/arm/mach-exynos/common.c
> +++ b/arch/arm/mach-exynos/common.c
> @@ -35,6 +35,7 @@
>  #include <mach/regs-pmu.h>
>  #include <mach/regs-gpio.h>
>  #include <mach/pmu.h>
> +#include <mach/irqs.h>
> 
>  #include <plat/cpu.h>
>  #include <plat/clock.h>
> @@ -1093,3 +1094,30 @@ static int __init exynos_init_irq_eint(void)
>  	return 0;
>  }
>  arch_initcall(exynos_init_irq_eint);
> +
> +static struct resource exynos4_pmu_resource[] = {
> +	DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
> +	DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
> +#if defined(CONFIG_SOC_EXYNOS4412)
> +	DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2),
> +	DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3),
> +#endif
> +};
> +
> +static struct platform_device exynos4_device_pmu = {
> +	.name		= "arm-pmu",
> +	.num_resources	= ARRAY_SIZE(exynos4_pmu_resource),
> +	.resource	= exynos4_pmu_resource,
> +};
> +
> +static int __init exynos_armpmu_init(void)
> +{
> +	if (!of_have_populated_dt()) {
> +		if (soc_is_exynos4210() || soc_is_exynos4212())
> +			exynos4_device_pmu.num_resources = 2;
> +		platform_device_register(&exynos4_device_pmu);
> +	}
> +
> +	return 0;
> +}
> +arch_initcall(exynos_armpmu_init);
> diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-
> exynos/include/mach/irqs.h
> index 3a83546..c67a54e 100644
> --- a/arch/arm/mach-exynos/include/mach/irqs.h
> +++ b/arch/arm/mach-exynos/include/mach/irqs.h
> @@ -128,7 +128,7 @@
>  #define EXYNOS4_IRQ_ADC1		IRQ_SPI(107)
>  #define EXYNOS4_IRQ_PEN1		IRQ_SPI(108)
>  #define EXYNOS4_IRQ_KEYPAD		IRQ_SPI(109)
> -#define EXYNOS4_IRQ_PMU			IRQ_SPI(110)
> +#define EXYNOS4_IRQ_POWER_PMU		IRQ_SPI(110)
>  #define EXYNOS4_IRQ_GPS			IRQ_SPI(111)
>  #define EXYNOS4_IRQ_INTFEEDCTRL_SSS	IRQ_SPI(112)
>  #define EXYNOS4_IRQ_SLIMBUS		IRQ_SPI(113)
> @@ -136,6 +136,11 @@
>  #define EXYNOS4_IRQ_TSI			IRQ_SPI(115)
>  #define EXYNOS4_IRQ_SATA		IRQ_SPI(116)
> 
> +#define EXYNOS4_IRQ_PMU			COMBINER_IRQ(2, 2)
> +#define EXYNOS4_IRQ_PMU_CPU1		COMBINER_IRQ(3, 2)
> +#define EXYNOS4_IRQ_PMU_CPU2		COMBINER_IRQ(18, 2)
> +#define EXYNOS4_IRQ_PMU_CPU3		COMBINER_IRQ(19, 2)
> +
>  #define EXYNOS4_IRQ_SYSMMU_MDMA0_0	COMBINER_IRQ(4, 0)
>  #define EXYNOS4_IRQ_SYSMMU_SSS_0	COMBINER_IRQ(4, 1)
>  #define EXYNOS4_IRQ_SYSMMU_FIMC0_0	COMBINER_IRQ(4, 2)
> @@ -232,7 +237,6 @@
>  #define IRQ_TC				EXYNOS4_IRQ_PEN0
> 
>  #define IRQ_KEYPAD			EXYNOS4_IRQ_KEYPAD
> -#define IRQ_PMU				EXYNOS4_IRQ_PMU
> 
>  #define IRQ_FIMD0_FIFO			EXYNOS4_IRQ_FIMD0_FIFO
>  #define IRQ_FIMD0_VSYNC			EXYNOS4_IRQ_FIMD0_VSYNC
> diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
> index 03f654d..ace76b4 100644
> --- a/arch/arm/plat-samsung/devs.c
> +++ b/arch/arm/plat-samsung/devs.c
> @@ -1125,7 +1125,7 @@ struct platform_device s5p_device_onenand = {
> 
>  /* PMU */
> 
> -#ifdef CONFIG_PLAT_S5P
> +#if defined(CONFIG_PLAT_S5P) && !defined(CONFIG_ARCH_EXYNOS)
>  static struct resource s5p_pmu_resource[] = {
>  	DEFINE_RES_IRQ(IRQ_PMU)
>  };
> --
> 1.7.9.5

Looks OK to me, will apply with your updated 2nd patch.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH v4 4/5] ARM: EXYNOS: Add arm-pmu DT binding for exynos5250

[Chanho Park]

This patch enables arm-pmu to bind device tree for exynos5250. The exynos5250
has two pmus which have combiner irq type.

Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/boot/dts/exynos5250.dtsi |    6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index dddfd6e..fab3eae 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -56,6 +56,12 @@
 			     <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
 	};
 
+	pmu {
+		compatible = "arm,cortex-a15-pmu";
+		interrupt-parent = <&combiner>;
+		interrupts = <1 2>, <22 4>;
+	};
+
 	watchdog {
 		compatible = "samsung,s3c2410-wdt";
 		reg = <0x101D0000 0x100>;
-- 
1.7.9.5

[PATCH v4 4/5] ARM: EXYNOS: Add arm-pmu DT binding for exynos5250

[Kukjin Kim]

Chanho Park wrote:
> 
> This patch enables arm-pmu to bind device tree for exynos5250. The
> exynos5250
> has two pmus which have combiner irq type.
> 
> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
>  arch/arm/boot/dts/exynos5250.dtsi |    6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi
> b/arch/arm/boot/dts/exynos5250.dtsi
> index dddfd6e..fab3eae 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -56,6 +56,12 @@
>  			     <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
>  	};
> 
> +	pmu {
> +		compatible = "arm,cortex-a15-pmu";
> +		interrupt-parent = <&combiner>;
> +		interrupts = <1 2>, <22 4>;
> +	};
> +
>  	watchdog {
>  		compatible = "samsung,s3c2410-wdt";
>  		reg = <0x101D0000 0x100>;
> --
> 1.7.9.5

OK, applied.
Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

[PATCH v4 5/5] ARM: EXYNOS: Add arm-pmu DT binding for exynos421x

[Chanho Park]

This patch adds a arm-pmu node to bind device tree for exynos4210.
The exynos4210 and 4212 have two cpus which includes a pmu. In contrast, the
exynos4412 has 4 cpus and pmus. We need to define two more pmus for this type
board. However, supporting arm-pmu for the exynos4412 will handle it later
because there is no dts support for 4412 based board.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/boot/dts/exynos4210.dtsi |    6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 214c557..90f9aed 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -42,6 +42,12 @@
 			     <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
 	};
 
+	pmu {
+		compatible = "arm,cortex-a9-pmu";
+		interrupt-parent = <&combiner>;
+		interrupts = <2 2>, <3 2>;
+	};
+
 	pinctrl_0: pinctrl at 11400000 {
 		compatible = "samsung,pinctrl-exynos4210";
 		reg = <0x11400000 0x1000>;
-- 
1.7.9.5

[PATCH v4 5/5] ARM: EXYNOS: Add arm-pmu DT binding for exynos421x

[Kukjin Kim]

Chanho Park wrote:
> 
> This patch adds a arm-pmu node to bind device tree for exynos4210.
> The exynos4210 and 4212 have two cpus which includes a pmu. In contrast,
> the
> exynos4412 has 4 cpus and pmus. We need to define two more pmus for this
> type
> board. However, supporting arm-pmu for the exynos4412 will handle it later
> because there is no dts support for 4412 based board.
> 
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> ---
>  arch/arm/boot/dts/exynos4210.dtsi |    6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/exynos4210.dtsi
> b/arch/arm/boot/dts/exynos4210.dtsi
> index 214c557..90f9aed 100644
> --- a/arch/arm/boot/dts/exynos4210.dtsi
> +++ b/arch/arm/boot/dts/exynos4210.dtsi
> @@ -42,6 +42,12 @@
>  			     <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
>  	};
> 
> +	pmu {
> +		compatible = "arm,cortex-a9-pmu";
> +		interrupt-parent = <&combiner>;
> +		interrupts = <2 2>, <3 2>;
> +	};
> +
>  	pinctrl_0: pinctrl at 11400000 {
>  		compatible = "samsung,pinctrl-exynos4210";
>  		reg = <0x11400000 0x1000>;
> --
> 1.7.9.5

Looks OK, applied.
Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.