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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org > -----Original Message----- > From: Shradha Todi > Sent: Monday, October 9, 2023 11:51 AM > To: jingoohan1@gmail.com; lpieralisi@kernel.org; kw@linux.com; > robh@kernel.org; bhelgaas@google.com; krzysztof.kozlowski@linaro.org; > alim.akhtar@samsung.com > Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > samsung-soc@vger.kernel.org; linux-kernel@vger.kernel.org; > pankaj.dubey@samsung.com; Shradha Todi > Subject: [PATCH] PCI: exynos: Change macro names to exynos specific > > Prefix macro names in exynos file with the term "EXYNOS" as the current > macro names seem to be generic to PCIe. > > Signed-off-by: Shradha Todi Reviewed-by: Alim Akhtar > --- > drivers/pci/controller/dwc/pci-exynos.c | 116 ++++++++++++------------ > 1 file changed, 58 insertions(+), 58 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pci-exynos.c > b/drivers/pci/controller/dwc/pci-exynos.c > index 6319082301d6..9e42cfcd99cc 100644 > --- a/drivers/pci/controller/dwc/pci-exynos.c > +++ b/drivers/pci/controller/dwc/pci-exynos.c > @@ -26,30 +26,30 @@ > #define to_exynos_pcie(x) dev_get_drvdata((x)->dev) > > /* PCIe ELBI registers */ > -#define PCIE_IRQ_PULSE 0x000 > -#define IRQ_INTA_ASSERT BIT(0) > -#define IRQ_INTB_ASSERT BIT(2) > -#define IRQ_INTC_ASSERT BIT(4) > -#define IRQ_INTD_ASSERT BIT(6) > -#define PCIE_IRQ_LEVEL 0x004 > -#define PCIE_IRQ_SPECIAL 0x008 > -#define PCIE_IRQ_EN_PULSE 0x00c > -#define PCIE_IRQ_EN_LEVEL 0x010 > -#define PCIE_IRQ_EN_SPECIAL 0x014 > -#define PCIE_SW_WAKE 0x018 > -#define PCIE_BUS_EN BIT(1) > -#define PCIE_CORE_RESET 0x01c > -#define PCIE_CORE_RESET_ENABLE BIT(0) > -#define PCIE_STICKY_RESET 0x020 > -#define PCIE_NONSTICKY_RESET 0x024 > -#define PCIE_APP_INIT_RESET 0x028 > -#define PCIE_APP_LTSSM_ENABLE 0x02c > -#define PCIE_ELBI_RDLH_LINKUP 0x074 > -#define PCIE_ELBI_XMLH_LINKUP BIT(4) > -#define PCIE_ELBI_LTSSM_ENABLE 0x1 > -#define PCIE_ELBI_SLV_AWMISC 0x11c > -#define PCIE_ELBI_SLV_ARMISC 0x120 > -#define PCIE_ELBI_SLV_DBI_ENABLE BIT(21) > +#define EXYNOS_PCIE_IRQ_PULSE 0x000 > +#define EXYNOS_IRQ_INTA_ASSERT BIT(0) > +#define EXYNOS_IRQ_INTB_ASSERT BIT(2) > +#define EXYNOS_IRQ_INTC_ASSERT BIT(4) > +#define EXYNOS_IRQ_INTD_ASSERT BIT(6) > +#define EXYNOS_PCIE_IRQ_LEVEL 0x004 > +#define EXYNOS_PCIE_IRQ_SPECIAL 0x008 > +#define EXYNOS_PCIE_IRQ_EN_PULSE 0x00c > +#define EXYNOS_PCIE_IRQ_EN_LEVEL 0x010 > +#define EXYNOS_PCIE_IRQ_EN_SPECIAL 0x014 > +#define EXYNOS_PCIE_SW_WAKE 0x018 > +#define EXYNOS_PCIE_BUS_EN BIT(1) > +#define EXYNOS_PCIE_CORE_RESET 0x01c > +#define EXYNOS_PCIE_CORE_RESET_ENABLE BIT(0) > +#define EXYNOS_PCIE_STICKY_RESET 0x020 > +#define EXYNOS_PCIE_NONSTICKY_RESET 0x024 > +#define EXYNOS_PCIE_APP_INIT_RESET 0x028 > +#define EXYNOS_PCIE_APP_LTSSM_ENABLE 0x02c > +#define EXYNOS_PCIE_ELBI_RDLH_LINKUP 0x074 > +#define EXYNOS_PCIE_ELBI_XMLH_LINKUP BIT(4) > +#define EXYNOS_PCIE_ELBI_LTSSM_ENABLE 0x1 > +#define EXYNOS_PCIE_ELBI_SLV_AWMISC 0x11c > +#define EXYNOS_PCIE_ELBI_SLV_ARMISC 0x120 > +#define EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE BIT(21) > > struct exynos_pcie { > struct dw_pcie pci; > @@ -105,49 +105,49 @@ static void > exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool on) { > u32 val; > > - val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC); > + val = exynos_pcie_readl(ep->elbi_base, > EXYNOS_PCIE_ELBI_SLV_AWMISC); > if (on) > - val |= PCIE_ELBI_SLV_DBI_ENABLE; > + val |= EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE; > else > - val &= ~PCIE_ELBI_SLV_DBI_ENABLE; > - exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC); > + val &= ~EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE; > + exynos_pcie_writel(ep->elbi_base, val, > EXYNOS_PCIE_ELBI_SLV_AWMISC); > } > > static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *ep, > bool on) { > u32 val; > > - val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC); > + val = exynos_pcie_readl(ep->elbi_base, > EXYNOS_PCIE_ELBI_SLV_ARMISC); > if (on) > - val |= PCIE_ELBI_SLV_DBI_ENABLE; > + val |= EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE; > else > - val &= ~PCIE_ELBI_SLV_DBI_ENABLE; > - exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC); > + val &= ~EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE; > + exynos_pcie_writel(ep->elbi_base, val, > EXYNOS_PCIE_ELBI_SLV_ARMISC); > } > > static void exynos_pcie_assert_core_reset(struct exynos_pcie *ep) { > u32 val; > > - val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET); > - val &= ~PCIE_CORE_RESET_ENABLE; > - exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET); > - exynos_pcie_writel(ep->elbi_base, 0, PCIE_STICKY_RESET); > - exynos_pcie_writel(ep->elbi_base, 0, PCIE_NONSTICKY_RESET); > + val = exynos_pcie_readl(ep->elbi_base, > EXYNOS_PCIE_CORE_RESET); > + val &= ~EXYNOS_PCIE_CORE_RESET_ENABLE; > + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_CORE_RESET); > + exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_STICKY_RESET); > + exynos_pcie_writel(ep->elbi_base, 0, > EXYNOS_PCIE_NONSTICKY_RESET); > } > > static void exynos_pcie_deassert_core_reset(struct exynos_pcie *ep) { > u32 val; > > - val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET); > - val |= PCIE_CORE_RESET_ENABLE; > + val = exynos_pcie_readl(ep->elbi_base, > EXYNOS_PCIE_CORE_RESET); > + val |= EXYNOS_PCIE_CORE_RESET_ENABLE; > > - exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET); > - exynos_pcie_writel(ep->elbi_base, 1, PCIE_STICKY_RESET); > - exynos_pcie_writel(ep->elbi_base, 1, PCIE_NONSTICKY_RESET); > - exynos_pcie_writel(ep->elbi_base, 1, PCIE_APP_INIT_RESET); > - exynos_pcie_writel(ep->elbi_base, 0, PCIE_APP_INIT_RESET); > + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_CORE_RESET); > + exynos_pcie_writel(ep->elbi_base, 1, EXYNOS_PCIE_STICKY_RESET); > + exynos_pcie_writel(ep->elbi_base, 1, > EXYNOS_PCIE_NONSTICKY_RESET); > + exynos_pcie_writel(ep->elbi_base, 1, > EXYNOS_PCIE_APP_INIT_RESET); > + exynos_pcie_writel(ep->elbi_base, 0, > EXYNOS_PCIE_APP_INIT_RESET); > } > > static int exynos_pcie_start_link(struct dw_pcie *pci) @@ -155,21 +155,21 > @@ static int exynos_pcie_start_link(struct dw_pcie *pci) > struct exynos_pcie *ep = to_exynos_pcie(pci); > u32 val; > > - val = exynos_pcie_readl(ep->elbi_base, PCIE_SW_WAKE); > - val &= ~PCIE_BUS_EN; > - exynos_pcie_writel(ep->elbi_base, val, PCIE_SW_WAKE); > + val = exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_SW_WAKE); > + val &= ~EXYNOS_PCIE_BUS_EN; > + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_SW_WAKE); > > /* assert LTSSM enable */ > - exynos_pcie_writel(ep->elbi_base, PCIE_ELBI_LTSSM_ENABLE, > - PCIE_APP_LTSSM_ENABLE); > + exynos_pcie_writel(ep->elbi_base, > EXYNOS_PCIE_ELBI_LTSSM_ENABLE, > + EXYNOS_PCIE_APP_LTSSM_ENABLE); > return 0; > } > > static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *ep) { > - u32 val = exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_PULSE); > + u32 val = exynos_pcie_readl(ep->elbi_base, > EXYNOS_PCIE_IRQ_PULSE); > > - exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_PULSE); > + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_IRQ_PULSE); > } > > static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg) @@ -182,12 > +182,12 @@ static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg) > > static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep) { > - u32 val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | > - IRQ_INTC_ASSERT | IRQ_INTD_ASSERT; > + u32 val = EXYNOS_IRQ_INTA_ASSERT | EXYNOS_IRQ_INTB_ASSERT | > + EXYNOS_IRQ_INTC_ASSERT | EXYNOS_IRQ_INTD_ASSERT; > > - exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_EN_PULSE); > - exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_LEVEL); > - exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_SPECIAL); > + exynos_pcie_writel(ep->elbi_base, val, > EXYNOS_PCIE_IRQ_EN_PULSE); > + exynos_pcie_writel(ep->elbi_base, 0, > EXYNOS_PCIE_IRQ_EN_LEVEL); > + exynos_pcie_writel(ep->elbi_base, 0, > EXYNOS_PCIE_IRQ_EN_SPECIAL); > } > > static u32 exynos_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, > @@ -244,9 +244,9 @@ static struct pci_ops exynos_pci_ops = { static int > exynos_pcie_link_up(struct dw_pcie *pci) { > struct exynos_pcie *ep = to_exynos_pcie(pci); > - u32 val = exynos_pcie_readl(ep->elbi_base, > PCIE_ELBI_RDLH_LINKUP); > + u32 val = exynos_pcie_readl(ep->elbi_base, > +EXYNOS_PCIE_ELBI_RDLH_LINKUP); > > - return (val & PCIE_ELBI_XMLH_LINKUP); > + return (val & EXYNOS_PCIE_ELBI_XMLH_LINKUP); > } > > static int exynos_pcie_host_init(struct dw_pcie_rp *pp) > -- > 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel