From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F1E1BC4829E for ; Thu, 15 Feb 2024 18:43:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=P9NjMFfPTMkykTiqZ114RV8SyWpzEzUkDOfIDosh3AE=; b=blAN1K5odLNnpl YEQxYSAWc2mmzlx1YN31Ij9sMaBEdOKAGDMxR9HjKGjhmV+eG9aBy6BhOjQkg7iU5KVPbAiNI8y/X 2k1m2f1STHXDCcZ/MdRF3mkSgTJUC3IZevp3ssLNCrZku34h9DVY+0f1Cm04hvFsqgzld5F11Iunu e52ityeOL+XjHVYO3G5f3xzlui3kOJAWyMr2cOKoemfrGPyMfgRPEaYX7N155oK61xBngkRvsGepP N+wC75fVxdXUJd+tAClR5iRsJDfd928jNCnRkjuKtK1as3/y6aCu7Hm+fj5afCXx605OyfsV2En9R Rkb3yNbwSga/CNxr8D1w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1raghC-0000000HPBd-47XT; Thu, 15 Feb 2024 18:42:54 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1ragh9-0000000HPA7-3Bvu for linux-arm-kernel@lists.infradead.org; Thu, 15 Feb 2024 18:42:53 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1C1311FB; Thu, 15 Feb 2024 10:43:29 -0800 (PST) Received: from [10.1.196.40] (e121345-lin.cambridge.arm.com [10.1.196.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 368023F762; Thu, 15 Feb 2024 10:42:38 -0800 (PST) Message-ID: <02fac0ab-07ac-448e-ae4e-26788ed4fce9@arm.com> Date: Thu, 15 Feb 2024 18:42:37 +0000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 01/17] iommu/arm-smmu-v3: Make STE programming independent of the callers Content-Language: en-GB To: Jason Gunthorpe , Will Deacon Cc: iommu@lists.linux.dev, Joerg Roedel , linux-arm-kernel@lists.infradead.org, Lu Baolu , Jean-Philippe Brucker , Joerg Roedel , Moritz Fischer , Moritz Fischer , Michael Shavit , Nicolin Chen , patches@lists.linux.dev, Shameer Kolothum , Mostafa Saleh , Zhangfei Gao References: <0-v5-cd1be8dd9c71+3fa-smmuv3_newapi_p1_jgg@nvidia.com> <1-v5-cd1be8dd9c71+3fa-smmuv3_newapi_p1_jgg@nvidia.com> <20240215134952.GA690@willie-the-truck> <20240215160135.GL1088888@nvidia.com> From: Robin Murphy In-Reply-To: <20240215160135.GL1088888@nvidia.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240215_104251_939400_05AC24BF X-CRM114-Status: GOOD ( 24.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 15/02/2024 4:01 pm, Jason Gunthorpe wrote: > On Thu, Feb 15, 2024 at 01:49:53PM +0000, Will Deacon wrote: >> Hi Jason, >> >> On Tue, Feb 06, 2024 at 11:12:38AM -0400, Jason Gunthorpe wrote: >>> As the comment in arm_smmu_write_strtab_ent() explains, this routine has >>> been limited to only work correctly in certain scenarios that the caller >>> must ensure. Generally the caller must put the STE into ABORT or BYPASS >>> before attempting to program it to something else. >> >> This is looking pretty good now, but I have a few comments inline. > > Ok > >>> @@ -48,6 +48,21 @@ enum arm_smmu_msi_index { >>> ARM_SMMU_MAX_MSIS, >>> }; >>> >>> +struct arm_smmu_entry_writer_ops; >>> +struct arm_smmu_entry_writer { >>> + const struct arm_smmu_entry_writer_ops *ops; >>> + struct arm_smmu_master *master; >>> +}; >>> + >>> +struct arm_smmu_entry_writer_ops { >>> + unsigned int num_entry_qwords; >>> + __le64 v_bit; >>> + void (*get_used)(const __le64 *entry, __le64 *used); >>> + void (*sync)(struct arm_smmu_entry_writer *writer); >>> +}; >> >> Can we avoid the indirection for now, please? I'm sure we'll want it later >> when you extend this to CDs, but for the initial support it just makes it >> more difficult to follow the flow. Should be a trivial thing to drop, I >> hope. > > We can. Ack, the abstraction is really hard to follow, and much of that seems entirely self-inflicted in the amount of recalculating information which was in-context in a previous step but then thrown away. And as best I can tell I think it will still end up doing more CFGIs than needed. Keeping a single monolithic check-and-update function will be *so* much easier to understand and maintain. As far as CDs go, anything we might reasonably want to change in a live CD is all in the first word so I don't see any value in attempting to generalise further on that side of things. Maybe arm_smmu_write_ctx_desc() could stand to be a bit prettier, but honestly I don't think it's too bad as-is. >>> +static void arm_smmu_get_ste_used(const __le64 *ent, __le64 *used_bits) >>> { >>> + unsigned int cfg = FIELD_GET(STRTAB_STE_0_CFG, le64_to_cpu(ent[0])); >>> + >>> + used_bits[0] = cpu_to_le64(STRTAB_STE_0_V); >>> + if (!(ent[0] & cpu_to_le64(STRTAB_STE_0_V))) >>> + return; >>> + >>> + /* >>> + * See 13.5 Summary of attribute/permission configuration fields for the >>> + * SHCFG behavior. It is only used for BYPASS, including S1DSS BYPASS, >>> + * and S2 only. >>> + */ >>> + if (cfg == STRTAB_STE_0_CFG_BYPASS || >>> + cfg == STRTAB_STE_0_CFG_S2_TRANS || >>> + (cfg == STRTAB_STE_0_CFG_S1_TRANS && >>> + FIELD_GET(STRTAB_STE_1_S1DSS, le64_to_cpu(ent[1])) == >>> + STRTAB_STE_1_S1DSS_BYPASS)) >>> + used_bits[1] |= cpu_to_le64(STRTAB_STE_1_SHCFG); >> >> Huh, SHCFG is really getting in the way here, isn't it? > > I wouldn't say that.. It is just a complicated bit of the spec. One of > the things we recently did was to audit all the cache settings and, at > least, we then realized that SHCFG was being subtly used by S2 as > well.. Yeah, that really shouldn't be subtle; incoming attributes are replaced by S1 translation, thus they are relevant to not-S1 configs. I think it's likely to be significantly more straightforward to give up on the switch statement and jump straight into the more architectural paradigm at this level, e.g. // Stage 1 if (cfg & BIT(0)) { ... } else { ... } // Stage 2 if (cfg & BIT(1)) { ... } else { ... } Thanks, Robin. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel