From mboxrd@z Thu Jan 1 00:00:00 1970 From: sean.wang@mediatek.com (sean.wang at mediatek.com) Date: Sun, 18 Feb 2018 03:54:47 +0800 Subject: [PATCH v3 12/15] arm64: dts: mt7622: add SATA device nodes In-Reply-To: References: Message-ID: <03cd35cd3ffce2a8cd238005ad3f68a868358b9e.1518895232.git.sean.wang@mediatek.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org From: Ryder Lee This patch adds SATA support fot MT7622. Signed-off-by: Ryder Lee Signed-off-by: Sean Wang --- arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 8 ++++++ arch/arm64/boot/dts/mediatek/mt7622.dtsi | 40 ++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts index 72ef443..6715ffa 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts @@ -323,6 +323,14 @@ status = "okay"; }; +&sata { + status = "okay"; +}; + +&sata_phy { + status = "okay"; +}; + &spi0 { pinctrl-names = "default"; pinctrl-0 = <&spic0_pins>; diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index cc026eb..881bc17 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -616,6 +617,45 @@ }; }; + sata: sata at 1a200000 { + compatible = "mediatek,mt7622-ahci", + "mediatek,mtk-ahci"; + reg = <0 0x1a200000 0 0x1100>; + interrupts = ; + interrupt-names = "hostc"; + clocks = <&pciesys CLK_SATA_AHB_EN>, + <&pciesys CLK_SATA_AXI_EN>, + <&pciesys CLK_SATA_ASIC_EN>, + <&pciesys CLK_SATA_RBC_EN>, + <&pciesys CLK_SATA_PM_EN>; + clock-names = "ahb", "axi", "asic", "rbc", "pm"; + phys = <&sata_port PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; + resets = <&pciesys MT7622_SATA_AXI_BUS_RST>, + <&pciesys MT7622_SATA_PHY_SW_RST>, + <&pciesys MT7622_SATA_PHY_REG_RST>; + reset-names = "axi", "sw", "reg"; + mediatek,phy-mode = <&pciesys>; + status = "disabled"; + }; + + sata_phy: sata-phy at 1a243000 { + compatible = "mediatek,generic-tphy-v1"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + sata_port: sata-phy at 1a243000 { + reg = <0 0x1a243000 0 0x0100>; + clocks = <&topckgen CLK_TOP_ETH_500M>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + ethsys: syscon at 1b000000 { compatible = "mediatek,mt7622-ethsys", "syscon"; -- 2.7.4