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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id uj19-20020a170907c99300b0088c804c4ae2sm5126434ejc.201.2023.02.06.01.52.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 06 Feb 2023 01:52:08 -0800 (PST) Message-ID: <03d6c92a-c9f3-915c-218a-14ff5c5250d2@linaro.org> Date: Mon, 6 Feb 2023 11:52:06 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 Subject: Re: [PATCH V3 4/9] dt-bindings: clock: Add Qualcomm IPQ5332 GCC Content-Language: en-GB To: Kathiravan T , krzysztof.kozlowski@linaro.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linus.walleij@linaro.org, catalin.marinas@arm.com, will@kernel.org, shawnguo@kernel.org, arnd@arndb.de, marcel.ziswiler@toradex.com, nfraprado@collabora.com, robimarko@gmail.com, quic_gurus@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: quic_varada@quicinc.com, quic_srichara@quicinc.com References: <20230206071217.29313-1-quic_kathirav@quicinc.com> <20230206071217.29313-5-quic_kathirav@quicinc.com> From: Dmitry Baryshkov In-Reply-To: <20230206071217.29313-5-quic_kathirav@quicinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230206_015213_589511_7A3966BA X-CRM114-Status: GOOD ( 19.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 06/02/2023 09:12, Kathiravan T wrote: > Add binding for the Qualcomm IPQ5332 Global Clock Controller. > > Signed-off-by: Kathiravan T > --- > Changes in V3: > - Actually I missed to remove the clocks in V2 which are supposed to > be removed. In V3 I have removed those and they are > GCC_APSS_AHB_CLK, GCC_APSS_AHB_CLK_SRC, GCC_APSS_AXI_CLK > - For the same, didn't add the Reviewed-By tags from Stephen and > Krzysztof > > Changes in V2: > - property 'clocks' is marked required > - Renamed the include file name to match with compatible > > .../bindings/clock/qcom,ipq5332-gcc.yaml | 61 +++ > include/dt-bindings/clock/qcom,ipq5332-gcc.h | 356 ++++++++++++++++++ > 2 files changed, 417 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml > create mode 100644 include/dt-bindings/clock/qcom,ipq5332-gcc.h > > diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml > new file mode 100644 > index 000000000000..961311af400c > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml > @@ -0,0 +1,61 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Global Clock & Reset Controller on IPQ5332 > + > +maintainers: > + - Stephen Boyd > + > +description: | > + Qualcomm global clock control module provides the clocks, resets and power > + domains on IPQ5332. > + > + See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h > + > +allOf: > + - $ref: qcom,gcc.yaml# > + > +properties: > + compatible: > + const: qcom,ipq5332-gcc > + > + clocks: > + items: > + - description: Board XO clock source > + - description: Sleep clock source > + - description: PCIE 2lane PHY pipe clock source > + - description: PCIE 2lane x1 PHY pipe clock source (For second lane) > + - description: USB PCIE wrapper pipe clock source > + > + clock-names: > + items: > + - const: xo > + - const: sleep_clk > + - const: pcie_2lane_phy_pipe_clk > + - const: pcie_2lane_phy_pipe_clk_x1 > + - const: usb_pcie_wrapper_pipe_clk pcie3x1_0_pipe_clk_src, pcie3x1_1_pipe_clk_src, pcie3x2_pipe_clk_src usb0_pipe_clk_src are missing. > + > +required: > + - compatible > + - clocks > + > +unevaluatedProperties: false > + > +examples: > + - | > + clock-controller@1800000 { > + compatible = "qcom,ipq5332-gcc"; > + reg = <0x01800000 0x80000>; > + clocks = <&xo_board>, > + <&sleep_clk>, > + <&pcie_2lane_phy_pipe_clk>, > + <&pcie_2lane_phy_pipe_clk_x1>, > + <&usb_pcie_wrapper_pipe_clk>; > + #clock-cells = <1>; > + #power-domain-cells = <1>; > + #reset-cells = <1>; > + }; > +... -- With best wishes Dmitry _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel