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From: Chanwoo Choi <cwchoi00@gmail.com>
To: Chanho Park <chanho61.park@samsung.com>,
	Sylwester Nawrocki <s.nawrocki@samsung.com>,
	Tomasz Figa <tomasz.figa@gmail.com>,
	Chanwoo Choi <cw00.choi@samsung.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
	Stephen Boyd <sboyd@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Alim Akhtar <alim.akhtar@samsung.com>,
	linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 1/3] dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1
Date: Thu, 30 Jun 2022 04:35:19 +0900	[thread overview]
Message-ID: <03f91699-f6f5-883d-14ae-2da193b59051@gmail.com> (raw)
In-Reply-To: <20220628104138.152118-2-chanho61.park@samsung.com>

On 22. 6. 28. 19:41, Chanho Park wrote:
> There are duplicated definitions of peric0 and peric1 cmu blocks. Thus,
> they should be defined correctly as numerical order.
> 
> Fixes: 680e1c8370a2 ("dt-bindings: clock: add clock binding definitions for Exynos Auto v9")
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
>  .../dt-bindings/clock/samsung,exynosautov9.h  | 56 +++++++++----------
>  1 file changed, 28 insertions(+), 28 deletions(-)
> 
> diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h
> index ea9f91b4eb1a..a7db6516593f 100644
> --- a/include/dt-bindings/clock/samsung,exynosautov9.h
> +++ b/include/dt-bindings/clock/samsung,exynosautov9.h
> @@ -226,21 +226,21 @@
>  #define CLK_GOUT_PERIC0_IPCLK_8		28
>  #define CLK_GOUT_PERIC0_IPCLK_9		29
>  #define CLK_GOUT_PERIC0_IPCLK_10	30
> -#define CLK_GOUT_PERIC0_IPCLK_11	30
> -#define CLK_GOUT_PERIC0_PCLK_0		31
> -#define CLK_GOUT_PERIC0_PCLK_1		32
> -#define CLK_GOUT_PERIC0_PCLK_2		33
> -#define CLK_GOUT_PERIC0_PCLK_3		34
> -#define CLK_GOUT_PERIC0_PCLK_4		35
> -#define CLK_GOUT_PERIC0_PCLK_5		36
> -#define CLK_GOUT_PERIC0_PCLK_6		37
> -#define CLK_GOUT_PERIC0_PCLK_7		38
> -#define CLK_GOUT_PERIC0_PCLK_8		39
> -#define CLK_GOUT_PERIC0_PCLK_9		40
> -#define CLK_GOUT_PERIC0_PCLK_10		41
> -#define CLK_GOUT_PERIC0_PCLK_11		42
> +#define CLK_GOUT_PERIC0_IPCLK_11	31
> +#define CLK_GOUT_PERIC0_PCLK_0		32
> +#define CLK_GOUT_PERIC0_PCLK_1		33
> +#define CLK_GOUT_PERIC0_PCLK_2		34
> +#define CLK_GOUT_PERIC0_PCLK_3		35
> +#define CLK_GOUT_PERIC0_PCLK_4		36
> +#define CLK_GOUT_PERIC0_PCLK_5		37
> +#define CLK_GOUT_PERIC0_PCLK_6		38
> +#define CLK_GOUT_PERIC0_PCLK_7		39
> +#define CLK_GOUT_PERIC0_PCLK_8		40
> +#define CLK_GOUT_PERIC0_PCLK_9		41
> +#define CLK_GOUT_PERIC0_PCLK_10		42
> +#define CLK_GOUT_PERIC0_PCLK_11		43
>  
> -#define PERIC0_NR_CLK			43
> +#define PERIC0_NR_CLK			44
>  
>  /* CMU_PERIC1 */
>  #define CLK_MOUT_PERIC1_BUS_USER	1
> @@ -272,21 +272,21 @@
>  #define CLK_GOUT_PERIC1_IPCLK_8		28
>  #define CLK_GOUT_PERIC1_IPCLK_9		29
>  #define CLK_GOUT_PERIC1_IPCLK_10	30
> -#define CLK_GOUT_PERIC1_IPCLK_11	30
> -#define CLK_GOUT_PERIC1_PCLK_0		31
> -#define CLK_GOUT_PERIC1_PCLK_1		32
> -#define CLK_GOUT_PERIC1_PCLK_2		33
> -#define CLK_GOUT_PERIC1_PCLK_3		34
> -#define CLK_GOUT_PERIC1_PCLK_4		35
> -#define CLK_GOUT_PERIC1_PCLK_5		36
> -#define CLK_GOUT_PERIC1_PCLK_6		37
> -#define CLK_GOUT_PERIC1_PCLK_7		38
> -#define CLK_GOUT_PERIC1_PCLK_8		39
> -#define CLK_GOUT_PERIC1_PCLK_9		40
> -#define CLK_GOUT_PERIC1_PCLK_10		41
> -#define CLK_GOUT_PERIC1_PCLK_11		42
> +#define CLK_GOUT_PERIC1_IPCLK_11	31
> +#define CLK_GOUT_PERIC1_PCLK_0		32
> +#define CLK_GOUT_PERIC1_PCLK_1		33
> +#define CLK_GOUT_PERIC1_PCLK_2		34
> +#define CLK_GOUT_PERIC1_PCLK_3		35
> +#define CLK_GOUT_PERIC1_PCLK_4		36
> +#define CLK_GOUT_PERIC1_PCLK_5		37
> +#define CLK_GOUT_PERIC1_PCLK_6		38
> +#define CLK_GOUT_PERIC1_PCLK_7		39
> +#define CLK_GOUT_PERIC1_PCLK_8		40
> +#define CLK_GOUT_PERIC1_PCLK_9		41
> +#define CLK_GOUT_PERIC1_PCLK_10		42
> +#define CLK_GOUT_PERIC1_PCLK_11		43
>  
> -#define PERIC1_NR_CLK			43
> +#define PERIC1_NR_CLK			44
>  
>  /* CMU_PERIS */
>  #define CLK_MOUT_PERIS_BUS_USER		1

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Samsung Electronics
Chanwoo Choi

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  reply	other threads:[~2022-06-29 19:36 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20220628104347epcas2p40f5b491f6c31b07300b5b17fe108bef7@epcas2p4.samsung.com>
2022-06-28 10:41 ` [PATCH v2 0/3] fixes for exynosautov9 clock Chanho Park
     [not found]   ` <CGME20220628104347epcas2p3cc1c9c7b17a449814fc2596f00052985@epcas2p3.samsung.com>
2022-06-28 10:41     ` [PATCH v2 1/3] dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1 Chanho Park
2022-06-29 19:35       ` Chanwoo Choi [this message]
     [not found]   ` <CGME20220628104347epcas2p4502a4524de0c98ababe8cab4b7b73c3f@epcas2p4.samsung.com>
2022-06-28 10:41     ` [PATCH v2 2/3] clk: samsung: exynosautov9: add missing gate clks for peric0/c1 Chanho Park
2022-06-29  9:59       ` Krzysztof Kozlowski
2022-06-29 19:36       ` Chanwoo Choi
     [not found]   ` <CGME20220628104347epcas2p48a7fe482ad82004c145fcf90e32eaec6@epcas2p4.samsung.com>
2022-06-28 10:41     ` [PATCH v2 3/3] clk: samsung: exynosautov9: correct register offsets of peric0/c1 Chanho Park
2022-06-29 19:37       ` Chanwoo Choi

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