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Wed, 27 Jul 2022 11:29:03 +0100 MIME-Version: 1.0 Date: Wed, 27 Jul 2022 11:29:03 +0100 From: Marc Zyngier To: Alexandru Elisei Cc: Oliver Upton , Will Deacon , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Subject: Re: KVM/arm64: SPE: Translate VA to IPA on a stage 2 fault instead of pinning VM memory In-Reply-To: References: <20220419141012.GB6143@willie-the-truck> User-Agent: Roundcube Webmail/1.4.13 Message-ID: <04dea801e298374fb783bf0760b15241@kernel.org> X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: alexandru.elisei@arm.com, oliver.upton@linux.dev, will@kernel.org, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220727_032907_629184_F1819C47 X-CRM114-Status: GOOD ( 21.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2022-07-27 11:19, Alexandru Elisei wrote: > Hi Oliver, > > Thank you for the help, replies below. > > On Tue, Jul 26, 2022 at 10:51:21AM -0700, Oliver Upton wrote: >> Hi Alex, >> >> On Mon, Jul 25, 2022 at 11:06:24AM +0100, Alexandru Elisei wrote: >> >> [...] >> >> > > A funkier approach might be to defer pinning of the buffer until the SPE is >> > > enabled and avoid pinning all of VM memory that way, although I can't >> > > immediately tell how flexible the architecture is in allowing you to cache >> > > the base/limit values. >> > >> > I was investigating this approach, and Mark raised a concern that I think >> > might be a showstopper. >> > >> > Let's consider this scenario: >> > >> > Initial conditions: guest at EL1, profiling disabled (PMBLIMITR_EL1.E = 0, >> > PMBSR_EL1.S = 0, PMSCR_EL1.{E0SPE,E1SPE} = {0,0}). >> > >> > 1. Guest programs the buffer and enables it (PMBLIMITR_EL1.E = 1). >> > 2. Guest programs SPE to enable profiling at **EL0** >> > (PMSCR_EL1.{E0SPE,E1SPE} = {1,0}). >> > 3. Guest changes the translation table entries for the buffer. The >> > architecture allows this. >> > 4. Guest does an ERET to EL0, thus enabling profiling. >> > >> > Since KVM cannot trap the ERET to EL0, it will be impossible for KVM to pin >> > the buffer at stage 2 when profiling gets enabled at EL0. >> >> Not saying we necessarily should, but this is possible with FGT no? > > It doesn't look to me like FEAT_FGT offers any knobs to trap ERET from > EL1. See HFGITR.ERET. Thanks, M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel