[PATCH 0/7] arm64: allwinner: a523: add USB3.0 support

[PATCH 0/7] arm64: allwinner: a523: add USB3.0 support

[iuncuim]

From: Mikhail Kalashnikov <iuncuim@gmail.com>

This series is a draft and does not include patches for dt-bindings.
The first series is necessary for testing on other devices and
initiating discussion.

This series of patches adds USB 3.0 functionality for the
A523/A527/H728/T527 processor.Most of the code is derived from the BSP,
 as the datasheet does not fully describe this feature.

I have verified functionality on two of my boards, walnutpi 2b (t527)
and x96qproplus (h728). When testing usb3.0 on x96qproplus, I get
reconnections of my nvme, it looks like the port does not provide enough
 current to work. I have encountered similar complaints from users of the
  device on Android. In the case of walnutpi, there is no such problem.

Based on 6.17-rc1

Mikhail Kalashnikov (7):
  clk: sunxi-ng: a523: add missing usb related clocks
  arm64: dts: allwinner: a523: add third usb2 phy
  phy: sun4i-usb: a523: add support for the USB2 PHY
  phy: allwinner: a523: add USB3/PCIe PHY driver
  arm64: dts: allwinner: a523: add USB3.0 phy node
  arm64: dts: allwinner: a523: add DWC3 USB3.0 node
  arm64: dts: allwinner: a523: activate USB3 for all boards

 .../arm64/boot/dts/allwinner/sun55i-a523.dtsi |  52 +++-
 .../dts/allwinner/sun55i-a527-cubie-a5e.dts   |   8 +
 .../dts/allwinner/sun55i-h728-x96qpro+.dts    |   8 +
 .../dts/allwinner/sun55i-t527-avaota-a1.dts   |   8 +
 drivers/clk/sunxi-ng/ccu-sun55i-a523.c        |  32 +++
 drivers/clk/sunxi-ng/ccu-sun55i-a523.h        |   2 +-
 drivers/phy/allwinner/Kconfig                 |   9 +
 drivers/phy/allwinner/Makefile                |   1 +
 drivers/phy/allwinner/phy-sun4i-usb.c         |  10 +
 drivers/phy/allwinner/phy-sun55i-usb3-pcie.c  | 267 ++++++++++++++++++
 include/dt-bindings/clock/sun55i-a523-ccu.h   |   4 +
 11 files changed, 392 insertions(+), 9 deletions(-)
 create mode 100644 drivers/phy/allwinner/phy-sun55i-usb3-pcie.c

-- 
2.50.1

[PATCH 1/7] clk: sunxi-ng: a523: add missing usb related clocks

[iuncuim]

From: Mikhail Kalashnikov <iuncuim@gmail.com>

Several clocks were omitted when adding the original driver. These clocks
are necessary for USB 3.0 to work correctly. I added these declarations
according to the driver's BSP code.

Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
---
 drivers/clk/sunxi-ng/ccu-sun55i-a523.c      | 32 +++++++++++++++++++++
 drivers/clk/sunxi-ng/ccu-sun55i-a523.h      |  2 +-
 include/dt-bindings/clock/sun55i-a523-ccu.h |  4 +++
 3 files changed, 37 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c
index 1a9a1cb86..7bf41e628 100644
--- a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c
+++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c
@@ -853,6 +853,31 @@ static struct ccu_mux usb_ohci1_clk = {
 	},
 };
 
+static SUNXI_CCU_GATE_DATA(usb2_clk, "usb2", osc24M, 0xa80, BIT(31), 0);
+
+static const struct clk_parent_data usb3_parents[] = {
+	{ .fw_name = "hosc" },
+	{ .hw = &pll_periph0_200M_clk.hw },
+	{ .hw = &pll_periph1_200M_clk.hw },
+};
+
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb3_clk, "usb3", usb3_parents, 0xa84,
+				      0, 5,	/* M */
+				      24, 3,	/* mux */
+				      BIT(31),	/* gate */
+				      0);
+
+static const struct clk_parent_data usb3_suspend_parents[] = {
+	{ .fw_name = "losc" },
+};
+
+static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb3_suspend_clk, "usb3-suspend",
+				      usb3_suspend_parents, 0xa88,
+				      0, 5,	/* M */
+				      24, 1,	/* mux */
+				      BIT(31),	/* gate */
+				      0);
+
 static SUNXI_CCU_GATE_HWS(bus_ohci0_clk, "bus-ohci0", ahb_hws, 0xa8c,
 			  BIT(0), 0);
 static SUNXI_CCU_GATE_HWS(bus_ohci1_clk, "bus-ohci1", ahb_hws, 0xa8c,
@@ -1290,6 +1315,9 @@ static struct ccu_common *sun55i_a523_ccu_clks[] = {
 	&bus_ths_clk.common,
 	&usb_ohci0_clk.common,
 	&usb_ohci1_clk.common,
+	&usb2_clk.common,
+	&usb3_clk.common,
+	&usb3_suspend_clk.common,
 	&bus_ohci0_clk.common,
 	&bus_ohci1_clk.common,
 	&bus_ehci0_clk.common,
@@ -1422,6 +1450,7 @@ static struct clk_hw_onecell_data sun55i_a523_hw_clks = {
 		[CLK_MBUS_DMA]		= &mbus_dma_clk.common.hw,
 		[CLK_MBUS_VE]		= &mbus_ve_clk.common.hw,
 		[CLK_MBUS_CE]		= &mbus_ce_clk.common.hw,
+		[CLK_MBUS_USB3]		= &mbus_usb3_clk.common.hw,
 		[CLK_MBUS_CSI]		= &mbus_csi_clk.common.hw,
 		[CLK_MBUS_ISP]		= &mbus_isp_clk.common.hw,
 		[CLK_MBUS_EMAC1]	= &mbus_gmac1_clk.common.hw,
@@ -1474,6 +1503,9 @@ static struct clk_hw_onecell_data sun55i_a523_hw_clks = {
 		[CLK_BUS_THS]		= &bus_ths_clk.common.hw,
 		[CLK_USB_OHCI0]		= &usb_ohci0_clk.common.hw,
 		[CLK_USB_OHCI1]		= &usb_ohci1_clk.common.hw,
+		[CLK_USB2]		= &usb2_clk.common.hw,
+		[CLK_USB3]		= &usb3_clk.common.hw,
+		[CLK_USB3_SUSPEND]	= &usb3_suspend_clk.common.hw,
 		[CLK_BUS_OHCI0]		= &bus_ohci0_clk.common.hw,
 		[CLK_BUS_OHCI1]		= &bus_ohci1_clk.common.hw,
 		[CLK_BUS_EHCI0]		= &bus_ehci0_clk.common.hw,
diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523.h b/drivers/clk/sunxi-ng/ccu-sun55i-a523.h
index fc8dd42f1..d6916c728 100644
--- a/drivers/clk/sunxi-ng/ccu-sun55i-a523.h
+++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523.h
@@ -9,6 +9,6 @@
 #include <dt-bindings/clock/sun55i-a523-ccu.h>
 #include <dt-bindings/reset/sun55i-a523-ccu.h>
 
-#define CLK_NUMBER	(CLK_FANOUT2 + 1)
+#define CLK_NUMBER	(CLK_MBUS_USB3 + 1)
 
 #endif /* _CCU_SUN55I_A523_H */
diff --git a/include/dt-bindings/clock/sun55i-a523-ccu.h b/include/dt-bindings/clock/sun55i-a523-ccu.h
index c8259ac5a..26b2e9dc8 100644
--- a/include/dt-bindings/clock/sun55i-a523-ccu.h
+++ b/include/dt-bindings/clock/sun55i-a523-ccu.h
@@ -185,5 +185,9 @@
 #define CLK_FANOUT0		176
 #define CLK_FANOUT1		177
 #define CLK_FANOUT2		178
+#define CLK_USB2		179
+#define CLK_USB3		180
+#define CLK_USB3_SUSPEND	181
+#define CLK_MBUS_USB3		182
 
 #endif /* _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_ */
-- 
2.50.1

[PATCH 2/7] arm64: dts: allwinner: a523: add third usb2 phy

[iuncuim]

From: Mikhail Kalashnikov <iuncuim@gmail.com>

It seems that there are actually three usb2 phys in the processor, which
makes it incompatible with D1.
The third phy is used together with USB3/PCIe combophy with DWC3
controller. In the BSP code, the third PHY requires a separate glue
driver, but it seems that it is not needed.
According to the BSP code, the third phy does not have a reset line; the
only reset is declared in the DWC3 node, but none of this is documented.
Since sun4i-usb-phy driver requires a reset, I added RST_BUS_3 here.

Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
---
 .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 21 ++++++++++++-------
 1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
index 6b6f2296b..e4ed4fa82 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
@@ -503,22 +503,27 @@ usb_otg: usb@4100000 {
 		};
 
 		usbphy: phy@4100400 {
-			compatible = "allwinner,sun55i-a523-usb-phy",
-				     "allwinner,sun20i-d1-usb-phy";
+			compatible = "allwinner,sun55i-a523-usb-phy";
 			reg = <0x4100400 0x100>,
 			      <0x4101800 0x100>,
-			      <0x4200800 0x100>;
+			      <0x4200800 0x100>,
+				  <0x4e00000 0x100>;
 			reg-names = "phy_ctrl",
 				    "pmu0",
-				    "pmu1";
+				    "pmu1",
+					"pmu2";
 			clocks = <&osc24M>,
-				 <&osc24M>;
+				 <&osc24M>,
+				 <&ccu CLK_USB2>;
 			clock-names = "usb0_phy",
-				      "usb1_phy";
+				      "usb1_phy",
+					  "usb2_phy";
 			resets = <&ccu RST_USB_PHY0>,
-				 <&ccu RST_USB_PHY1>;
+				 <&ccu RST_USB_PHY1>,
+				 <&ccu RST_BUS_3>;
 			reset-names = "usb0_reset",
-				      "usb1_reset";
+				      "usb1_reset",
+					  "usb2_reset";
 			status = "disabled";
 			#phy-cells = <1>;
 		};
-- 
2.50.1

[PATCH 3/7] phy: sun4i-usb: a523: add support for the USB2 PHY

[iuncuim]

From: Mikhail Kalashnikov <iuncuim@gmail.com>

Previously, USB PHY was compatible with D1 and did not require
separatedata options. But now we need to add a third PHY, which makes it
incompatible. The third PHY is used together with USB3/PCIe combophy with
DWC3 controller. In the BSP code, the third PHY requires a separate glue
driver, but it seems that it is not needed.

Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
---
 drivers/phy/allwinner/phy-sun4i-usb.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index 8873aed3a..bb79339f2 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -1025,6 +1025,15 @@ static const struct sun4i_usb_phy_cfg sun50i_h616_cfg = {
 	.siddq_in_base = true,
 };
 
+static const struct sun4i_usb_phy_cfg sun55i_a523_cfg = {
+	.num_phys = 3,
+	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
+	.hci_phy_ctl_clear = PHY_CTL_SIDDQ,
+	.phy0_dual_route = true,
+	.siddq_in_base = true,
+};
+
 static const struct of_device_id sun4i_usb_phy_of_match[] = {
 	{ .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg },
 	{ .compatible = "allwinner,sun5i-a13-usb-phy", .data = &sun5i_a13_cfg },
@@ -1041,6 +1050,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
 	  .data = &sun50i_a64_cfg},
 	{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = &sun50i_h6_cfg },
 	{ .compatible = "allwinner,sun50i-h616-usb-phy", .data = &sun50i_h616_cfg },
+	{ .compatible = "allwinner,sun55i-a523-usb-phy", .data = &sun55i_a523_cfg },
 	{ .compatible = "allwinner,suniv-f1c100s-usb-phy",
 	  .data = &suniv_f1c100s_cfg },
 	{ },
-- 
2.50.1

[PATCH 4/7] phy: allwinner: a523: add USB3/PCIe PHY driver

[iuncuim]

From: Mikhail Kalashnikov <iuncuim@gmail.com>

The A523 family of processors features a combophy for USB 3.0 and PCIe,
developed by Innosilicon. Simultaneous operation of both interfaces is
not supported by design.
Currently, the driver only adds support for USB 3.0. PCIe support is
currently unavailable and will be added later.
All data on phy configuration is taken from the manufacturer's BSP driver.

Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
---
 drivers/phy/allwinner/Kconfig                |   9 +
 drivers/phy/allwinner/Makefile               |   1 +
 drivers/phy/allwinner/phy-sun55i-usb3-pcie.c | 267 +++++++++++++++++++
 3 files changed, 277 insertions(+)
 create mode 100644 drivers/phy/allwinner/phy-sun55i-usb3-pcie.c

diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig
index fb584518b..af2a82e51 100644
--- a/drivers/phy/allwinner/Kconfig
+++ b/drivers/phy/allwinner/Kconfig
@@ -57,3 +57,12 @@ config PHY_SUN50I_USB3
 	  part of Allwinner H6 SoC.
 
 	  This driver controls each individual USB 2+3 host PHY combo.
+
+config PHY_SUN55I_USB3_PCIE
+	tristate "Allwinner A523 Innosilicon USB3/PCIe Combophy Driver"
+	depends on ARCH_SUNXI || COMPILE_TEST
+	depends on RESET_CONTROLLER
+	select GENERIC_PHY
+	help
+	  Enable this to support the Allwinner PCIe/USB3.0 combo PHY
+	  with Innosilicon IP block founded in A523/A527/H728/T527 SOC
diff --git a/drivers/phy/allwinner/Makefile b/drivers/phy/allwinner/Makefile
index bd74901a1..5948a27ef 100644
--- a/drivers/phy/allwinner/Makefile
+++ b/drivers/phy/allwinner/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_PHY_SUN4I_USB)		+= phy-sun4i-usb.o
 obj-$(CONFIG_PHY_SUN6I_MIPI_DPHY)	+= phy-sun6i-mipi-dphy.o
 obj-$(CONFIG_PHY_SUN9I_USB)		+= phy-sun9i-usb.o
 obj-$(CONFIG_PHY_SUN50I_USB3)		+= phy-sun50i-usb3.o
+obj-$(CONFIG_PHY_SUN55I_USB3_PCIE)		+= phy-sun55i-usb3-pcie.o
diff --git a/drivers/phy/allwinner/phy-sun55i-usb3-pcie.c b/drivers/phy/allwinner/phy-sun55i-usb3-pcie.c
new file mode 100644
index 000000000..905c54a67
--- /dev/null
+++ b/drivers/phy/allwinner/phy-sun55i-usb3-pcie.c
@@ -0,0 +1,267 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for Innosilicon USB3.0/PCIe phy found in Allwinner A523 processors.
+ * Currently, the driver only supports the USB3.0 part.
+ *
+ * Copyright (C) 2025 Mikhail Kalashnikov <iuncuim@gmail.com>
+ * Based on phy-sun50i-usb3.c, which is:
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+
+#define PHY_SYS_VER			0x00
+
+#define PHY_USB3_BGR		0x08
+/* Control bits for the USB3 part */
+#define USB3_RESETN			BIT(0)
+#define USB3_ACLK_EN		BIT(17)
+#define USB3_HCLK_EN		BIT(16)
+
+#define PHY_CTL				0x10
+/* Control bits for the common part */
+#define PHY_RSTN			BIT(0)
+/* Bit for selecting internal(0) or external(1) clock */
+#define PHY_CLK_SEL			BIT(30)
+/* Bit for selecting PCIe(0) or USB3(1) role */
+#define PHY_USE_SEL			BIT(31)
+
+#define PHY_CLK_OFFSET		0x80000
+
+struct sun55i_usb3_pcie_phy {
+	struct device *dev;
+	struct phy *phy;
+	void __iomem *regs;
+	void __iomem *regs_clk;
+	struct reset_control *reset;
+	struct clk *clk;
+};
+
+/*
+ * These values are derived from the manufacturer's driver code.
+ * Comments are preserved.
+ */
+static void sun55i_usb3_phy_open(struct sun55i_usb3_pcie_phy *phy)
+{
+	u32 val;
+
+	val = readl(phy->regs_clk + 0x1418);
+	val &= ~(GENMASK(17, 16));
+	val |= BIT(25);
+	writel(val, phy->regs_clk + 0x1418);
+
+	/* reg_rx_eq_bypass[3]=1, rx_ctle_res_cal_bypass */
+	val = readl(phy->regs_clk + 0x674);
+	val |= BIT(3);
+	writel(val, phy->regs_clk + 0x674);
+
+	/* rx_ctle_res_cal=0xf, 0x4->0xf */
+	val = readl(phy->regs_clk + 0x704);
+	val |= BIT(8) | BIT(9) | BIT(11);
+	writel(val, phy->regs_clk + 0x704);
+
+	/* CDR_div_fin_gain1 */
+	val = readl(phy->regs_clk + 0x400);
+	val |= BIT(4);
+	writel(val, phy->regs_clk + 0x400);
+
+	/* CDR_div1_fin_gain1 */
+	val = readl(phy->regs_clk + 0x404);
+	val |= GENMASK(3, 0);
+	val |= BIT(5);
+	writel(val, phy->regs_clk + 0x404);
+
+	/* CDR_div3_fin_gain1 */
+	val = readl(phy->regs_clk + 0x408);
+	val |= BIT(5);
+	writel(val, phy->regs_clk + 0x408);
+
+	val = readl(phy->regs_clk + 0x109c);
+	val |= BIT(1);
+	writel(val, phy->regs_clk + 0x109c);
+
+	/* SSC configure */
+	/* div_N */
+	val = readl(phy->regs_clk + 0x107c);
+	val &= ~(GENMASK(17, 12));
+	val |= BIT(12);
+	writel(val, phy->regs_clk + 0x107c);
+
+	/* modulation freq div */
+	val = readl(phy->regs_clk + 0x1020);
+	val &= ~(GENMASK(4, 0));
+	val |= BIT(1) | BIT(2);
+	writel(val, phy->regs_clk + 0x1020);
+
+	/* spread[6:0], 400*9=4410ppm ssc */
+	val = readl(phy->regs_clk + 0x1034);
+	val &= ~(GENMASK(22, 16));
+	val |= BIT(16) | BIT(19);
+	writel(val, phy->regs_clk + 0x1034);
+
+	val = readl(phy->regs_clk + 0x101c);
+	/* don't disable ssc = 0 */
+	val &= ~BIT(28);
+	/* choose downspread */
+	val |= BIT(27);
+	writel(val, phy->regs_clk + 0x101c);
+}
+
+static int sun55i_usb3_pcie_clk_init(struct sun55i_usb3_pcie_phy *phy)
+{
+	u32 val;
+	int ret;
+
+	ret = clk_prepare_enable(phy->clk);
+	if (ret)
+		return ret;
+
+	ret = reset_control_deassert(phy->reset);
+	if (ret) {
+		clk_disable_unprepare(phy->clk);
+		return ret;
+	}
+
+	val = readl(phy->regs + PHY_CTL);
+	val |= PHY_USE_SEL | PHY_RSTN;
+	val &= ~PHY_CLK_SEL;
+	writel(val, phy->regs + PHY_CTL);
+
+	val = readl(phy->regs + PHY_USB3_BGR);
+	val |= USB3_ACLK_EN | USB3_HCLK_EN | USB3_RESETN;
+	writel(val, phy->regs + PHY_USB3_BGR);
+
+	return 0;
+}
+
+static int sun55i_usb3_pcie_phy_init(struct phy *_phy)
+{
+	struct sun55i_usb3_pcie_phy *phy = phy_get_drvdata(_phy);
+
+	sun55i_usb3_phy_open(phy);
+
+	return 0;
+}
+
+static int sun55i_usb3_pcie_phy_exit(struct phy *_phy)
+{
+	struct sun55i_usb3_pcie_phy *phy = phy_get_drvdata(_phy);
+
+	reset_control_assert(phy->reset);
+	clk_disable_unprepare(phy->clk);
+
+	return 0;
+}
+
+static void sun55i_usb3_pcie_phy_power_set(struct phy *_phy, bool on)
+{
+	struct sun55i_usb3_pcie_phy *phy = phy_get_drvdata(_phy);
+	u32 val;
+
+	val = readl(phy->regs_clk + 0x14);
+	val = on ? (val & ~BIT(26)) : (val | BIT(26));
+	writel(val, phy->regs_clk + 0x14);
+
+	val = readl(phy->regs_clk);
+	val = on ? (val & ~BIT(10)) : (val | BIT(10));
+	writel(val, phy->regs_clk);
+}
+
+static int sun55i_usb3_pcie_phy_power_on(struct phy *_phy)
+{
+	sun55i_usb3_pcie_phy_power_set(_phy, true);
+
+	return 0;
+}
+
+static int sun55i_usb3_pcie_phy_power_off(struct phy *_phy)
+{
+	sun55i_usb3_pcie_phy_power_set(_phy, false);
+
+	return 0;
+}
+
+static const struct phy_ops sun55i_usb3_pcie_phy_ops = {
+	.init		= sun55i_usb3_pcie_phy_init,
+	.exit		= sun55i_usb3_pcie_phy_exit,
+	.power_on	= sun55i_usb3_pcie_phy_power_on,
+	.power_off	= sun55i_usb3_pcie_phy_power_off,
+	.owner		= THIS_MODULE,
+};
+
+static int sun55i_usb3_pcie_phy_probe(struct platform_device *pdev)
+{
+	struct sun55i_usb3_pcie_phy *phy;
+	struct device *dev = &pdev->dev;
+	struct phy_provider *phy_provider;
+	int ret;
+
+	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+	if (!phy)
+		return -ENOMEM;
+
+	phy->dev = dev;
+	phy->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(phy->clk)) {
+		if (PTR_ERR(phy->clk) != -EPROBE_DEFER)
+			dev_err(dev, "failed to get phy clock\n");
+		return PTR_ERR(phy->clk);
+	}
+
+	phy->reset = devm_reset_control_get(dev, NULL);
+	if (IS_ERR(phy->reset)) {
+		dev_err(dev, "failed to get reset control\n");
+		return PTR_ERR(phy->reset);
+	}
+
+	phy->regs = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(phy->regs))
+		return PTR_ERR(phy->regs);
+
+	phy->regs_clk = phy->regs + PHY_CLK_OFFSET;
+	if (IS_ERR(phy->regs_clk))
+		return PTR_ERR(phy->regs_clk);
+
+	phy->phy = devm_phy_create(dev, NULL, &sun55i_usb3_pcie_phy_ops);
+	if (IS_ERR(phy->phy)) {
+		dev_err(dev, "failed to create PHY\n");
+		return PTR_ERR(phy->phy);
+	}
+
+	phy_set_drvdata(phy->phy, phy);
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+	ret = sun55i_usb3_pcie_clk_init(phy);
+	if (ret)
+		return ret;
+	dev_info(phy->dev, "phy version is: 0x%x\n", readl(phy->regs));
+
+	return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id sun55i_usb3_pcie_phy_of_match[] = {
+	{ .compatible = "allwinner,sun55i-a523-usb3-pcie-phy" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, sun55i_usb3_pcie_phy_of_match);
+
+static struct platform_driver sun55i_usb3_pcie_phy_driver = {
+	.probe	= sun55i_usb3_pcie_phy_probe,
+	.driver = {
+		.of_match_table	= sun55i_usb3_pcie_phy_of_match,
+		.name  = "sun55i-usb3-pcie-phy",
+	}
+};
+module_platform_driver(sun55i_usb3_pcie_phy_driver);
+
+MODULE_DESCRIPTION("Allwinner A523 USB3/PCIe phy driver");
+MODULE_AUTHOR("Mikhail Kalashnikov <iuncuim@gmail.com>");
+MODULE_LICENSE("GPL");
-- 
2.50.1

[PATCH 5/7] arm64: dts: allwinner: a523: add USB3.0 phy node

[iuncuim]

From: Mikhail Kalashnikov <iuncuim@gmail.com>

After adding the phy driver, we can also add phy node. In addition to the
clk and reset lines, the power domain PD_PCIE is declared in this node
according to the bsp dtb. So let's mention it. 
Currently, phy driver does not support role selection and only works in
USB3.0 mode.

Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
---
 arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
index e4ed4fa82..233365496 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
@@ -606,6 +606,16 @@ mdio0: mdio {
 			};
 		};
 
+		combophy: phy@4f00000 {
+			compatible = "allwinner,sun55i-a523-usb3-pcie-phy";
+			reg = <0x04f00000 0x100000>;
+			clocks = <&ccu CLK_USB3>;
+			resets = <&ccu RST_BUS_PCIE_USB3>;
+			#phy-cells = <0>;
+			power-domains = <&pck600 PD_PCIE>;
+			status = "disabled";
+		};
+
 		ppu: power-controller@7001400 {
 			compatible = "allwinner,sun55i-a523-ppu";
 			reg = <0x07001400 0x400>;
-- 
2.50.1

[PATCH 6/7] arm64: dts: allwinner: a523: add DWC3 USB3.0 node

[iuncuim]

From: Mikhail Kalashnikov <iuncuim@gmail.com>

After adding the phy bindings, we can also add dwc3 node, which uses the
previously added usbphy2 and part of usb3 from combophy.
All settings declared in dwc3 node are obtained from the x96qproplus' dtb.
BSP contains an additional glue driver for dwc3, but it seems that it is
not needed.

Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
---
 .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 21 +++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
index 233365496..ec170888a 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
@@ -606,6 +606,27 @@ mdio0: mdio {
 			};
 		};
 
+		dwc3: usb@4d00000 {
+			compatible = "snps,dwc3";
+			reg = <0x04d00000 0x100000>;
+			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+			dr_mode = "host";
+			clocks = <&ccu CLK_MBUS_USB3>, <&ccu CLK_USB3>,
+				 <&ccu CLK_USB2>, <&ccu CLK_USB3_SUSPEND>;
+			clock-names = "bus_clk", "ref_clk3", "ref_clk2", "suspend";
+			maximum-speed = "super-speed";
+			phy_type = "utmi";
+			snps,dis_enblslpm_quirk;
+			snps,dis-u1-entry-quirk;
+			snps,dis-u2-entry-quirk;
+			snps,dis_u3_susphy_quirk;
+			snps,dis_u2_susphy_quirk;
+			snps,dis_rxdet_inp3_quirk;
+			phys = <&usbphy 2>, <&combophy>;
+			phy-names = "usb2-phy", "usb3-phy";
+			status = "disabled";
+		};
+
 		combophy: phy@4f00000 {
 			compatible = "allwinner,sun55i-a523-usb3-pcie-phy";
 			reg = <0x04f00000 0x100000>;
-- 
2.50.1

[PATCH 7/7] arm64: dts: allwinner: a523: activate USB3 for all boards

[iuncuim]

From: Mikhail Kalashnikov <iuncuim@gmail.com>

Currently, these devices have a USB 3.0 port. Therefore, we can activate
it.

Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
---
 arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts | 8 ++++++++
 arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts  | 8 ++++++++
 arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts | 8 ++++++++
 3 files changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
index 553ad774e..6842f8e8d 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
@@ -47,6 +47,14 @@ reg_usb_vbus: vbus {
 	};
 };
 
+&combophy {
+	status = "okay";
+};
+
+&dwc3 {
+	status = "okay";
+};
+
 &ehci0 {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts b/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts
index a96927fbd..19388bc11 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts
+++ b/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts
@@ -46,6 +46,14 @@ reg_vcc3v3: vcc3v3 {
 	};
 };
 
+&combophy {
+	status = "okay";
+};
+
+&dwc3 {
+	status = "okay";
+};
+
 &ehci0 {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts
index b9eeb6753..6f05cd297 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts
@@ -57,6 +57,14 @@ reg_usb_vbus: vbus {
 	};
 };
 
+&combophy {
+	status = "okay";
+};
+
+&dwc3 {
+	status = "okay";
+};
+
 &ehci0 {
 	status = "okay";
 };
-- 
2.50.1

Re: [PATCH 1/7] clk: sunxi-ng: a523: add missing usb related clocks

[Krzysztof Kozlowski]

On 16/08/2025 10:46, iuncuim wrote:
> From: Mikhail Kalashnikov <iuncuim@gmail.com>
> 
> Several clocks were omitted when adding the original driver. These clocks
> are necessary for USB 3.0 to work correctly. I added these declarations
> according to the driver's BSP code.
> 
> Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
> ---
>  drivers/clk/sunxi-ng/ccu-sun55i-a523.c      | 32 +++++++++++++++++++++
>  drivers/clk/sunxi-ng/ccu-sun55i-a523.h      |  2 +-
>  include/dt-bindings/clock/sun55i-a523-ccu.h |  4 +++


Bindings should be a separate patch. Checkpatch should also suggest that.

Best regards,
Krzysztof

Re: [PATCH 2/7] arm64: dts: allwinner: a523: add third usb2 phy

[Krzysztof Kozlowski]

On 16/08/2025 10:46, iuncuim wrote:
> From: Mikhail Kalashnikov <iuncuim@gmail.com>
> 
> It seems that there are actually three usb2 phys in the processor, which
> makes it incompatible with D1.
> The third phy is used together with USB3/PCIe combophy with DWC3
> controller. In the BSP code, the third PHY requires a separate glue
> driver, but it seems that it is not needed.
> According to the BSP code, the third phy does not have a reset line; the
> only reset is declared in the DWC3 node, but none of this is documented.
> Since sun4i-usb-phy driver requires a reset, I added RST_BUS_3 here.
> 
> Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
> ---
>  .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 21 ++++++++++++-------
>  1 file changed, 13 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
> index 6b6f2296b..e4ed4fa82 100644
> --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
> @@ -503,22 +503,27 @@ usb_otg: usb@4100000 {
>  		};
>  
>  		usbphy: phy@4100400 {
> -			compatible = "allwinner,sun55i-a523-usb-phy",
> -				     "allwinner,sun20i-d1-usb-phy";
> +			compatible = "allwinner,sun55i-a523-usb-phy";


That's potential break of all users. Also, having third phy (so
additional piece) is not making things incompatible.



Best regards,
Krzysztof

Re: [PATCH 5/7] arm64: dts: allwinner: a523: add USB3.0 phy node

[Krzysztof Kozlowski]

On 16/08/2025 10:46, iuncuim wrote:
> From: Mikhail Kalashnikov <iuncuim@gmail.com>
> 
> After adding the phy driver, we can also add phy node. In addition to the
> clk and reset lines, the power domain PD_PCIE is declared in this node
> according to the bsp dtb. So let's mention it. 
> Currently, phy driver does not support role selection and only works in
> USB3.0 mode.
> 
> Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
> ---
>  arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)

Please organize your patches correctly. One DTS was in the middle of
patchset, other is at the end. They all must be at the end, because you
cannot have dependency of driver on DTS.

Best regards,
Krzysztof

Re: [PATCH 4/7] phy: allwinner: a523: add USB3/PCIe PHY driver

[Krzysztof Kozlowski]

On 16/08/2025 10:46, iuncuim wrote:
> +
> +	phy->reset = devm_reset_control_get(dev, NULL);
> +	if (IS_ERR(phy->reset)) {
> +		dev_err(dev, "failed to get reset control\n");
> +		return PTR_ERR(phy->reset);

Syntax is return dev_err_probe.

> +	}
> +
> +	phy->regs = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(phy->regs))
> +		return PTR_ERR(phy->regs);
> +
> +	phy->regs_clk = phy->regs + PHY_CLK_OFFSET;
> +	if (IS_ERR(phy->regs_clk))
> +		return PTR_ERR(phy->regs_clk);
> +
> +	phy->phy = devm_phy_create(dev, NULL, &sun55i_usb3_pcie_phy_ops);
> +	if (IS_ERR(phy->phy)) {
> +		dev_err(dev, "failed to create PHY\n");
> +		return PTR_ERR(phy->phy);
> +	}
> +
> +	phy_set_drvdata(phy->phy, phy);
> +	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +
> +	ret = sun55i_usb3_pcie_clk_init(phy);
> +	if (ret)
> +		return ret;
> +	dev_info(phy->dev, "phy version is: 0x%x\n", readl(phy->regs));


This should be rather dev_dbg. See coding style.

> +
> +	return PTR_ERR_OR_ZERO(phy_provider);
> +}
> +
> +static const struct of_device_id sun55i_usb3_pcie_phy_of_match[] = {
> +	{ .compatible = "allwinner,sun55i-a523-usb3-pcie-phy" },

Please run scripts/checkpatch.pl on the patches and fix reported
warnings. After that, run also 'scripts/checkpatch.pl --strict' on the
patches and (probably) fix more warnings. Some warnings can be ignored,
especially from --strict run, but the code here looks like it needs a
fix. Feel free to get in touch if the warning is not clear.

> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, sun55i_usb3_pcie_phy_of_match);
> +
> +static struct platform_driver sun55i_usb3_pcie_phy_driver = {
> +	.probe	= sun55i_usb3_pcie_phy_probe,
> +	.driver = {
> +		.of_match_table	= sun55i_usb3_pcie_phy_of_match,
> +		.name  = "sun55i-usb3-pcie-phy",
> +	}
> +};
> +module_platform_driver(sun55i_usb3_pcie_phy_driver);
> +
> +MODULE_DESCRIPTION("Allwinner A523 USB3/PCIe phy driver");
> +MODULE_AUTHOR("Mikhail Kalashnikov <iuncuim@gmail.com>");
> +MODULE_LICENSE("GPL");


Best regards,
Krzysztof

Re: [PATCH 3/7] phy: sun4i-usb: a523: add support for the USB2 PHY

[Andre Przywara]

On Sat, 16 Aug 2025 16:46:56 +0800
iuncuim <iuncuim@gmail.com> wrote:

Hi Mikhail,

many thanks for posting these patches, that's a nice surprise to see
this moving forward!

I think there are some issues with this series, but we can surely iron
those out.

> From: Mikhail Kalashnikov <iuncuim@gmail.com>
> 
> Previously, USB PHY was compatible with D1 and did not require
> separatedata options. But now we need to add a third PHY, which makes it
> incompatible. The third PHY is used together with USB3/PCIe combophy with
> DWC3 controller.

It is really used together? I think on IRC we lately established that
the USB2.0 and USB3.0 parts are somewhat independent, and I think the
Radxa board wires PHY1 to the D-/D+ pins of the USB3.0 socket, instead
of PHY2.

Regardless: this change would be a compatibility break: When a new
kernel with this change sees an old DT, it would bail out, because it
doesn't find the resources for the third PHY in the DT.

What I'd suggest instead is to drop the hardcoded assumption about the
number of PHYs, and instead just enumerate all "pmu<x>" cells in
reg-names. That would work with both old and new DTs, and then we can
also keep the fallback compatible name in the DT, to allow new DTs on
older kernels (for instance a U-Boot provided DT on a stable kernel).

As an added benefit, it would make future enablement easier, as we are
more likely to find a matching compatible string, even when the number
of PHYs differ.

Cheers,
Andre

> In the BSP code, the third PHY requires a separate glue
> driver, but it seems that it is not needed.





> 
> Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
> ---
>  drivers/phy/allwinner/phy-sun4i-usb.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
> index 8873aed3a..bb79339f2 100644
> --- a/drivers/phy/allwinner/phy-sun4i-usb.c
> +++ b/drivers/phy/allwinner/phy-sun4i-usb.c
> @@ -1025,6 +1025,15 @@ static const struct sun4i_usb_phy_cfg sun50i_h616_cfg = {
>  	.siddq_in_base = true,
>  };
>  
> +static const struct sun4i_usb_phy_cfg sun55i_a523_cfg = {
> +	.num_phys = 3,
> +	.phyctl_offset = REG_PHYCTL_A33,
> +	.dedicated_clocks = true,
> +	.hci_phy_ctl_clear = PHY_CTL_SIDDQ,
> +	.phy0_dual_route = true,
> +	.siddq_in_base = true,
> +};
> +
>  static const struct of_device_id sun4i_usb_phy_of_match[] = {
>  	{ .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg },
>  	{ .compatible = "allwinner,sun5i-a13-usb-phy", .data = &sun5i_a13_cfg },
> @@ -1041,6 +1050,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
>  	  .data = &sun50i_a64_cfg},
>  	{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = &sun50i_h6_cfg },
>  	{ .compatible = "allwinner,sun50i-h616-usb-phy", .data = &sun50i_h616_cfg },
> +	{ .compatible = "allwinner,sun55i-a523-usb-phy", .data = &sun55i_a523_cfg },
>  	{ .compatible = "allwinner,suniv-f1c100s-usb-phy",
>  	  .data = &suniv_f1c100s_cfg },
>  	{ },

Re: [PATCH 2/7] arm64: dts: allwinner: a523: add third usb2 phy

[Andre Przywara]

On Sat, 16 Aug 2025 11:31:12 +0200
Krzysztof Kozlowski <krzk@kernel.org> wrote:

> On 16/08/2025 10:46, iuncuim wrote:
> > From: Mikhail Kalashnikov <iuncuim@gmail.com>
> > 
> > It seems that there are actually three usb2 phys in the processor, which
> > makes it incompatible with D1.
> > The third phy is used together with USB3/PCIe combophy with DWC3
> > controller. In the BSP code, the third PHY requires a separate glue
> > driver, but it seems that it is not needed.
> > According to the BSP code, the third phy does not have a reset line; the
> > only reset is declared in the DWC3 node, but none of this is documented.
> > Since sun4i-usb-phy driver requires a reset, I added RST_BUS_3 here.
> > 
> > Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
> > ---
> >  .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 21 ++++++++++++-------
> >  1 file changed, 13 insertions(+), 8 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
> > index 6b6f2296b..e4ed4fa82 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
> > +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
> > @@ -503,22 +503,27 @@ usb_otg: usb@4100000 {
> >  		};
> >  
> >  		usbphy: phy@4100400 {
> > -			compatible = "allwinner,sun55i-a523-usb-phy",
> > -				     "allwinner,sun20i-d1-usb-phy";
> > +			compatible = "allwinner,sun55i-a523-usb-phy";  
> 
> 
> That's potential break of all users. Also, having third phy (so
> additional piece) is not making things incompatible.

Yes, we would want to keep the fallback, to allow newer DTs working on
older kernel. As the Linux driver is implemented right now, it's not
fully compatible, since it ties the number of PHYs to the compatible
string - but that's a Linux implementation choice, not something really
related to the binding. And as I replied on the driver patch, that
breaks anyway, and I think we can change it there to preserve
compatibility, and make everyone happy: newer DTs on older kernels,
older DTs on newer kernels, and all working within the kernel's
capability.

Oh, and it looks like there are whitespace issues in the patch ...

Cheers,
Andre

Re: [PATCH 5/7] arm64: dts: allwinner: a523: add USB3.0 phy node

[Andre Przywara]

On Sat, 16 Aug 2025 16:46:58 +0800
iuncuim <iuncuim@gmail.com> wrote:

Hi,

> From: Mikhail Kalashnikov <iuncuim@gmail.com>
> 
> After adding the phy driver, we can also add phy node. In addition to the
> clk and reset lines, the power domain PD_PCIE is declared in this node
> according to the bsp dtb. So let's mention it. 
> Currently, phy driver does not support role selection and only works in
> USB3.0 mode.

That's the current limitation of the proposed Linux driver, but should
not affect the binding or DT:

> 
> Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
> ---
>  arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
> index e4ed4fa82..233365496 100644
> --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
> @@ -606,6 +606,16 @@ mdio0: mdio {
>  			};
>  		};
>  
> +		combophy: phy@4f00000 {
> +			compatible = "allwinner,sun55i-a523-usb3-pcie-phy";
> +			reg = <0x04f00000 0x100000>;
> +			clocks = <&ccu CLK_USB3>;

Will we need more clocks (or resets) when supporting PCIe later? If
yes, we should add them already now, even if they are not used by the
current driver.

> +			resets = <&ccu RST_BUS_PCIE_USB3>;
> +			#phy-cells = <0>;

I think we should use one PHY cell here, to allow users to select the
PHY path they need. A USB3.0-only driver implementation could choose to
ignore it, or require the number to be 0 only, rejecting anything else.
But this way we keep compatibility with newer DTs.

Cheers,
Andre

> +			power-domains = <&pck600 PD_PCIE>;
> +			status = "disabled";
> +		};
> +
>  		ppu: power-controller@7001400 {
>  			compatible = "allwinner,sun55i-a523-ppu";
>  			reg = <0x07001400 0x400>;

Re: [PATCH 6/7] arm64: dts: allwinner: a523: add DWC3 USB3.0 node

[Andre Przywara]

On Sat, 16 Aug 2025 16:46:59 +0800
iuncuim <iuncuim@gmail.com> wrote:

Hi,

> From: Mikhail Kalashnikov <iuncuim@gmail.com>
> 
> After adding the phy bindings, we can also add dwc3 node, which uses the
> previously added usbphy2 and part of usb3 from combophy.
> All settings declared in dwc3 node are obtained from the x96qproplus' dtb.
> BSP contains an additional glue driver for dwc3, but it seems that it is
> not needed.
> 
> Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
> ---
>  .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 21 +++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
> index 233365496..ec170888a 100644
> --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
> @@ -606,6 +606,27 @@ mdio0: mdio {
>  			};
>  		};
>  
> +		dwc3: usb@4d00000 {
> +			compatible = "snps,dwc3";

Wouldn't we need an A523 specific compatible string first?

> +			reg = <0x04d00000 0x100000>;
> +			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> +			dr_mode = "host";
> +			clocks = <&ccu CLK_MBUS_USB3>, <&ccu CLK_USB3>,
> +				 <&ccu CLK_USB2>, <&ccu CLK_USB3_SUSPEND>;
> +			clock-names = "bus_clk", "ref_clk3", "ref_clk2", "suspend";

How does this work, exactly? I see "bus_clk" (deprecated, should be
"bus_early") and "suspend" in the bindings and the Linux driver, but
where do ref_clk3 and ref_clk2 come from, and more importantly who is
going to use them? IIUC, the binding hints that certain implementations
could need more clocks, but then it's their responsibility to parse and
enable them, in platform specific glue code, I think.



> +			maximum-speed = "super-speed";
> +			phy_type = "utmi";
> +			snps,dis_enblslpm_quirk;
> +			snps,dis-u1-entry-quirk;
> +			snps,dis-u2-entry-quirk;
> +			snps,dis_u3_susphy_quirk;
> +			snps,dis_u2_susphy_quirk;
> +			snps,dis_rxdet_inp3_quirk;
> +			phys = <&usbphy 2>, <&combophy>;

Related to my comment on the other DT patch, this should be
"<&combophy 0>" (with "#phy-cells = <1>;" in the PHY node, to be forward
compatible.

Cheers,
Andre


> +			phy-names = "usb2-phy", "usb3-phy";
> +			status = "disabled";
> +		};
> +
>  		combophy: phy@4f00000 {
>  			compatible = "allwinner,sun55i-a523-usb3-pcie-phy";
>  			reg = <0x04f00000 0x100000>;

Re: [PATCH 0/7] arm64: allwinner: a523: add USB3.0 support

[Rob Herring (Arm)]

On Sat, 16 Aug 2025 16:46:53 +0800, iuncuim wrote:
> From: Mikhail Kalashnikov <iuncuim@gmail.com>
> 
> This series is a draft and does not include patches for dt-bindings.
> The first series is necessary for testing on other devices and
> initiating discussion.
> 
> This series of patches adds USB 3.0 functionality for the
> A523/A527/H728/T527 processor.Most of the code is derived from the BSP,
>  as the datasheet does not fully describe this feature.
> 
> I have verified functionality on two of my boards, walnutpi 2b (t527)
> and x96qproplus (h728). When testing usb3.0 on x96qproplus, I get
> reconnections of my nvme, it looks like the port does not provide enough
>  current to work. I have encountered similar complaints from users of the
>   device on Android. In the case of walnutpi, there is no such problem.
> 
> Based on 6.17-rc1
> 
> Mikhail Kalashnikov (7):
>   clk: sunxi-ng: a523: add missing usb related clocks
>   arm64: dts: allwinner: a523: add third usb2 phy
>   phy: sun4i-usb: a523: add support for the USB2 PHY
>   phy: allwinner: a523: add USB3/PCIe PHY driver
>   arm64: dts: allwinner: a523: add USB3.0 phy node
>   arm64: dts: allwinner: a523: add DWC3 USB3.0 node
>   arm64: dts: allwinner: a523: activate USB3 for all boards
> 
>  .../arm64/boot/dts/allwinner/sun55i-a523.dtsi |  52 +++-
>  .../dts/allwinner/sun55i-a527-cubie-a5e.dts   |   8 +
>  .../dts/allwinner/sun55i-h728-x96qpro+.dts    |   8 +
>  .../dts/allwinner/sun55i-t527-avaota-a1.dts   |   8 +
>  drivers/clk/sunxi-ng/ccu-sun55i-a523.c        |  32 +++
>  drivers/clk/sunxi-ng/ccu-sun55i-a523.h        |   2 +-
>  drivers/phy/allwinner/Kconfig                 |   9 +
>  drivers/phy/allwinner/Makefile                |   1 +
>  drivers/phy/allwinner/phy-sun4i-usb.c         |  10 +
>  drivers/phy/allwinner/phy-sun55i-usb3-pcie.c  | 267 ++++++++++++++++++
>  include/dt-bindings/clock/sun55i-a523-ccu.h   |   4 +
>  11 files changed, 392 insertions(+), 9 deletions(-)
>  create mode 100644 drivers/phy/allwinner/phy-sun55i-usb3-pcie.c
> 
> --
> 2.50.1
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


This patch series was applied (using b4) to base:
 Base: attempting to guess base-commit...
 Base: remotes/korg/master-95-g90d970cade8e (exact match)

If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)

New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/allwinner/' for 20250816084700.569524-1-iuncuim@gmail.com:

arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dtb: phy@4100400 (allwinner,sun55i-a523-usb-phy): clock-names: ['usb0_phy', 'usb1_phy', 'usb2_phy'] is too long
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dtb: phy@4100400 (allwinner,sun55i-a523-usb-phy): clocks: [[5], [5], [2, 179]] is too long
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dtb: phy@4100400 (allwinner,sun55i-a523-usb-phy): compatible: 'oneOf' conditional failed, one must be fixed:
	['allwinner,sun55i-a523-usb-phy'] is too short
	'allwinner,sun55i-a523-usb-phy' is not one of ['allwinner,sun20i-d1-usb-phy', 'allwinner,sun50i-a64-usb-phy']
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dtb: phy@4100400 (allwinner,sun55i-a523-usb-phy): reg: [[68158464, 256], [68163584, 256], [69208064, 256], [81788928, 256]] is too long
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dtb: phy@4100400 (allwinner,sun55i-a523-usb-phy): reg-names: ['phy_ctrl', 'pmu0', 'pmu1', 'pmu2'] is too long
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dtb: phy@4100400 (allwinner,sun55i-a523-usb-phy): reset-names: ['usb0_reset', 'usb1_reset', 'usb2_reset'] is too long
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dtb: phy@4100400 (allwinner,sun55i-a523-usb-phy): clock-names: ['usb0_phy', 'usb1_phy', 'usb2_phy'] is too long
arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dtb: phy@4100400 (allwinner,sun55i-a523-usb-phy): resets: [[2, 49], [2, 50], [2, 56]] is too long
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dtb: phy@4100400 (allwinner,sun55i-a523-usb-phy): clocks: [[5], [5], [2, 179]] is too long
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dtb: phy@4100400 (allwinner,sun55i-a523-usb-phy): compatible: 'oneOf' conditional failed, one must be fixed:
	['allwinner,sun55i-a523-usb-phy'] is too short
	'allwinner,sun55i-a523-usb-phy' is not one of ['allwinner,sun20i-d1-usb-phy', 'allwinner,sun50i-a64-usb-phy']
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dtb: phy@4100400 (allwinner,sun55i-a523-usb-phy): reg: [[68158464, 256], [68163584, 256], [69208064, 256], [81788928, 256]] is too long
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dtb: phy@4100400 (allwinner,sun55i-a523-usb-phy): reg-names: ['phy_ctrl', 'pmu0', 'pmu1', 'pmu2'] is too long
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dtb: phy@4100400 (allwinner,sun55i-a523-usb-phy): reset-names: ['usb0_reset', 'usb1_reset', 'usb2_reset'] is too long
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dtb: phy@4100400 (allwinner,sun55i-a523-usb-phy): resets: [[2, 49], [2, 50], [2, 56]] is too long
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dtb: phy@4100400 (allwinner,sun55i-a523-usb-phy): clock-names: ['usb0_phy', 'usb1_phy', 'usb2_phy'] is too long
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dtb: phy@4100400 (allwinner,sun55i-a523-usb-phy): clocks: [[5], [5], [2, 179]] is too long
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dtb: phy@4100400 (allwinner,sun55i-a523-usb-phy): compatible: 'oneOf' conditional failed, one must be fixed:
	['allwinner,sun55i-a523-usb-phy'] is too short
	'allwinner,sun55i-a523-usb-phy' is not one of ['allwinner,sun20i-d1-usb-phy', 'allwinner,sun50i-a64-usb-phy']
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dtb: phy@4100400 (allwinner,sun55i-a523-usb-phy): reg: [[68158464, 256], [68163584, 256], [69208064, 256], [81788928, 256]] is too long
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dtb: phy@4100400 (allwinner,sun55i-a523-usb-phy): reg-names: ['phy_ctrl', 'pmu0', 'pmu1', 'pmu2'] is too long
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dtb: phy@4100400 (allwinner,sun55i-a523-usb-phy): reset-names: ['usb0_reset', 'usb1_reset', 'usb2_reset'] is too long
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dtb: phy@4100400 (allwinner,sun55i-a523-usb-phy): resets: [[2, 49], [2, 50], [2, 56]] is too long
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dtb: phy@4100400 (allwinner,sun55i-a523-usb-phy): clock-names: ['usb0_phy', 'usb1_phy', 'usb2_phy'] is too long
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dtb: phy@4100400 (allwinner,sun55i-a523-usb-phy): clocks: [[5], [5], [2, 179]] is too long
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dtb: phy@4100400 (allwinner,sun55i-a523-usb-phy): compatible: 'oneOf' conditional failed, one must be fixed:
	['allwinner,sun55i-a523-usb-phy'] is too short
	'allwinner,sun55i-a523-usb-phy' is not one of ['allwinner,sun20i-d1-usb-phy', 'allwinner,sun50i-a64-usb-phy']
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dtb: phy@4100400 (allwinner,sun55i-a523-usb-phy): reg: [[68158464, 256], [68163584, 256], [69208064, 256], [81788928, 256]] is too long
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dtb: phy@4100400 (allwinner,sun55i-a523-usb-phy): reg-names: ['phy_ctrl', 'pmu0', 'pmu1', 'pmu2'] is too long
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dtb: phy@4100400 (allwinner,sun55i-a523-usb-phy): reset-names: ['usb0_reset', 'usb1_reset', 'usb2_reset'] is too long
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dtb: phy@4100400 (allwinner,sun55i-a523-usb-phy): resets: [[2, 49], [2, 50], [2, 56]] is too long
	from schema $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dtb: /soc/phy@4f00000: failed to match any schema with compatible: ['allwinner,sun55i-a523-usb3-pcie-phy']
arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dtb: /soc/phy@4f00000: failed to match any schema with compatible: ['allwinner,sun55i-a523-usb3-pcie-phy']
arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dtb: /soc/phy@4f00000: failed to match any schema with compatible: ['allwinner,sun55i-a523-usb3-pcie-phy']
arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dtb: /soc/phy@4f00000: failed to match any schema with compatible: ['allwinner,sun55i-a523-usb3-pcie-phy']

Re: [PATCH 4/7] phy: allwinner: a523: add USB3/PCIe PHY driver

[Philipp Zabel]

On Sa, 2025-08-16 at 16:46 +0800, iuncuim wrote:
> From: Mikhail Kalashnikov <iuncuim@gmail.com>
> 
> The A523 family of processors features a combophy for USB 3.0 and PCIe,
> developed by Innosilicon. Simultaneous operation of both interfaces is
> not supported by design.
> Currently, the driver only adds support for USB 3.0. PCIe support is
> currently unavailable and will be added later.
> All data on phy configuration is taken from the manufacturer's BSP driver.
> 
> Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
> ---
>  drivers/phy/allwinner/Kconfig                |   9 +
>  drivers/phy/allwinner/Makefile               |   1 +
>  drivers/phy/allwinner/phy-sun55i-usb3-pcie.c | 267 +++++++++++++++++++
>  3 files changed, 277 insertions(+)
>  create mode 100644 drivers/phy/allwinner/phy-sun55i-usb3-pcie.c
> 
> diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig
> index fb584518b..af2a82e51 100644
> --- a/drivers/phy/allwinner/Kconfig
> +++ b/drivers/phy/allwinner/Kconfig
> @@ -57,3 +57,12 @@ config PHY_SUN50I_USB3
>  	  part of Allwinner H6 SoC.
>  
>  	  This driver controls each individual USB 2+3 host PHY combo.
> +
> +config PHY_SUN55I_USB3_PCIE
> +	tristate "Allwinner A523 Innosilicon USB3/PCIe Combophy Driver"
> +	depends on ARCH_SUNXI || COMPILE_TEST
> +	depends on RESET_CONTROLLER

This dependency is not necessary. The reset controller API is stubbed
out in case  RESET_CONTROLLER is disabled.

ARCH_SUNXI selects ARCH_HAS_RESET_CONTROLLER, which default-enables
RESET_CONTROLLER.

> +	select GENERIC_PHY
> +	help
> +	  Enable this to support the Allwinner PCIe/USB3.0 combo PHY
> +	  with Innosilicon IP block founded in A523/A527/H728/T527 SOC
> diff --git a/drivers/phy/allwinner/Makefile b/drivers/phy/allwinner/Makefile
> index bd74901a1..5948a27ef 100644
> --- a/drivers/phy/allwinner/Makefile
> +++ b/drivers/phy/allwinner/Makefile
> @@ -3,3 +3,4 @@ obj-$(CONFIG_PHY_SUN4I_USB)		+= phy-sun4i-usb.o
>  obj-$(CONFIG_PHY_SUN6I_MIPI_DPHY)	+= phy-sun6i-mipi-dphy.o
>  obj-$(CONFIG_PHY_SUN9I_USB)		+= phy-sun9i-usb.o
>  obj-$(CONFIG_PHY_SUN50I_USB3)		+= phy-sun50i-usb3.o
> +obj-$(CONFIG_PHY_SUN55I_USB3_PCIE)		+= phy-sun55i-usb3-pcie.o
> diff --git a/drivers/phy/allwinner/phy-sun55i-usb3-pcie.c b/drivers/phy/allwinner/phy-sun55i-usb3-pcie.c
> new file mode 100644
> index 000000000..905c54a67
> --- /dev/null
> +++ b/drivers/phy/allwinner/phy-sun55i-usb3-pcie.c
> @@ -0,0 +1,267 @@
[...]
> +static int sun55i_usb3_pcie_phy_init(struct phy *_phy)
> +{
> +	struct sun55i_usb3_pcie_phy *phy = phy_get_drvdata(_phy);
> +
> +	sun55i_usb3_phy_open(phy);

Given that sun55i_usb3_pcie_phy_exit() asserts the reset and disables
the clock, why isn't the clock enabled and the reset deasserted here?

As is, it looks like the code in sun55i_usb3_phy_open() could be just
folded into sun55i_usb3_pcie_phy_init().

> +	return 0;
> +}
[...]
> +static int sun55i_usb3_pcie_phy_probe(struct platform_device *pdev)
> +{
> +	struct sun55i_usb3_pcie_phy *phy;
> +	struct device *dev = &pdev->dev;
> +	struct phy_provider *phy_provider;
> +	int ret;
> +
> +	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
> +	if (!phy)
> +		return -ENOMEM;
> +
> +	phy->dev = dev;
> +	phy->clk = devm_clk_get(dev, NULL);
> +	if (IS_ERR(phy->clk)) {
> +		if (PTR_ERR(phy->clk) != -EPROBE_DEFER)
> +			dev_err(dev, "failed to get phy clock\n");
> +		return PTR_ERR(phy->clk);
> +	}
> +
> +	phy->reset = devm_reset_control_get(dev, NULL);

Please use devm_reset_control_get_exclusive() directly.

> +	if (IS_ERR(phy->reset)) {
> +		dev_err(dev, "failed to get reset control\n");

Consider using dev_err_probe().

regards
Philipp

Re: [PATCH 5/7] arm64: dts: allwinner: a523: add USB3.0 phy node

[Chen-Yu Tsai]

On Sat, Aug 16, 2025 at 3:52 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> On Sat, 16 Aug 2025 16:46:58 +0800
> iuncuim <iuncuim@gmail.com> wrote:
>
> Hi,
>
> > From: Mikhail Kalashnikov <iuncuim@gmail.com>
> >
> > After adding the phy driver, we can also add phy node. In addition to the
> > clk and reset lines, the power domain PD_PCIE is declared in this node
> > according to the bsp dtb. So let's mention it.
> > Currently, phy driver does not support role selection and only works in
> > USB3.0 mode.
>
> That's the current limitation of the proposed Linux driver, but should
> not affect the binding or DT:
>
> >
> > Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
> > ---
> >  arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
> > index e4ed4fa82..233365496 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
> > +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
> > @@ -606,6 +606,16 @@ mdio0: mdio {
> >                       };
> >               };
> >
> > +             combophy: phy@4f00000 {
> > +                     compatible = "allwinner,sun55i-a523-usb3-pcie-phy";
> > +                     reg = <0x04f00000 0x100000>;
> > +                     clocks = <&ccu CLK_USB3>;
>
> Will we need more clocks (or resets) when supporting PCIe later? If
> yes, we should add them already now, even if they are not used by the
> current driver.
>
> > +                     resets = <&ccu RST_BUS_PCIE_USB3>;
> > +                     #phy-cells = <0>;
>
> I think we should use one PHY cell here, to allow users to select the
> PHY path they need. A USB3.0-only driver implementation could choose to
> ignore it, or require the number to be 0 only, rejecting anything else.
> But this way we keep compatibility with newer DTs.

Agreed. It seems this is the common case for combined PHYs. The last
cell tells which type of PHY is to be used.

ChenYu

> Cheers,
> Andre
>
> > +                     power-domains = <&pck600 PD_PCIE>;
> > +                     status = "disabled";
> > +             };
> > +
> >               ppu: power-controller@7001400 {
> >                       compatible = "allwinner,sun55i-a523-ppu";
> >                       reg = <0x07001400 0x400>;
>

Re: [PATCH 4/7] phy: allwinner: a523: add USB3/PCIe PHY driver

[Chukun Pan]

Hi,

> --- a/drivers/phy/allwinner/Makefile
> +++ b/drivers/phy/allwinner/Makefile
> @@ -3,3 +3,4 @@ obj-$(CONFIG_PHY_SUN4I_USB)		+= phy-sun4i-usb.o
>  obj-$(CONFIG_PHY_SUN6I_MIPI_DPHY)	+= phy-sun6i-mipi-dphy.o
>  obj-$(CONFIG_PHY_SUN9I_USB)		+= phy-sun9i-usb.o
>  obj-$(CONFIG_PHY_SUN50I_USB3)		+= phy-sun50i-usb3.o
> +obj-$(CONFIG_PHY_SUN55I_USB3_PCIE)		+= phy-sun55i-usb3-pcie.o

Would it be better to call it phy-sun55i-combophy ?

> --- /dev/null
> +++ b/drivers/phy/allwinner/phy-sun55i-usb3-pcie.c
> ...
> +static int sun55i_usb3_pcie_phy_init(struct phy *_phy)
> +{
> +	struct sun55i_usb3_pcie_phy *phy = phy_get_drvdata(_phy);
> +
> +	sun55i_usb3_phy_open(phy);

Maybe we need to add `case PHY_TYPE_USB3:`
And use <&combophy PHY_TYPE_USB3> in the DT

> +
> +	return 0;
> +}
> ...

> +static const struct of_device_id sun55i_usb3_pcie_phy_of_match[] = {
> +	{ .compatible = "allwinner,sun55i-a523-usb3-pcie-phy" },

Would it be better to use "allwinner,sun55i-a523-combophy" as
the compatible?

> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, sun55i_usb3_pcie_phy_of_match);

Thanks,
Chukun