[PATCH v3 0/6] clock: imx95: Add LVDS/DISPLAY CSR for i.MX94

[PATCH v3 0/6] clock: imx95: Add LVDS/DISPLAY CSR for i.MX94

[Peng Fan]

Similar to i.MX95, i.MX94 also has LVDS/DISPLAY CSR to provide
clock gate for LVDS and DISPLAY Controller. So following same approach
to add the support, as what have been done for i.MX95.

Patch 1 is to add the binding doc.
Patch 2 is fixes when supporting i.MX94, but the issues are
also exposed to i.MX95 even not triggered. No need to rush the
two patches for 6.16.
Patch 3 and 4 is to add the clk driver. Patch 3 is almost picked from
NXP downstream with a minor update. Patch 4 is modified from NXP
downstream with a few minor patches merged and updated.
Patch 5 is the dts part to give reviewer a whole view on how it is used.

Thanks for Frank Li helping do NXP internal review for the patchset.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
Changes in v3:
- Add R-b from Abel and Frank
- Correct License in patch 1 to add dt-binding
- Address Frank's comments in patch 3, 4 for compatible strings order.
- Add a patch to update MAINTAINERS entry for i.MX clock entry
- Link to v2: https://lore.kernel.org/r/20250703-imx95-blk-ctl-7-1-v2-0-b378ad796330@nxp.com

Changes in v2:
- Correct compatible string order in patch 1 which add dt-binding
- Sort the order of of_device_id in patch 4 which add i.MX94 driver
- Update ldb pll div7 node name in patch 5 which add dts nodes
- Link to v1: https://lore.kernel.org/r/20250701-imx95-blk-ctl-7-1-v1-0-00db23bd8876@nxp.com

---
Laurentiu Palcu (1):
      clk: imx95-blk-ctl: Fix synchronous abort

Peng Fan (4):
      dt-bindings: clock: Add support for i.MX94 LVDS/DISPLAY CSR
      clk: imx95-blk-ctl: Add clock for i.MX94 LVDS/Display CSR
      MAINTAINERS: Update i.MX Clock Entry
      arm64: dts: imx943: Add LVDS/DISPLAY CSR nodes

Sandor Yu (1):
      clk: imx95-blk-ctl: Rename lvds and displaymix csr blk

 .../bindings/clock/nxp,imx95-blk-ctl.yaml          |  2 +
 MAINTAINERS                                        |  4 +-
 arch/arm64/boot/dts/freescale/imx943.dtsi          | 34 ++++++++
 drivers/clk/imx/clk-imx95-blk-ctl.c                | 93 +++++++++++++++++-----
 include/dt-bindings/clock/nxp,imx94-clock.h        | 13 +++
 5 files changed, 122 insertions(+), 24 deletions(-)
---
base-commit: fa643a3813b6df6356b86e1c8061e2dfd0c99746
change-id: 20250701-imx95-blk-ctl-7-1-e9f82be61980

Best regards,
-- 
Peng Fan <peng.fan@nxp.com>

[PATCH v3 1/6] dt-bindings: clock: Add support for i.MX94 LVDS/DISPLAY CSR

[Peng Fan]

Add i.MX94 LVDS/DISPLAY CSR compatible string.

Add clock index for the two CSRs.

Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 .../devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml        |  2 ++
 include/dt-bindings/clock/nxp,imx94-clock.h                 | 13 +++++++++++++
 2 files changed, 15 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml b/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
index d0291bfff23a27cb55683880fe3a1f8b3e2ada5a..27403b4c52d6219d31649d75539af93edae0f17d 100644
--- a/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
+++ b/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
@@ -13,6 +13,8 @@ properties:
   compatible:
     items:
       - enum:
+          - nxp,imx94-display-csr
+          - nxp,imx94-lvds-csr
           - nxp,imx95-camera-csr
           - nxp,imx95-display-csr
           - nxp,imx95-hsio-blk-ctl
diff --git a/include/dt-bindings/clock/nxp,imx94-clock.h b/include/dt-bindings/clock/nxp,imx94-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..c4ba13352b99b4b13d4331450c78590cf6c1660c
--- /dev/null
+++ b/include/dt-bindings/clock/nxp,imx94-clock.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright 2025 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX94_H
+#define __DT_BINDINGS_CLOCK_IMX94_H
+
+#define IMX94_CLK_DISPMIX_CLK_SEL	0
+
+#define IMX94_CLK_DISPMIX_LVDS_CLK_GATE	0
+
+#endif /* __DT_BINDINGS_CLOCK_IMX94_H */

-- 
2.37.1

[PATCH v3 2/6] clk: imx95-blk-ctl: Fix synchronous abort

[Peng Fan]

From: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>

When enabling runtime PM for clock suppliers that also belong to a power
domain, the following crash is thrown:
error: synchronous external abort: 0000000096000010 [#1] PREEMPT SMP
Workqueue: events_unbound deferred_probe_work_func
pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
pc : clk_mux_get_parent+0x60/0x90
lr : clk_core_reparent_orphans_nolock+0x58/0xd8
  Call trace:
   clk_mux_get_parent+0x60/0x90
   clk_core_reparent_orphans_nolock+0x58/0xd8
   of_clk_add_hw_provider.part.0+0x90/0x100
   of_clk_add_hw_provider+0x1c/0x38
   imx95_bc_probe+0x2e0/0x3f0
   platform_probe+0x70/0xd8

Enabling runtime PM without explicitly resuming the device caused
the power domain cut off after clk_register() is called. As a result,
a crash happens when the clock hardware provider is added and attempts
to access the BLK_CTL register.

Fix this by using devm_pm_runtime_enable() instead of pm_runtime_enable()
and getting rid of the pm_runtime_disable() in the cleanup path.

Fixes: 5224b189462f ("clk: imx: add i.MX95 BLK CTL clk driver")
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx95-blk-ctl.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-imx95-blk-ctl.c
index cc2ee2be18195f0e05e911bcb26e284b1a894244..86bdcd21753102b7d160288e7b69bf73da5a5706 100644
--- a/drivers/clk/imx/clk-imx95-blk-ctl.c
+++ b/drivers/clk/imx/clk-imx95-blk-ctl.c
@@ -342,8 +342,10 @@ static int imx95_bc_probe(struct platform_device *pdev)
 	if (!clk_hw_data)
 		return -ENOMEM;
 
-	if (bc_data->rpm_enabled)
-		pm_runtime_enable(&pdev->dev);
+	if (bc_data->rpm_enabled) {
+		devm_pm_runtime_enable(&pdev->dev);
+		pm_runtime_resume_and_get(&pdev->dev);
+	}
 
 	clk_hw_data->num = bc_data->num_clks;
 	hws = clk_hw_data->hws;
@@ -383,8 +385,10 @@ static int imx95_bc_probe(struct platform_device *pdev)
 		goto cleanup;
 	}
 
-	if (pm_runtime_enabled(bc->dev))
+	if (pm_runtime_enabled(bc->dev)) {
+		pm_runtime_put_sync(&pdev->dev);
 		clk_disable_unprepare(bc->clk_apb);
+	}
 
 	return 0;
 
@@ -395,9 +399,6 @@ static int imx95_bc_probe(struct platform_device *pdev)
 		clk_hw_unregister(hws[i]);
 	}
 
-	if (bc_data->rpm_enabled)
-		pm_runtime_disable(&pdev->dev);
-
 	return ret;
 }
 

-- 
2.37.1

[PATCH v3 3/6] clk: imx95-blk-ctl: Rename lvds and displaymix csr blk

[Peng Fan]

From: Sandor Yu <Sandor.yu@nxp.com>

Rename i.MX95 lvds and displaymix csr blk drvdata in order to add
support for i.MX943.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx95-blk-ctl.c | 30 +++++++++++++++---------------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-imx95-blk-ctl.c
index 86bdcd21753102b7d160288e7b69bf73da5a5706..c62d61c3444bd40fabcc0b50929584cc1724ae95 100644
--- a/drivers/clk/imx/clk-imx95-blk-ctl.c
+++ b/drivers/clk/imx/clk-imx95-blk-ctl.c
@@ -156,7 +156,7 @@ static const struct imx95_blk_ctl_dev_data camblk_dev_data = {
 	.clk_reg_offset = 0,
 };
 
-static const struct imx95_blk_ctl_clk_dev_data lvds_clk_dev_data[] = {
+static const struct imx95_blk_ctl_clk_dev_data imx95_lvds_clk_dev_data[] = {
 	[IMX95_CLK_DISPMIX_LVDS_PHY_DIV] = {
 		.name = "ldb_phy_div",
 		.parent_names = (const char *[]){ "ldbpll", },
@@ -213,21 +213,21 @@ static const struct imx95_blk_ctl_clk_dev_data lvds_clk_dev_data[] = {
 	},
 };
 
-static const struct imx95_blk_ctl_dev_data lvds_csr_dev_data = {
-	.num_clks = ARRAY_SIZE(lvds_clk_dev_data),
-	.clk_dev_data = lvds_clk_dev_data,
+static const struct imx95_blk_ctl_dev_data imx95_lvds_csr_dev_data = {
+	.num_clks = ARRAY_SIZE(imx95_lvds_clk_dev_data),
+	.clk_dev_data = imx95_lvds_clk_dev_data,
 	.clk_reg_offset = 0,
 };
 
-static const char * const disp_engine_parents[] = {
+static const char * const imx95_disp_engine_parents[] = {
 	"videopll1", "dsi_pll", "ldb_pll_div7"
 };
 
-static const struct imx95_blk_ctl_clk_dev_data dispmix_csr_clk_dev_data[] = {
+static const struct imx95_blk_ctl_clk_dev_data imx95_dispmix_csr_clk_dev_data[] = {
 	[IMX95_CLK_DISPMIX_ENG0_SEL] = {
 		.name = "disp_engine0_sel",
-		.parent_names = disp_engine_parents,
-		.num_parents = ARRAY_SIZE(disp_engine_parents),
+		.parent_names = imx95_disp_engine_parents,
+		.num_parents = ARRAY_SIZE(imx95_disp_engine_parents),
 		.reg = 0,
 		.bit_idx = 0,
 		.bit_width = 2,
@@ -236,8 +236,8 @@ static const struct imx95_blk_ctl_clk_dev_data dispmix_csr_clk_dev_data[] = {
 	},
 	[IMX95_CLK_DISPMIX_ENG1_SEL] = {
 		.name = "disp_engine1_sel",
-		.parent_names = disp_engine_parents,
-		.num_parents = ARRAY_SIZE(disp_engine_parents),
+		.parent_names = imx95_disp_engine_parents,
+		.num_parents = ARRAY_SIZE(imx95_disp_engine_parents),
 		.reg = 0,
 		.bit_idx = 2,
 		.bit_width = 2,
@@ -246,9 +246,9 @@ static const struct imx95_blk_ctl_clk_dev_data dispmix_csr_clk_dev_data[] = {
 	}
 };
 
-static const struct imx95_blk_ctl_dev_data dispmix_csr_dev_data = {
-	.num_clks = ARRAY_SIZE(dispmix_csr_clk_dev_data),
-	.clk_dev_data = dispmix_csr_clk_dev_data,
+static const struct imx95_blk_ctl_dev_data imx95_dispmix_csr_dev_data = {
+	.num_clks = ARRAY_SIZE(imx95_dispmix_csr_clk_dev_data),
+	.clk_dev_data = imx95_dispmix_csr_clk_dev_data,
 	.clk_reg_offset = 0,
 };
 
@@ -469,8 +469,8 @@ static const struct dev_pm_ops imx95_bc_pm_ops = {
 static const struct of_device_id imx95_bc_of_match[] = {
 	{ .compatible = "nxp,imx95-camera-csr", .data = &camblk_dev_data },
 	{ .compatible = "nxp,imx95-display-master-csr", },
-	{ .compatible = "nxp,imx95-lvds-csr", .data = &lvds_csr_dev_data },
-	{ .compatible = "nxp,imx95-display-csr", .data = &dispmix_csr_dev_data },
+	{ .compatible = "nxp,imx95-display-csr", .data = &imx95_dispmix_csr_dev_data },
+	{ .compatible = "nxp,imx95-lvds-csr", .data = &imx95_lvds_csr_dev_data },
 	{ .compatible = "nxp,imx95-hsio-blk-ctl", .data = &hsio_blk_ctl_dev_data },
 	{ .compatible = "nxp,imx95-vpu-csr", .data = &vpublk_dev_data },
 	{ .compatible = "nxp,imx95-netcmix-blk-ctrl", .data = &netcmix_dev_data},

-- 
2.37.1

[PATCH v3 4/6] clk: imx95-blk-ctl: Add clock for i.MX94 LVDS/Display CSR

[Peng Fan]

i.MX94 BLK CTL LVDS CSR's LVDS_PHY_CLOCK_CONTRL register controls the clock
gating logic of LVDS units. Display CSR's DISPLAY_ENGINES_CLOCK_CONTROL
register controls the selection of the clock feeding the display engine.

Add clock gate support for the two CSRs.

Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx95-blk-ctl.c | 50 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 49 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-imx95-blk-ctl.c
index c62d61c3444bd40fabcc0b50929584cc1724ae95..7e88877a624518cc679cfb3bf673418207a1bc74 100644
--- a/drivers/clk/imx/clk-imx95-blk-ctl.c
+++ b/drivers/clk/imx/clk-imx95-blk-ctl.c
@@ -1,8 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  */
 
+#include <dt-bindings/clock/nxp,imx94-clock.h>
 #include <dt-bindings/clock/nxp,imx95-clock.h>
 #include <linux/clk.h>
 #include <linux/clk-provider.h>
@@ -300,6 +301,51 @@ static const struct imx95_blk_ctl_dev_data hsio_blk_ctl_dev_data = {
 	.clk_reg_offset = 0,
 };
 
+static const struct imx95_blk_ctl_clk_dev_data imx94_lvds_clk_dev_data[] = {
+	[IMX94_CLK_DISPMIX_LVDS_CLK_GATE] = {
+		.name = "lvds_clk_gate",
+		.parent_names = (const char *[]){ "ldbpll", },
+		.num_parents = 1,
+		.reg = 0,
+		.bit_idx = 1,
+		.bit_width = 1,
+		.type = CLK_GATE,
+		.flags = CLK_SET_RATE_PARENT,
+		.flags2 = CLK_GATE_SET_TO_DISABLE,
+	},
+};
+
+static const struct imx95_blk_ctl_dev_data imx94_lvds_csr_dev_data = {
+	.num_clks = ARRAY_SIZE(imx94_lvds_clk_dev_data),
+	.clk_dev_data = imx94_lvds_clk_dev_data,
+	.clk_reg_offset = 0,
+	.rpm_enabled = true,
+};
+
+static const char * const imx94_disp_engine_parents[] = {
+	"disppix", "ldb_pll_div7"
+};
+
+static const struct imx95_blk_ctl_clk_dev_data imx94_dispmix_csr_clk_dev_data[] = {
+	[IMX94_CLK_DISPMIX_CLK_SEL] = {
+		.name = "disp_clk_sel",
+		.parent_names = imx94_disp_engine_parents,
+		.num_parents = ARRAY_SIZE(imx94_disp_engine_parents),
+		.reg = 0,
+		.bit_idx = 1,
+		.bit_width = 1,
+		.type = CLK_MUX,
+		.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct imx95_blk_ctl_dev_data imx94_dispmix_csr_dev_data = {
+	.num_clks = ARRAY_SIZE(imx94_dispmix_csr_clk_dev_data),
+	.clk_dev_data = imx94_dispmix_csr_clk_dev_data,
+	.clk_reg_offset = 0,
+	.rpm_enabled = true,
+};
+
 static int imx95_bc_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -467,6 +513,8 @@ static const struct dev_pm_ops imx95_bc_pm_ops = {
 };
 
 static const struct of_device_id imx95_bc_of_match[] = {
+	{ .compatible = "nxp,imx94-display-csr", .data = &imx94_dispmix_csr_dev_data },
+	{ .compatible = "nxp,imx94-lvds-csr", .data = &imx94_lvds_csr_dev_data },
 	{ .compatible = "nxp,imx95-camera-csr", .data = &camblk_dev_data },
 	{ .compatible = "nxp,imx95-display-master-csr", },
 	{ .compatible = "nxp,imx95-display-csr", .data = &imx95_dispmix_csr_dev_data },

-- 
2.37.1

[PATCH v3 5/6] MAINTAINERS: Update i.MX Clock Entry

[Peng Fan]

Update file match pattern to include nxp,imx* and fsl,imx*.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 MAINTAINERS | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 92e9d8c7708ff4874efaa9727814ad7f1c9f6b0c..8be3e0fbe72b82dc398046d415481d6cfd09c78b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -18073,9 +18073,9 @@ L:	linux-clk@vger.kernel.org
 L:	imx@lists.linux.dev
 S:	Maintained
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux.git clk/imx
-F:	Documentation/devicetree/bindings/clock/imx*
+F:	Documentation/devicetree/bindings/clock/*imx*
 F:	drivers/clk/imx/
-F:	include/dt-bindings/clock/imx*
+F:	include/dt-bindings/clock/*imx*
 
 NXP PF8100/PF8121A/PF8200 PMIC REGULATOR DEVICE DRIVER
 M:	Jagan Teki <jagan@amarulasolutions.com>

-- 
2.37.1

[PATCH v3 6/6] arm64: dts: imx943: Add LVDS/DISPLAY CSR nodes

[Peng Fan]

Add nodes for LVDS/DISPLAY CSR.

Add clock-ldb-pll-div7 node which is used for clock source of DISPLAY CSR.

Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx943.dtsi | 34 +++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi
index 45b8da758e87771c0775eb799ce2da3aac37c060..657c81b6016f21270a1b13d636af72c14ab4f8ef 100644
--- a/arch/arm64/boot/dts/freescale/imx943.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx943.dtsi
@@ -3,6 +3,8 @@
  * Copyright 2025 NXP
  */
 
+#include <dt-bindings/clock/nxp,imx94-clock.h>
+
 #include "imx94.dtsi"
 
 / {
@@ -145,4 +147,36 @@ l3_cache: l3-cache {
 			cache-unified;
 		};
 	};
+
+	clock-ldb-pll-div7 {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&scmi_clk IMX94_CLK_LDBPLL>;
+		clock-div = <7>;
+		clock-mult = <1>;
+		clock-output-names = "ldb_pll_div7";
+	};
+
+	soc {
+		dispmix_csr: syscon@4b010000 {
+			compatible = "nxp,imx94-display-csr", "syscon";
+			reg = <0x0 0x4b010000 0x0 0x10000>;
+			clocks = <&scmi_clk IMX94_CLK_DISPAPB>;
+			#clock-cells = <1>;
+			power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
+			assigned-clocks = <&scmi_clk IMX94_CLK_DISPAXI>,
+					  <&scmi_clk IMX94_CLK_DISPAPB>;
+			assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>,
+						 <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
+			assigned-clock-rates = <400000000>,  <133333333>;
+		};
+
+		lvds_csr: syscon@4b0c0000 {
+			compatible = "nxp,imx94-lvds-csr", "syscon";
+			reg = <0x0 0x4b0c0000 0x0 0x10000>;
+			clocks = <&scmi_clk IMX94_CLK_DISPAPB>;
+			#clock-cells = <1>;
+			power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
+		};
+	};
 };

-- 
2.37.1

Re: [PATCH v3 1/6] dt-bindings: clock: Add support for i.MX94 LVDS/DISPLAY CSR

[Krzysztof Kozlowski]

On 07/07/2025 04:24, Peng Fan wrote:
> Add i.MX94 LVDS/DISPLAY CSR compatible string.
> 
> Add clock index for the two CSRs.
> 
> Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v3 0/6] clock: imx95: Add LVDS/DISPLAY CSR for i.MX94

[Abel Vesa]

On 25-07-07 10:24:36, Peng Fan wrote:
> Similar to i.MX95, i.MX94 also has LVDS/DISPLAY CSR to provide
> clock gate for LVDS and DISPLAY Controller. So following same approach
> to add the support, as what have been done for i.MX95.
> 
> Patch 1 is to add the binding doc.
> Patch 2 is fixes when supporting i.MX94, but the issues are
> also exposed to i.MX95 even not triggered. No need to rush the
> two patches for 6.16.
> Patch 3 and 4 is to add the clk driver. Patch 3 is almost picked from
> NXP downstream with a minor update. Patch 4 is modified from NXP
> downstream with a few minor patches merged and updated.
> Patch 5 is the dts part to give reviewer a whole view on how it is used.
> 
> Thanks for Frank Li helping do NXP internal review for the patchset.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

For some reason, this doesn't apply cleanly.

Can you rebase on 6.16-rc1 and resend?

Thanks,
Abel

Re: [PATCH v3 6/6] arm64: dts: imx943: Add LVDS/DISPLAY CSR nodes

[Laurentiu Palcu]

Hi Peng,

On Mon, Jul 07, 2025 at 10:24:42AM +0800, Peng Fan wrote:
> Add nodes for LVDS/DISPLAY CSR.
> 
> Add clock-ldb-pll-div7 node which is used for clock source of DISPLAY CSR.
> 
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx943.dtsi | 34 +++++++++++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi
> index 45b8da758e87771c0775eb799ce2da3aac37c060..657c81b6016f21270a1b13d636af72c14ab4f8ef 100644
> --- a/arch/arm64/boot/dts/freescale/imx943.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi
> @@ -3,6 +3,8 @@
>   * Copyright 2025 NXP
>   */
>  
> +#include <dt-bindings/clock/nxp,imx94-clock.h>
> +
>  #include "imx94.dtsi"
>  
>  / {
> @@ -145,4 +147,36 @@ l3_cache: l3-cache {
>  			cache-unified;
>  		};
>  	};
> +
> +	clock-ldb-pll-div7 {

You need to add a label to this node, so it can be referenced from
other nodes. I hit this issue while trying to prepare the DCIF patches
for sending upstream, using your latest patchset.

Thanks,
Laurentiu

> +		compatible = "fixed-factor-clock";
> +		#clock-cells = <0>;
> +		clocks = <&scmi_clk IMX94_CLK_LDBPLL>;
> +		clock-div = <7>;
> +		clock-mult = <1>;
> +		clock-output-names = "ldb_pll_div7";
> +	};
> +
> +	soc {
> +		dispmix_csr: syscon@4b010000 {
> +			compatible = "nxp,imx94-display-csr", "syscon";
> +			reg = <0x0 0x4b010000 0x0 0x10000>;
> +			clocks = <&scmi_clk IMX94_CLK_DISPAPB>;
> +			#clock-cells = <1>;
> +			power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
> +			assigned-clocks = <&scmi_clk IMX94_CLK_DISPAXI>,
> +					  <&scmi_clk IMX94_CLK_DISPAPB>;
> +			assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>,
> +						 <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
> +			assigned-clock-rates = <400000000>,  <133333333>;
> +		};
> +
> +		lvds_csr: syscon@4b0c0000 {
> +			compatible = "nxp,imx94-lvds-csr", "syscon";
> +			reg = <0x0 0x4b0c0000 0x0 0x10000>;
> +			clocks = <&scmi_clk IMX94_CLK_DISPAPB>;
> +			#clock-cells = <1>;
> +			power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
> +		};
> +	};
>  };
> 
> -- 
> 2.37.1
> 
> 

RE: [PATCH v3 0/6] clock: imx95: Add LVDS/DISPLAY CSR for i.MX94

[Peng Fan]

Hi Abel,

> Subject: Re: [PATCH v3 0/6] clock: imx95: Add LVDS/DISPLAY CSR for
> i.MX94
> 
> On 25-07-07 10:24:36, Peng Fan wrote:
> > Similar to i.MX95, i.MX94 also has LVDS/DISPLAY CSR to provide
> clock
> > gate for LVDS and DISPLAY Controller. So following same approach to
> > add the support, as what have been done for i.MX95.
> >
> > Patch 1 is to add the binding doc.
> > Patch 2 is fixes when supporting i.MX94, but the issues are also
> > exposed to i.MX95 even not triggered. No need to rush the two
> patches
> > for 6.16.
> > Patch 3 and 4 is to add the clk driver. Patch 3 is almost picked from
> > NXP downstream with a minor update. Patch 4 is modified from NXP
> > downstream with a few minor patches merged and updated.
> > Patch 5 is the dts part to give reviewer a whole view on how it is used.
> >
> > Thanks for Frank Li helping do NXP internal review for the patchset.
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> 
> For some reason, this doesn't apply cleanly.
> 
> Can you rebase on 6.16-rc1 and resend?

The patch was picked by Stephen as a fix.
clk: imx: Fix an out-of-bounds access in dispmix_csr_clk_dev_data
aacc875a448d363332b9df0621dde6d3a225ea9f

Your tree does not have the upper patch, so
there is conflict when applying the patchset.

You may need to update your base.

Please let me know if I still need to resend the patch
without the upper fix included.

Thanks,
Peng.

> 
> Thanks,
> Abel

Re: [PATCH v3 5/6] MAINTAINERS: Update i.MX Clock Entry

[Abel Vesa]

On 25-07-07 10:24:41, Peng Fan wrote:
> Update file match pattern to include nxp,imx* and fsl,imx*.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Reviewed-by: Abel Vesa <abel.vesa@linaro.org>

Re: (subset) [PATCH v3 0/6] clock: imx95: Add LVDS/DISPLAY CSR for i.MX94

[Abel Vesa]

On Mon, 07 Jul 2025 10:24:36 +0800, Peng Fan wrote:
> Similar to i.MX95, i.MX94 also has LVDS/DISPLAY CSR to provide
> clock gate for LVDS and DISPLAY Controller. So following same approach
> to add the support, as what have been done for i.MX95.
> 
> Patch 1 is to add the binding doc.
> Patch 2 is fixes when supporting i.MX94, but the issues are
> also exposed to i.MX95 even not triggered. No need to rush the
> two patches for 6.16.
> Patch 3 and 4 is to add the clk driver. Patch 3 is almost picked from
> NXP downstream with a minor update. Patch 4 is modified from NXP
> downstream with a few minor patches merged and updated.
> Patch 5 is the dts part to give reviewer a whole view on how it is used.
> 
> [...]

Applied, thanks!

[1/6] dt-bindings: clock: Add support for i.MX94 LVDS/DISPLAY CSR
      commit: 0b0cd1857b783711b4bdfb8eb513c263b8a84f6d
[2/6] clk: imx95-blk-ctl: Fix synchronous abort
      commit: b08217a257215ed9130fce93d35feba66b49bf0a
[3/6] clk: imx95-blk-ctl: Rename lvds and displaymix csr blk
      commit: 88768d6f8c13ede81b248177fed3ac285499f77c
[4/6] clk: imx95-blk-ctl: Add clock for i.MX94 LVDS/Display CSR
      commit: 9678bc7661cb34bec4be92685039eec68ca67dad
[5/6] MAINTAINERS: Update i.MX Clock Entry
      commit: c78865241ecffaff7ce5db00ed5b71c1a70c0ff1

Best regards,
-- 
Abel Vesa <abel.vesa@linaro.org>

Re: [PATCH v3 6/6] arm64: dts: imx943: Add LVDS/DISPLAY CSR nodes

[Peng Fan]

On Tue, Jul 08, 2025 at 03:19:26PM +0300, Laurentiu Palcu wrote:
>Hi Peng,
>
>On Mon, Jul 07, 2025 at 10:24:42AM +0800, Peng Fan wrote:
>> Add nodes for LVDS/DISPLAY CSR.
>> 
>> Add clock-ldb-pll-div7 node which is used for clock source of DISPLAY CSR.
>> 
>> Reviewed-by: Frank Li <Frank.Li@nxp.com>
>> Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>> ---
>>  arch/arm64/boot/dts/freescale/imx943.dtsi | 34 +++++++++++++++++++++++++++++++
>>  1 file changed, 34 insertions(+)
>> 
>> diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi
>> index 45b8da758e87771c0775eb799ce2da3aac37c060..657c81b6016f21270a1b13d636af72c14ab4f8ef 100644
>> --- a/arch/arm64/boot/dts/freescale/imx943.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi
>> @@ -3,6 +3,8 @@
>>   * Copyright 2025 NXP
>>   */
>>  
>> +#include <dt-bindings/clock/nxp,imx94-clock.h>
>> +
>>  #include "imx94.dtsi"
>>  
>>  / {
>> @@ -145,4 +147,36 @@ l3_cache: l3-cache {
>>  			cache-unified;
>>  		};
>>  	};
>> +
>> +	clock-ldb-pll-div7 {
>
>You need to add a label to this node, so it can be referenced from
>other nodes. I hit this issue while trying to prepare the DCIF patches
>for sending upstream, using your latest patchset.

Thanks for the comment. Let's add a label when there is a real reference
in the file. Since you adds the label in your patch to support i.MX943
DCIF as we talked, I will leave this patch at it is.

Thanks,
Peng

>
>Thanks,
>Laurentiu
>
>> +		compatible = "fixed-factor-clock";
>> +		#clock-cells = <0>;
>> +		clocks = <&scmi_clk IMX94_CLK_LDBPLL>;
>> +		clock-div = <7>;
>> +		clock-mult = <1>;
>> +		clock-output-names = "ldb_pll_div7";
>> +	};
>> +
>> +	soc {
>> +		dispmix_csr: syscon@4b010000 {
>> +			compatible = "nxp,imx94-display-csr", "syscon";
>> +			reg = <0x0 0x4b010000 0x0 0x10000>;
>> +			clocks = <&scmi_clk IMX94_CLK_DISPAPB>;
>> +			#clock-cells = <1>;
>> +			power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
>> +			assigned-clocks = <&scmi_clk IMX94_CLK_DISPAXI>,
>> +					  <&scmi_clk IMX94_CLK_DISPAPB>;
>> +			assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>,
>> +						 <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
>> +			assigned-clock-rates = <400000000>,  <133333333>;
>> +		};
>> +
>> +		lvds_csr: syscon@4b0c0000 {
>> +			compatible = "nxp,imx94-lvds-csr", "syscon";
>> +			reg = <0x0 0x4b0c0000 0x0 0x10000>;
>> +			clocks = <&scmi_clk IMX94_CLK_DISPAPB>;
>> +			#clock-cells = <1>;
>> +			power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
>> +		};
>> +	};
>>  };
>> 
>> -- 
>> 2.37.1
>> 
>>