* [PATCH 0/3] add clocks support for exynosauto v920 SoC [not found] <CGME20240912103903epcas2p3ff3df48eb8b19d27053b2c2fe40ea1c5@epcas2p3.samsung.com> @ 2024-09-12 10:38 ` Sunyeal Hong 2024-09-12 10:38 ` [PATCH 1/3] dt-bindings: clock: exynosautov920: add peric1, misc and hsi0/1 clock definitions Sunyeal Hong ` (2 more replies) 0 siblings, 3 replies; 8+ messages in thread From: Sunyeal Hong @ 2024-09-12 10:38 UTC (permalink / raw) To: Krzysztof Kozlowski, Rob Herring, Conor Dooley, Alim Akhtar, Sylwester Nawrocki, Chanwoo Choi, Michael Turquette, Stephen Boyd Cc: devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel, linux-clk, Sunyeal Hong This patchset adds the CMU block below to support exynosauto v920 SoC. - CMU_PERIC1 - CMU_MISC - CMU_HSI0/1 Sunyeal Hong (3): dt-bindings: clock: exynosautov920: add peric1, misc and hsi0/1 clock definitions clk: samsung: exynosautov920: add peric1, misc and hsi0/1 clock support arm64: dts: exynosautov920: add peric1, misc and hsi0/1 clock DT nodes .../arm64/boot/dts/exynos/exynosautov920.dtsi | 50 +++ drivers/clk/samsung/clk-exynosautov920.c | 290 ++++++++++++++++++ .../clock/samsung,exynosautov920.h | 47 +++ 3 files changed, 387 insertions(+) -- 2.46.0 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/3] dt-bindings: clock: exynosautov920: add peric1, misc and hsi0/1 clock definitions 2024-09-12 10:38 ` [PATCH 0/3] add clocks support for exynosauto v920 SoC Sunyeal Hong @ 2024-09-12 10:38 ` Sunyeal Hong 2024-09-12 10:38 ` [PATCH 2/3] clk: samsung: exynosautov920: add peric1, misc and hsi0/1 clock support Sunyeal Hong 2024-09-12 10:38 ` [PATCH 3/3] arm64: dts: exynosautov920: add peric1, misc and hsi0/1 clock DT nodes Sunyeal Hong 2 siblings, 0 replies; 8+ messages in thread From: Sunyeal Hong @ 2024-09-12 10:38 UTC (permalink / raw) To: Krzysztof Kozlowski, Rob Herring, Conor Dooley, Alim Akhtar, Sylwester Nawrocki, Chanwoo Choi, Michael Turquette, Stephen Boyd Cc: devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel, linux-clk, Sunyeal Hong Add peric1, misc and hsi0/1 clock definitions. - CMU_PERIC1 for USI, IC2 and I3C - CMU_MISC for MISC, GIC and OTP - HSI0 for PCIE - HSI1 for USB and MMC Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> --- .../clock/samsung,exynosautov920.h | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/include/dt-bindings/clock/samsung,exynosautov920.h b/include/dt-bindings/clock/samsung,exynosautov920.h index c720f344b6bf..0c681f2ba3d0 100644 --- a/include/dt-bindings/clock/samsung,exynosautov920.h +++ b/include/dt-bindings/clock/samsung,exynosautov920.h @@ -160,6 +160,7 @@ #define DOUT_CLKCMU_SNW_NOC 144 #define DOUT_CLKCMU_SSP_NOC 145 #define DOUT_CLKCMU_TAA_NOC 146 +#define DOUT_TCXO_DIV2 147 /* CMU_PERIC0 */ #define CLK_MOUT_PERIC0_IP_USER 1 @@ -188,4 +189,50 @@ #define CLK_DOUT_PERIC0_USI_I2C 23 #define CLK_DOUT_PERIC0_I3C 24 +/* CMU_PERIC1 */ +#define CLK_MOUT_PERIC1_IP_USER 1 +#define CLK_MOUT_PERIC1_NOC_USER 2 +#define CLK_MOUT_PERIC1_USI09_USI 3 +#define CLK_MOUT_PERIC1_USI10_USI 4 +#define CLK_MOUT_PERIC1_USI11_USI 5 +#define CLK_MOUT_PERIC1_USI12_USI 6 +#define CLK_MOUT_PERIC1_USI13_USI 7 +#define CLK_MOUT_PERIC1_USI14_USI 8 +#define CLK_MOUT_PERIC1_USI15_USI 9 +#define CLK_MOUT_PERIC1_USI16_USI 10 +#define CLK_MOUT_PERIC1_USI17_USI 11 +#define CLK_MOUT_PERIC1_USI_I2C 12 +#define CLK_MOUT_PERIC1_I3C 13 + +#define CLK_DOUT_PERIC1_USI09_USI 14 +#define CLK_DOUT_PERIC1_USI10_USI 15 +#define CLK_DOUT_PERIC1_USI11_USI 16 +#define CLK_DOUT_PERIC1_USI12_USI 17 +#define CLK_DOUT_PERIC1_USI13_USI 18 +#define CLK_DOUT_PERIC1_USI14_USI 19 +#define CLK_DOUT_PERIC1_USI15_USI 20 +#define CLK_DOUT_PERIC1_USI16_USI 21 +#define CLK_DOUT_PERIC1_USI17_USI 22 +#define CLK_DOUT_PERIC1_USI_I2C 23 +#define CLK_DOUT_PERIC1_I3C 24 + +/* CMU_MISC */ +#define CLK_MOUT_MISC_NOC_USER 1 +#define CLK_MOUT_MISC_GIC 2 + +#define CLK_DOUT_MISC_OTP 3 +#define CLK_DOUT_MISC_NOCP 4 +#define CLK_DOUT_MISC_OSC_DIV2 5 + +/* CMU_HSI0 */ +#define CLK_MOUT_HSI0_NOC_USER 1 + +#define CLK_DOUT_HSI0_PCIE_APB 2 + +/* CMU_HSI1 */ +#define CLK_MOUT_HSI1_MMC_CARD_USER 1 +#define CLK_MOUT_HSI1_NOC_USER 2 +#define CLK_MOUT_HSI1_USBDRD_USER 3 +#define CLK_MOUT_HSI1_USBDRD 4 + #endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */ -- 2.46.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/3] clk: samsung: exynosautov920: add peric1, misc and hsi0/1 clock support 2024-09-12 10:38 ` [PATCH 0/3] add clocks support for exynosauto v920 SoC Sunyeal Hong 2024-09-12 10:38 ` [PATCH 1/3] dt-bindings: clock: exynosautov920: add peric1, misc and hsi0/1 clock definitions Sunyeal Hong @ 2024-09-12 10:38 ` Sunyeal Hong 2024-09-30 11:36 ` Krzysztof Kozlowski 2024-09-12 10:38 ` [PATCH 3/3] arm64: dts: exynosautov920: add peric1, misc and hsi0/1 clock DT nodes Sunyeal Hong 2 siblings, 1 reply; 8+ messages in thread From: Sunyeal Hong @ 2024-09-12 10:38 UTC (permalink / raw) To: Krzysztof Kozlowski, Rob Herring, Conor Dooley, Alim Akhtar, Sylwester Nawrocki, Chanwoo Choi, Michael Turquette, Stephen Boyd Cc: devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel, linux-clk, Sunyeal Hong Like CMU_PERIC1, this provides clocks for USI09 ~ USI17, USI_I2C and USI_I3C. Like CMU_MISC, this provides clocks for MISC, GIC and OTP. Like CMU_HSI0, this provides clocks for PCIE. Like CMU_HSI1, this provides clocks for USB and MMC. Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> --- drivers/clk/samsung/clk-exynosautov920.c | 290 +++++++++++++++++++++++ 1 file changed, 290 insertions(+) diff --git a/drivers/clk/samsung/clk-exynosautov920.c b/drivers/clk/samsung/clk-exynosautov920.c index 7ba9748c0526..d9f8e6efdbd8 100644 --- a/drivers/clk/samsung/clk-exynosautov920.c +++ b/drivers/clk/samsung/clk-exynosautov920.c @@ -19,6 +19,10 @@ /* NOTE: Must be equal to the last clock ID increased by one */ #define CLKS_NR_TOP (DOUT_CLKCMU_TAA_NOC + 1) #define CLKS_NR_PERIC0 (CLK_DOUT_PERIC0_I3C + 1) +#define CLKS_NR_PERIC1 (CLK_DOUT_PERIC1_I3C + 1) +#define CLKS_NR_MISC (CLK_DOUT_MISC_OSC_DIV2 + 1) +#define CLKS_NR_HSI0 (CLK_DOUT_HSI0_PCIE_APB + 1) +#define CLKS_NR_HSI1 (CLK_MOUT_HSI1_USBDRD + 1) /* ---- CMU_TOP ------------------------------------------------------------ */ @@ -974,6 +978,8 @@ static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initcon "mout_shared5_pll", 1, 3, 0), FFACTOR(DOUT_SHARED5_DIV4, "dout_shared5_div4", "mout_shared5_pll", 1, 4, 0), + FFACTOR(DOUT_TCXO_DIV2, "dout_tcxo_div2", + "oscclk", 1, 2, 0), }; static const struct samsung_cmu_info top_cmu_info __initconst = { @@ -1139,6 +1145,277 @@ static const struct samsung_cmu_info peric0_cmu_info __initconst = { .clk_name = "noc", }; +/* ---- CMU_PERIC1 --------------------------------------------------------- */ + +/* Register Offset definitions for CMU_PERIC1 (0x10C00000) */ +#define PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER 0x600 +#define PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER 0x610 +#define CLK_CON_MUX_MUX_CLK_PERIC1_I3C 0x1000 +#define CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI 0x1004 +#define CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI 0x1008 +#define CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI 0x100c +#define CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI 0x1010 +#define CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI 0x1014 +#define CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI 0x1018 +#define CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI 0x101c +#define CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI 0x1020 +#define CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI 0x1024 +#define CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C 0x1028 +#define CLK_CON_DIV_DIV_CLK_PERIC1_I3C 0x1800 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI 0x1804 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1808 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x180c +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x1810 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI 0x1814 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI 0x1818 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI 0x181c +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI 0x1820 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI 0x1824 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C 0x1828 + +static const unsigned long peric1_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER, + CLK_CON_MUX_MUX_CLK_PERIC1_I3C, + CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI, + CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI, + CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI, + CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI, + CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI, + CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI, + CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI, + CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI, + CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI, + CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C, + CLK_CON_DIV_DIV_CLK_PERIC1_I3C, + CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, +}; + +/* List of parent clocks for Muxes in CMU_PERIC1 */ +PNAME(mout_peric1_ip_user_p) = { "oscclk", "dout_clkcmu_peric1_ip" }; +PNAME(mout_peric1_noc_user_p) = { "oscclk", "dout_clkcmu_peric1_noc" }; +PNAME(mout_peric1_usi_p) = { "oscclk", "mout_peric1_ip_user" }; + +static const struct samsung_mux_clock peric1_mux_clks[] __initconst = { + MUX(CLK_MOUT_PERIC1_IP_USER, "mout_peric1_ip_user", + mout_peric1_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_NOC_USER, "mout_peric1_noc_user", + mout_peric1_noc_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER, 4, 1), + /* USI09 ~ USI17 */ + MUX(CLK_MOUT_PERIC1_USI09_USI, "mout_peric1_usi09_usi", + mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI, 0, 1), + MUX(CLK_MOUT_PERIC1_USI10_USI, "mout_peric1_usi10_usi", + mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI, 0, 1), + MUX(CLK_MOUT_PERIC1_USI11_USI, "mout_peric1_usi11_usi", + mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI, 0, 1), + MUX(CLK_MOUT_PERIC1_USI12_USI, "mout_peric1_usi12_usi", + mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI, 0, 1), + MUX(CLK_MOUT_PERIC1_USI13_USI, "mout_peric1_usi13_usi", + mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI, 0, 1), + MUX(CLK_MOUT_PERIC1_USI14_USI, "mout_peric1_usi14_usi", + mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI, 0, 1), + MUX(CLK_MOUT_PERIC1_USI15_USI, "mout_peric1_usi15_usi", + mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI, 0, 1), + MUX(CLK_MOUT_PERIC1_USI16_USI, "mout_peric1_usi16_usi", + mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI, 0, 1), + MUX(CLK_MOUT_PERIC1_USI17_USI, "mout_peric1_usi17_usi", + mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI, 0, 1), + /* USI_I2C */ + MUX(CLK_MOUT_PERIC1_USI_I2C, "mout_peric1_usi_i2c", + mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C, 0, 1), + /* USI_I3C */ + MUX(CLK_MOUT_PERIC1_I3C, "mout_peric1_i3c", + mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_I3C, 0, 1), +}; + +static const struct samsung_div_clock peric1_div_clks[] __initconst = { + /* USI09 ~ USI17 */ + DIV(CLK_DOUT_PERIC1_USI09_USI, "dout_peric1_usi09_usi", + "mout_peric1_usi09_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI, + 0, 4), + DIV(CLK_DOUT_PERIC1_USI10_USI, "dout_peric1_usi10_usi", + "mout_peric1_usi10_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, + 0, 4), + DIV(CLK_DOUT_PERIC1_USI11_USI, "dout_peric1_usi11_usi", + "mout_peric1_usi11_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, + 0, 4), + DIV(CLK_DOUT_PERIC1_USI12_USI, "dout_peric1_usi12_usi", + "mout_peric1_usi12_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, + 0, 4), + DIV(CLK_DOUT_PERIC1_USI13_USI, "dout_peric1_usi13_usi", + "mout_peric1_usi13_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, + 0, 4), + DIV(CLK_DOUT_PERIC1_USI14_USI, "dout_peric1_usi14_usi", + "mout_peric1_usi14_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI, + 0, 4), + DIV(CLK_DOUT_PERIC1_USI15_USI, "dout_peric1_usi15_usi", + "mout_peric1_usi15_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI, + 0, 4), + DIV(CLK_DOUT_PERIC1_USI16_USI, "dout_peric1_usi16_usi", + "mout_peric1_usi16_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI, + 0, 4), + DIV(CLK_DOUT_PERIC1_USI17_USI, "dout_peric1_usi17_usi", + "mout_peric1_usi17_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI, + 0, 4), + /* USI_I2C */ + DIV(CLK_DOUT_PERIC1_USI_I2C, "dout_peric1_usi_i2c", + "mout_peric1_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 0, 4), + /* USI_I3C */ + DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c", + "mout_peric1_i3c", CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4), +}; + +static const struct samsung_cmu_info peric1_cmu_info __initconst = { + .mux_clks = peric1_mux_clks, + .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks), + .div_clks = peric1_div_clks, + .nr_div_clks = ARRAY_SIZE(peric1_div_clks), + .nr_clk_ids = CLKS_NR_PERIC1, + .clk_regs = peric1_clk_regs, + .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), + .clk_name = "noc", +}; + +/* ---- CMU_MISC --------------------------------------------------------- */ + +/* Register Offset definitions for CMU_MISC (0x10020000) */ +#define PLL_CON0_MUX_CLKCMU_MISC_NOC_USER 0x600 +#define CLK_CON_MUX_MUX_CLK_MISC_GIC 0x1000 +#define CLK_CON_DIV_CLKCMU_OTP 0x1800 +#define CLK_CON_DIV_DIV_CLK_MISC_NOCP 0x1804 +#define CLK_CON_DIV_DIV_CLK_MISC_OSC_DIV2 0x1808 + +static const unsigned long misc_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_MISC_NOC_USER, + CLK_CON_MUX_MUX_CLK_MISC_GIC, + CLK_CON_DIV_CLKCMU_OTP, + CLK_CON_DIV_DIV_CLK_MISC_NOCP, + CLK_CON_DIV_DIV_CLK_MISC_OSC_DIV2, +}; + +/* List of parent clocks for Muxes in CMU_MISC */ +PNAME(mout_misc_noc_user_p) = { "oscclk", "dout_clkcmu_misc_noc" }; +PNAME(mout_misc_gic_p) = { "dout_misc_nocp", "oscclk" }; + +static const struct samsung_mux_clock misc_mux_clks[] __initconst = { + MUX(CLK_MOUT_MISC_NOC_USER, "mout_misc_noc_user", + mout_misc_noc_user_p, PLL_CON0_MUX_CLKCMU_MISC_NOC_USER, 4, 1), + MUX(CLK_MOUT_MISC_GIC, "mout_misc_gic", + mout_misc_gic_p, CLK_CON_MUX_MUX_CLK_MISC_GIC, 0, 1), +}; + +static const struct samsung_div_clock misc_div_clks[] __initconst = { + DIV(CLK_DOUT_MISC_NOCP, "dout_misc_nocp", + "mout_misc_noc_user", CLK_CON_DIV_DIV_CLK_MISC_NOCP, + 0, 3), +}; + +static const struct samsung_fixed_factor_clock misc_fixed_factor_clks[] __initconst = { + FFACTOR(CLK_DOUT_MISC_OTP, "dout_misc_otp", + "oscclk", 1, 10, 0), + FFACTOR(CLK_DOUT_MISC_OSC_DIV2, "dout_misc_osc_div2", + "oscclk", 1, 2, 0), +}; + +static const struct samsung_cmu_info misc_cmu_info __initconst = { + .mux_clks = misc_mux_clks, + .nr_mux_clks = ARRAY_SIZE(misc_mux_clks), + .div_clks = misc_div_clks, + .nr_div_clks = ARRAY_SIZE(misc_div_clks), + .fixed_factor_clks = misc_fixed_factor_clks, + .nr_fixed_factor_clks = ARRAY_SIZE(misc_fixed_factor_clks), + .nr_clk_ids = CLKS_NR_MISC, + .clk_regs = misc_clk_regs, + .nr_clk_regs = ARRAY_SIZE(misc_clk_regs), + .clk_name = "noc", +}; + +/* ---- CMU_HSI0 --------------------------------------------------------- */ + +/* Register Offset definitions for CMU_HSI0 (0x16000000) */ +#define PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER 0x600 +#define CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB 0x1800 + +static const unsigned long hsi0_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER, + CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB, +}; + +/* List of parent clocks for Muxes in CMU_HSI0 */ +PNAME(mout_hsi0_noc_user_p) = { "oscclk", "dout_clkcmu_hsi0_noc" }; + +static const struct samsung_mux_clock hsi0_mux_clks[] __initconst = { + MUX(CLK_MOUT_HSI0_NOC_USER, "mout_hsi0_noc_user", + mout_hsi0_noc_user_p, PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER, 4, 1), +}; + +static const struct samsung_div_clock hsi0_div_clks[] __initconst = { + DIV(CLK_DOUT_HSI0_PCIE_APB, "dout_hsi0_pcie_apb", + "mout_hsi0_noc_user", CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB, + 0, 4), +}; + +static const struct samsung_cmu_info hsi0_cmu_info __initconst = { + .mux_clks = hsi0_mux_clks, + .nr_mux_clks = ARRAY_SIZE(hsi0_mux_clks), + .div_clks = hsi0_div_clks, + .nr_div_clks = ARRAY_SIZE(hsi0_div_clks), + .nr_clk_ids = CLKS_NR_HSI0, + .clk_regs = hsi0_clk_regs, + .nr_clk_regs = ARRAY_SIZE(hsi0_clk_regs), + .clk_name = "noc", +}; + +/* ---- CMU_HSI1 --------------------------------------------------------- */ + +/* Register Offset definitions for CMU_HSI1 (0x16400000) */ +#define PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER 0x600 +#define PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER 0x610 +#define PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER 0x620 +#define CLK_CON_MUX_MUX_CLK_HSI1_USBDRD 0x1000 + +static const unsigned long hsi1_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER, + PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER, + PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER, + CLK_CON_MUX_MUX_CLK_HSI1_USBDRD, +}; + +/* List of parent clocks for Muxes in CMU_HSI1 */ +PNAME(mout_hsi1_mmc_card_user_p) = {"oscclk", "dout_clkcmu_hsi1_mmc_card"}; +PNAME(mout_hsi1_noc_user_p) = { "oscclk", "dout_clkcmu_hsi1_noc" }; +PNAME(mout_hsi1_usbdrd_user_p) = { "oscclk", "mout_clkcmu_hsi1_usbdrd" }; +PNAME(mout_hsi1_usbdrd_p) = { "dout_tcxo_div2", "mout_hsi1_usbdrd_user" }; + +static const struct samsung_mux_clock hsi1_mux_clks[] __initconst = { + MUX(CLK_MOUT_HSI1_MMC_CARD_USER, "mout_hsi1_mmc_card_user", + mout_hsi1_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER, 4, 1), + MUX(CLK_MOUT_HSI1_NOC_USER, "mout_hsi1_noc_user", + mout_hsi1_noc_user_p, PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER, 4, 1), + MUX(CLK_MOUT_HSI1_USBDRD_USER, "mout_hsi1_usbdrd_user", + mout_hsi1_usbdrd_user_p, PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER, 4, 1), + MUX(CLK_MOUT_HSI1_USBDRD, "mout_hsi1_usbdrd", + mout_hsi1_usbdrd_p, CLK_CON_MUX_MUX_CLK_HSI1_USBDRD, 4, 1), +}; + +static const struct samsung_cmu_info hsi1_cmu_info __initconst = { + .mux_clks = hsi1_mux_clks, + .nr_mux_clks = ARRAY_SIZE(hsi1_mux_clks), + .nr_clk_ids = CLKS_NR_HSI1, + .clk_regs = hsi1_clk_regs, + .nr_clk_regs = ARRAY_SIZE(hsi1_clk_regs), + .clk_name = "noc", +}; + static int __init exynosautov920_cmu_probe(struct platform_device *pdev) { const struct samsung_cmu_info *info; @@ -1154,6 +1431,19 @@ static const struct of_device_id exynosautov920_cmu_of_match[] = { { .compatible = "samsung,exynosautov920-cmu-peric0", .data = &peric0_cmu_info, + }, { + .compatible = "samsung,exynosautov920-cmu-peric1", + .data = &peric1_cmu_info, + }, { + .compatible = "samsung,exynosautov920-cmu-misc", + .data = &misc_cmu_info, + }, { + .compatible = "samsung,exynosautov920-cmu-hsi0", + .data = &hsi0_cmu_info, + }, { + .compatible = "samsung,exynosautov920-cmu-hsi1", + .data = &hsi1_cmu_info, + }, { }, }; -- 2.46.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/3] clk: samsung: exynosautov920: add peric1, misc and hsi0/1 clock support 2024-09-12 10:38 ` [PATCH 2/3] clk: samsung: exynosautov920: add peric1, misc and hsi0/1 clock support Sunyeal Hong @ 2024-09-30 11:36 ` Krzysztof Kozlowski 2024-10-07 8:04 ` sunyeal.hong 0 siblings, 1 reply; 8+ messages in thread From: Krzysztof Kozlowski @ 2024-09-30 11:36 UTC (permalink / raw) To: Sunyeal Hong, Krzysztof Kozlowski, Rob Herring, Conor Dooley, Alim Akhtar, Sylwester Nawrocki, Chanwoo Choi, Michael Turquette, Stephen Boyd Cc: devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel, linux-clk On 12/09/2024 12:38, Sunyeal Hong wrote: > Like CMU_PERIC1, this provides clocks for USI09 ~ USI17, USI_I2C and USI_I3C. > Like CMU_MISC, this provides clocks for MISC, GIC and OTP. > Like CMU_HSI0, this provides clocks for PCIE. > Like CMU_HSI1, this provides clocks for USB and MMC. > > Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> > --- ... > + > static int __init exynosautov920_cmu_probe(struct platform_device *pdev) > { > const struct samsung_cmu_info *info; > @@ -1154,6 +1431,19 @@ static const struct of_device_id exynosautov920_cmu_of_match[] = { > { > .compatible = "samsung,exynosautov920-cmu-peric0", > .data = &peric0_cmu_info, > + }, { > + .compatible = "samsung,exynosautov920-cmu-peric1", > + .data = &peric1_cmu_info, > + }, { > + .compatible = "samsung,exynosautov920-cmu-misc", > + .data = &misc_cmu_info, > + }, { > + .compatible = "samsung,exynosautov920-cmu-hsi0", > + .data = &hsi0_cmu_info, > + }, { > + .compatible = "samsung,exynosautov920-cmu-hsi1", > + .data = &hsi1_cmu_info, > + }, { This is unrelated change. Please rebase. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH 2/3] clk: samsung: exynosautov920: add peric1, misc and hsi0/1 clock support 2024-09-30 11:36 ` Krzysztof Kozlowski @ 2024-10-07 8:04 ` sunyeal.hong 2024-10-07 8:06 ` Krzysztof Kozlowski 0 siblings, 1 reply; 8+ messages in thread From: sunyeal.hong @ 2024-10-07 8:04 UTC (permalink / raw) To: 'Krzysztof Kozlowski', 'Krzysztof Kozlowski', 'Rob Herring', 'Conor Dooley', 'Alim Akhtar', 'Sylwester Nawrocki', 'Chanwoo Choi', 'Michael Turquette', 'Stephen Boyd' Cc: devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel, linux-clk Hello Krzysztof, > -----Original Message----- > From: Krzysztof Kozlowski <krzk@kernel.org> > Sent: Monday, September 30, 2024 8:36 PM > To: Sunyeal Hong <sunyeal.hong@samsung.com>; Krzysztof Kozlowski > <krzk+dt@kernel.org>; Rob Herring <robh@kernel.org>; Conor Dooley > <conor+dt@kernel.org>; Alim Akhtar <alim.akhtar@samsung.com>; Sylwester > Nawrocki <s.nawrocki@samsung.com>; Chanwoo Choi <cw00.choi@samsung.com>; > Michael Turquette <mturquette@baylibre.com>; Stephen Boyd > <sboyd@kernel.org> > Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > linux-samsung-soc@vger.kernel.org; linux-kernel@vger.kernel.org; linux- > clk@vger.kernel.org > Subject: Re: [PATCH 2/3] clk: samsung: exynosautov920: add peric1, misc > and hsi0/1 clock support > > On 12/09/2024 12:38, Sunyeal Hong wrote: > > Like CMU_PERIC1, this provides clocks for USI09 ~ USI17, USI_I2C and > USI_I3C. > > Like CMU_MISC, this provides clocks for MISC, GIC and OTP. > > Like CMU_HSI0, this provides clocks for PCIE. > > Like CMU_HSI1, this provides clocks for USB and MMC. > > > > Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> > > --- > > ... > > > + > > static int __init exynosautov920_cmu_probe(struct platform_device > > *pdev) { > > const struct samsung_cmu_info *info; @@ -1154,6 +1431,19 @@ static > > const struct of_device_id exynosautov920_cmu_of_match[] = { > > { > > .compatible = "samsung,exynosautov920-cmu-peric0", > > .data = &peric0_cmu_info, > > + }, { > > + .compatible = "samsung,exynosautov920-cmu-peric1", > > + .data = &peric1_cmu_info, > > + }, { > > + .compatible = "samsung,exynosautov920-cmu-misc", > > + .data = &misc_cmu_info, > > + }, { > > + .compatible = "samsung,exynosautov920-cmu-hsi0", > > + .data = &hsi0_cmu_info, > > + }, { > > + .compatible = "samsung,exynosautov920-cmu-hsi1", > > + .data = &hsi1_cmu_info, > > + }, { > > This is unrelated change. Please rebase. > Could you please explain in more detail the comment mentioned above? Best Regards, sunyeal > Best regards, > Krzysztof > ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/3] clk: samsung: exynosautov920: add peric1, misc and hsi0/1 clock support 2024-10-07 8:04 ` sunyeal.hong @ 2024-10-07 8:06 ` Krzysztof Kozlowski 2024-10-07 8:39 ` sunyeal.hong 0 siblings, 1 reply; 8+ messages in thread From: Krzysztof Kozlowski @ 2024-10-07 8:06 UTC (permalink / raw) To: sunyeal.hong, 'Krzysztof Kozlowski', 'Rob Herring', 'Conor Dooley', 'Alim Akhtar', 'Sylwester Nawrocki', 'Chanwoo Choi', 'Michael Turquette', 'Stephen Boyd' Cc: devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel, linux-clk On 07/10/2024 10:04, sunyeal.hong wrote: > Hello Krzysztof, > >> -----Original Message----- >> From: Krzysztof Kozlowski <krzk@kernel.org> >> Sent: Monday, September 30, 2024 8:36 PM >> To: Sunyeal Hong <sunyeal.hong@samsung.com>; Krzysztof Kozlowski >> <krzk+dt@kernel.org>; Rob Herring <robh@kernel.org>; Conor Dooley >> <conor+dt@kernel.org>; Alim Akhtar <alim.akhtar@samsung.com>; Sylwester >> Nawrocki <s.nawrocki@samsung.com>; Chanwoo Choi <cw00.choi@samsung.com>; >> Michael Turquette <mturquette@baylibre.com>; Stephen Boyd >> <sboyd@kernel.org> >> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; >> linux-samsung-soc@vger.kernel.org; linux-kernel@vger.kernel.org; linux- >> clk@vger.kernel.org >> Subject: Re: [PATCH 2/3] clk: samsung: exynosautov920: add peric1, misc >> and hsi0/1 clock support >> >> On 12/09/2024 12:38, Sunyeal Hong wrote: >>> Like CMU_PERIC1, this provides clocks for USI09 ~ USI17, USI_I2C and >> USI_I3C. >>> Like CMU_MISC, this provides clocks for MISC, GIC and OTP. >>> Like CMU_HSI0, this provides clocks for PCIE. >>> Like CMU_HSI1, this provides clocks for USB and MMC. >>> >>> Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> >>> --- >> >> ... >> >>> + >>> static int __init exynosautov920_cmu_probe(struct platform_device >>> *pdev) { >>> const struct samsung_cmu_info *info; @@ -1154,6 +1431,19 @@ static >>> const struct of_device_id exynosautov920_cmu_of_match[] = { >>> { >>> .compatible = "samsung,exynosautov920-cmu-peric0", >>> .data = &peric0_cmu_info, >>> + }, { >>> + .compatible = "samsung,exynosautov920-cmu-peric1", >>> + .data = &peric1_cmu_info, >>> + }, { >>> + .compatible = "samsung,exynosautov920-cmu-misc", >>> + .data = &misc_cmu_info, >>> + }, { >>> + .compatible = "samsung,exynosautov920-cmu-hsi0", >>> + .data = &hsi0_cmu_info, >>> + }, { >>> + .compatible = "samsung,exynosautov920-cmu-hsi1", >>> + .data = &hsi1_cmu_info, >>> + }, { >> >> This is unrelated change. Please rebase. >> > Could you please explain in more detail the comment mentioned above? You were growing this list, didn't you? Then adding sentinel is unrelated. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH 2/3] clk: samsung: exynosautov920: add peric1, misc and hsi0/1 clock support 2024-10-07 8:06 ` Krzysztof Kozlowski @ 2024-10-07 8:39 ` sunyeal.hong 0 siblings, 0 replies; 8+ messages in thread From: sunyeal.hong @ 2024-10-07 8:39 UTC (permalink / raw) To: 'Krzysztof Kozlowski', 'Krzysztof Kozlowski', 'Rob Herring', 'Conor Dooley', 'Alim Akhtar', 'Sylwester Nawrocki', 'Chanwoo Choi', 'Michael Turquette', 'Stephen Boyd' Cc: devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel, linux-clk Hello Krzysztof, > -----Original Message----- > From: Krzysztof Kozlowski <krzk@kernel.org> > Sent: Monday, October 7, 2024 5:07 PM > To: sunyeal.hong <sunyeal.hong@samsung.com>; 'Krzysztof Kozlowski' > <krzk+dt@kernel.org>; 'Rob Herring' <robh@kernel.org>; 'Conor Dooley' > <conor+dt@kernel.org>; 'Alim Akhtar' <alim.akhtar@samsung.com>; 'Sylwester > Nawrocki' <s.nawrocki@samsung.com>; 'Chanwoo Choi' <cw00.choi@samsung.com>; > 'Michael Turquette' <mturquette@baylibre.com>; 'Stephen Boyd' > <sboyd@kernel.org> > Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > linux-samsung-soc@vger.kernel.org; linux-kernel@vger.kernel.org; linux- > clk@vger.kernel.org > Subject: Re: [PATCH 2/3] clk: samsung: exynosautov920: add peric1, misc > and hsi0/1 clock support > > On 07/10/2024 10:04, sunyeal.hong wrote: > > Hello Krzysztof, > > > >> -----Original Message----- > >> From: Krzysztof Kozlowski <krzk@kernel.org> > >> Sent: Monday, September 30, 2024 8:36 PM > >> To: Sunyeal Hong <sunyeal.hong@samsung.com>; Krzysztof Kozlowski > >> <krzk+dt@kernel.org>; Rob Herring <robh@kernel.org>; Conor Dooley > >> <conor+dt@kernel.org>; Alim Akhtar <alim.akhtar@samsung.com>; > >> Sylwester Nawrocki <s.nawrocki@samsung.com>; Chanwoo Choi > >> <cw00.choi@samsung.com>; Michael Turquette <mturquette@baylibre.com>; > >> Stephen Boyd <sboyd@kernel.org> > >> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > >> linux-samsung-soc@vger.kernel.org; linux-kernel@vger.kernel.org; > >> linux- clk@vger.kernel.org > >> Subject: Re: [PATCH 2/3] clk: samsung: exynosautov920: add peric1, > >> misc and hsi0/1 clock support > >> > >> On 12/09/2024 12:38, Sunyeal Hong wrote: > >>> Like CMU_PERIC1, this provides clocks for USI09 ~ USI17, USI_I2C and > >> USI_I3C. > >>> Like CMU_MISC, this provides clocks for MISC, GIC and OTP. > >>> Like CMU_HSI0, this provides clocks for PCIE. > >>> Like CMU_HSI1, this provides clocks for USB and MMC. > >>> > >>> Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> > >>> --- > >> > >> ... > >> > >>> + > >>> static int __init exynosautov920_cmu_probe(struct platform_device > >>> *pdev) { > >>> const struct samsung_cmu_info *info; @@ -1154,6 +1431,19 @@ static > >>> const struct of_device_id exynosautov920_cmu_of_match[] = { > >>> { > >>> .compatible = "samsung,exynosautov920-cmu-peric0", > >>> .data = &peric0_cmu_info, > >>> + }, { > >>> + .compatible = "samsung,exynosautov920-cmu-peric1", > >>> + .data = &peric1_cmu_info, > >>> + }, { > >>> + .compatible = "samsung,exynosautov920-cmu-misc", > >>> + .data = &misc_cmu_info, > >>> + }, { > >>> + .compatible = "samsung,exynosautov920-cmu-hsi0", > >>> + .data = &hsi0_cmu_info, > >>> + }, { > >>> + .compatible = "samsung,exynosautov920-cmu-hsi1", > >>> + .data = &hsi1_cmu_info, > >>> + }, { > >> > >> This is unrelated change. Please rebase. > >> > > Could you please explain in more detail the comment mentioned above? > > You were growing this list, didn't you? Then adding sentinel is unrelated. > I have confirmed that the sentinel is being applied duplicately. I will send you a patch after fixing it. Best Regards, sunyeal > > Best regards, > Krzysztof > ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 3/3] arm64: dts: exynosautov920: add peric1, misc and hsi0/1 clock DT nodes 2024-09-12 10:38 ` [PATCH 0/3] add clocks support for exynosauto v920 SoC Sunyeal Hong 2024-09-12 10:38 ` [PATCH 1/3] dt-bindings: clock: exynosautov920: add peric1, misc and hsi0/1 clock definitions Sunyeal Hong 2024-09-12 10:38 ` [PATCH 2/3] clk: samsung: exynosautov920: add peric1, misc and hsi0/1 clock support Sunyeal Hong @ 2024-09-12 10:38 ` Sunyeal Hong 2 siblings, 0 replies; 8+ messages in thread From: Sunyeal Hong @ 2024-09-12 10:38 UTC (permalink / raw) To: Krzysztof Kozlowski, Rob Herring, Conor Dooley, Alim Akhtar, Sylwester Nawrocki, Chanwoo Choi, Michael Turquette, Stephen Boyd Cc: devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel, linux-clk, Sunyeal Hong Add cmu_peric1 for USI, I2C and I3C clocks respectively. Add cmu_misc for MISC, GIC and OTP clocks respectively. Add cmu_hsi0 for PCIE clocks respectively. Add cmu_hsi1 for USB and MMC clocks respectively. Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com> --- .../arm64/boot/dts/exynos/exynosautov920.dtsi | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi index 91882b37fdb3..c759134c909e 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -172,6 +172,17 @@ chipid@10000000 { reg = <0x10000000 0x24>; }; + cmu_misc: clock-controller@10020000 { + compatible = "samsung,exynosautov920-cmu-misc"; + reg = <0x10020000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_MISC_NOC>; + clock-names = "oscclk", + "noc"; + }; + gic: interrupt-controller@10400000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; @@ -247,6 +258,19 @@ pwm: pwm@109b0000 { status = "disabled"; }; + cmu_peric1: clock-controller@10c00000 { + compatible = "samsung,exynosautov920-cmu-peric1"; + reg = <0x10c00000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_PERIC1_NOC>, + <&cmu_top DOUT_CLKCMU_PERIC1_IP>; + clock-names = "oscclk", + "noc", + "ip"; + }; + syscon_peric1: syscon@10c20000 { compatible = "samsung,exynosautov920-peric1-sysreg", "syscon"; @@ -283,12 +307,38 @@ pmu_system_controller: system-controller@11860000 { reg = <0x11860000 0x10000>; }; + cmu_hsi0: clock-controller@16000000 { + compatible = "samsung,exynosautov920-cmu-hsi0"; + reg = <0x16000000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_HSI0_NOC>; + clock-names = "oscclk", + "noc"; + }; + pinctrl_hsi0: pinctrl@16040000 { compatible = "samsung,exynosautov920-pinctrl"; reg = <0x16040000 0x10000>; interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>; }; + cmu_hsi1: clock-controller@16400000 { + compatible = "samsung,exynosautov920-cmu-hsi1"; + reg = <0x16400000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_HSI1_NOC>, + <&cmu_top DOUT_CLKCMU_HSI1_USBDRD>, + <&cmu_top DOUT_CLKCMU_HSI1_MMC_CARD>; + clock-names = "oscclk", + "noc", + "usbdrd", + "mmc_card"; + }; + pinctrl_hsi1: pinctrl@16450000 { compatible = "samsung,exynosautov920-pinctrl"; reg = <0x16450000 0x10000>; -- 2.46.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2024-10-07 8:42 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
[not found] <CGME20240912103903epcas2p3ff3df48eb8b19d27053b2c2fe40ea1c5@epcas2p3.samsung.com>
2024-09-12 10:38 ` [PATCH 0/3] add clocks support for exynosauto v920 SoC Sunyeal Hong
2024-09-12 10:38 ` [PATCH 1/3] dt-bindings: clock: exynosautov920: add peric1, misc and hsi0/1 clock definitions Sunyeal Hong
2024-09-12 10:38 ` [PATCH 2/3] clk: samsung: exynosautov920: add peric1, misc and hsi0/1 clock support Sunyeal Hong
2024-09-30 11:36 ` Krzysztof Kozlowski
2024-10-07 8:04 ` sunyeal.hong
2024-10-07 8:06 ` Krzysztof Kozlowski
2024-10-07 8:39 ` sunyeal.hong
2024-09-12 10:38 ` [PATCH 3/3] arm64: dts: exynosautov920: add peric1, misc and hsi0/1 clock DT nodes Sunyeal Hong
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).