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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83965946543sm28990915b3a.16.2026.05.12.02.10.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 12 May 2026 02:10:26 -0700 (PDT) Message-ID: <07ca65f6-33da-40b1-afcd-0b0ceabd49f9@gmail.com> Date: Tue, 12 May 2026 17:10:22 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] drm/verisilicon: add support for Nuvoton MA35D1 DCUltra Lite display controller To: Thomas Zimmermann , zhengxingda@iscas.ac.cn, maarten.lankhorst@linux.intel.com, mripard@kernel.org, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260511075142.54752-1-a0987203069@gmail.com> <20260511075142.54752-3-a0987203069@gmail.com> <5157ab4d-3195-49f3-a3e9-aef6d58e869e@suse.de> Content-Language: en-US From: Joey Lu In-Reply-To: <5157ab4d-3195-49f3-a3e9-aef6d58e869e@suse.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260512_021028_590890_DBD66E79 X-CRM114-Status: GOOD ( 24.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 5/12/2026 4:24 PM, Thomas Zimmermann wrote: > Hi, > > instead of this if-else branchery, I strongly recommend to add a new > file with a new mode-setting pipeline for the new chipset. You can > share existing helpers where possible, and implement variants where > chips differ.  It's a bit more code, but will be a lot easier to > maintain in the future. > > See ast and mgag200 for example. Both drivers support various > revisions of their chipset, where each rev has its oddities. > > Best regards > Thomas Thank you for the detailed suggestion. I see your point and will refactor by adding a new file with a mode-setting pipeline for the chipset, reusing helpers where possible and handling variants as needed. > > Am 11.05.26 um 09:51 schrieb Joey Lu: >> The Nuvoton MA35D1 SoC integrates a Verisilicon DCUltra Lite display >> controller, which is a previous generation of the DC8000 series. While >> the general register layout is similar to the DC8000, there are several >> key differences that require per-variant handling in the driver. >> >> Add a vs_dc_info platform data structure (in vs_hwdb.h) to describe >> per-IP-variant capabilities, and use it throughout the driver to select >> the correct code paths at runtime. >> >> Key differences between DC8000 and DCUltra Lite handled: >> >> 1. No chip identity registers (0x0020-0x0030): DCUltra Lite uses static >>     platform data instead of reading model/revision/customer_id from HW. >> >> 2. No CONFIG_EX commit mechanism: DC8000 uses registers at 0x1CC0 >>     (FB_CONFIG_EX), 0x24D8 (FB_TOP_LEFT), 0x24E0 (FB_BOTTOM_RIGHT), >>     0x2510 (FB_BLEND_CONFIG), 0x2518 (PANEL_CONFIG_EX). DCUltra Lite >>     omits all of these and instead uses enable/reset bits in FB_CONFIG >>     (bit 0 = enable, bit 4 = reset) for direct framebuffer updates. >> >> 3. No PANEL_START register (0x1CCC): DCUltra Lite panel output starts >>     when PANEL_CONFIG.RUNNING is set; no separate multi-display sync >>     start register is needed. >> >> 4. Different IRQ registers: DCUltra Lite uses 0x147C (IRQ_STA) / >>     0x1480 (IRQ_EN); DC8000 uses 0x0010 (IRQ_ACK) / 0x0014 (IRQ_EN). >> >> 5. Different clock/reset topology: DCUltra Lite requires only "core" >>     (bus gate) and "pix0" (pixel divider) clocks with no reset lines >>     managed by the driver. DC8000 needs core/axi/ahb clocks and three >>     resets. >> >> 6. Single output only: DCUltra Lite has one display output; per-output >>     index logic is still in place but display_count is fixed at 1. >> >> 7. Reduced register space: max_register is 0x2000 vs DC8000's 0x2544. >> >> Add the "nuvoton,ma35d1-dcu" compatible string to the OF match table, >> extend Kconfig to allow building on ARCH_MA35 platforms, and expose >> vs_formats_no_yuv444 as the default format table for DCUltra Lite >> (YUV444 blending is a DC8000-only feature). >> >> All changes have been tested on Nuvoton MA35D1 hardware and are >> functioning correctly. >> >> Signed-off-by: Joey Lu >> --- >>   drivers/gpu/drm/verisilicon/Kconfig           |   2 +- >>   drivers/gpu/drm/verisilicon/vs_bridge.c       |  28 ++-- >>   drivers/gpu/drm/verisilicon/vs_crtc.c         |  13 +- >>   drivers/gpu/drm/verisilicon/vs_dc.c           | 129 ++++++++++++------ >>   drivers/gpu/drm/verisilicon/vs_dc.h           |   1 + >>   drivers/gpu/drm/verisilicon/vs_drm.c          |  16 ++- >>   drivers/gpu/drm/verisilicon/vs_hwdb.c         |   2 +- >>   drivers/gpu/drm/verisilicon/vs_hwdb.h         |  25 ++++ >>   .../gpu/drm/verisilicon/vs_primary_plane.c    |  43 +++--- >>   .../drm/verisilicon/vs_primary_plane_regs.h   |   2 + >>   10 files changed, 187 insertions(+), 74 deletions(-) >> >> >