From: Judith Mendez <jm@ti.com>
To: Andrew Davis <afd@ti.com>, Nishanth Menon <nm@ti.com>,
Vignesh Raghavendra <vigneshr@ti.com>,
Tero Kristo <kristo@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Santosh Shilimkar <ssantosh@kernel.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 2/2] soc: ti: k3-socinfo: Add support for AM62P variants via NVMEM
Date: Wed, 4 Feb 2026 18:51:00 -0600 [thread overview]
Message-ID: <07ebc227-58a8-4aaa-9711-2d8469d49dee@ti.com> (raw)
In-Reply-To: <25ced9af-b103-4cd3-9b31-42b188fcad60@ti.com>
Hi Andrew,
On 2/4/26 3:54 PM, Andrew Davis wrote:
> On 2/4/26 3:37 PM, Judith Mendez wrote:
>> Add support for detecting AM62P silicon revisions.
>>
>> On AM62P, silicon revision is discovered with GP_SW1 register instead
>> of JTAGID register. Use the NVMEM framework to read GP_SW1 from the
>> gpsw-efuse nvmem provider to determine SoC revision.
>>
>> Signed-off-by: Judith Mendez <jm@ti.com>
>> ---
>> drivers/soc/ti/k3-socinfo.c | 48 ++++++++++++++++++++++++++++++++++---
>> 1 file changed, 45 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/soc/ti/k3-socinfo.c b/drivers/soc/ti/k3-socinfo.c
>> index 42275cb5ba1c8..4b6947a9ceb4d 100644
>> --- a/drivers/soc/ti/k3-socinfo.c
>> +++ b/drivers/soc/ti/k3-socinfo.c
>> @@ -6,6 +6,7 @@
>> */
>> #include <linux/mfd/syscon.h>
>> +#include <linux/nvmem-consumer.h>
>> #include <linux/of.h>
>> #include <linux/of_address.h>
>> #include <linux/regmap.h>
>> @@ -25,6 +26,9 @@
>> #define CTRLMMR_WKUP_JTAGID_VARIANT_SHIFT (28)
>> #define CTRLMMR_WKUP_JTAGID_VARIANT_MASK GENMASK(31, 28)
>> +#define GP_SW1_VALID_BIT BIT(4)
>> +#define GP_SW1_ADR_MASK GENMASK(3, 0)
>> +
>> #define CTRLMMR_WKUP_JTAGID_PARTNO_SHIFT (12)
>> #define CTRLMMR_WKUP_JTAGID_PARTNO_MASK GENMASK(27, 12)
>> @@ -70,6 +74,29 @@ static const char * const am62lx_rev_string_map[] = {
>> "1.0", "1.1",
>> };
>> +static const char * const am62p_gpsw_rev_string_map[] = {
>> + "1.0", "1.1", "1.2",
>> +};
>> +
>> +static int
>> +k3_chipinfo_get_gpsw_variant(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + u32 gpsw_val, adr_val = 0;
>> + int ret;
>> +
>> + ret = nvmem_cell_read_u32(dev, "gpsw1", &gpsw_val);
>> + if (ret)
>> + return ret;
>> +
>> + if (!(gpsw_val & GP_SW1_VALID_BIT))
>> + return 0;
>
> Return -1 here so you will get the warning message about setting default
> SR1.0.
>
>> +
>> + adr_val = gpsw_val & GP_SW1_ADR_MASK;
>> +
>> + return adr_val;
>
> Merge the above two lines,
>
> return gpsw_val & GP_SW1_ADR_MASK;
>
> Or maybe try using FIELD_GET() or similar if you are feeling fancy.
>
>> +}
>> +
>> static int
>> k3_chipinfo_partno_to_names(unsigned int partno,
>> struct soc_device_attribute *soc_dev_attr)
>> @@ -86,9 +113,11 @@ k3_chipinfo_partno_to_names(unsigned int partno,
>> }
>> static int
>> -k3_chipinfo_variant_to_sr(unsigned int partno, unsigned int variant,
>> - struct soc_device_attribute *soc_dev_attr)
>> +k3_chipinfo_variant_to_sr(struct platform_device *pdev, unsigned int
>> partno,
>
> You pass in the platform_device struct pointer, but only ever use the
> ->dev member, just pass in the "dev" device pointer.
>
> Otherwise LGTM
>
> Andrew
>
Thanks for reviewing!
Will fix according to your review and respin the series.
~ Judith
next prev parent reply other threads:[~2026-02-05 0:51 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-04 21:37 [PATCH 0/2] Add AM62P silicon revision detection via NVMEM Judith Mendez
2026-02-04 21:37 ` [PATCH 1/2] dt-bindings: hwinfo: ti,k3-socinfo: Add nvmem-cells support Judith Mendez
2026-02-04 21:37 ` [PATCH 2/2] soc: ti: k3-socinfo: Add support for AM62P variants via NVMEM Judith Mendez
2026-02-04 21:54 ` Andrew Davis
2026-02-05 0:51 ` Judith Mendez [this message]
2026-02-06 0:38 ` Judith Mendez
2026-02-06 16:50 ` Andrew Davis
2026-02-06 18:46 ` Judith Mendez
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