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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id q3-20020a05600c46c300b003fc3b03caa5sm3996574wmo.1.2023.07.20.04.35.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 20 Jul 2023 04:35:10 -0700 (PDT) Message-ID: <0809ac02-b8bf-ed63-9e2e-e77cd7e93464@baylibre.com> Date: Thu, 20 Jul 2023 13:35:09 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH 1/3] arm64: dts: mediatek: mt6795: Add support for display blocks and DPI/DSI Content-Language: en-US To: AngeloGioacchino Del Regno , matthias.bgg@gmail.com Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, kernel@collabora.com References: <20230720091559.86406-1-angelogioacchino.delregno@collabora.com> <20230720091559.86406-2-angelogioacchino.delregno@collabora.com> From: Alexandre Mergnat In-Reply-To: <20230720091559.86406-2-angelogioacchino.delregno@collabora.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230720_043516_156140_2398B207 X-CRM114-Status: GOOD ( 17.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 20/07/2023 11:15, AngeloGioacchino Del Regno wrote: > Introduce all nodes for all of the display blocks in the MediaTek Helio > X10 MT6795 SoC, including the DSI PHY and DSI/DPI interfaces: those are > left disabled as usage is board specific. > > Signed-off-by: AngeloGioacchino Del Regno > --- > arch/arm64/boot/dts/mediatek/mt6795.dtsi | 252 +++++++++++++++++++++++ > 1 file changed, 252 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi > index 597bce2fed72..d805d7a63024 100644 > --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi > @@ -2,6 +2,9 @@ > /* > * Copyright (c) 2015 MediaTek Inc. > * Author: Mars.C > + * > + * Copyright (C) 2023 Collabora Ltd. > + * AngeloGioacchino Del Regno Shouldn't be like this ? * Copyright (c) 2015 MediaTek Inc. * Copyright (C) 2023 Collabora Ltd. * Authors: Mars.C * AngeloGioacchino Del Regno > */ > > #include > @@ -19,6 +22,23 @@ / { > #address-cells = <2>; > #size-cells = <2>; > > + aliases { > + ovl0 = &ovl0; > + ovl1 = &ovl1; > + rdma0 = &rdma0; > + rdma1 = &rdma1; > + rdma2 = &rdma2; > + wdma0 = &wdma0; > + wdma1 = &wdma1; > + color0 = &color0; > + color1 = &color1; > + split0 = &split0; > + split1 = &split1; > + dpi0 = &dpi0; > + dsi0 = &dsi0; > + dsi1 = &dsi1; > + }; > + > psci { > compatible = "arm,psci-0.2"; > method = "smc"; > @@ -434,6 +454,26 @@ gce: mailbox@10212000 { > #mbox-cells = <2>; > }; > > + mipi_tx0: dsi-phy@10215000 { > + compatible = "mediatek,mt8173-mipi-tx"; > + reg = <0 0x10215000 0 0x1000>; > + clocks = <&clk26m>; > + clock-output-names = "mipi_tx0_pll"; > + #clock-cells = <0>; > + #phy-cells = <0>; > + status = "disabled"; > + }; > + > + mipi_tx1: dsi-phy@10216000 { > + compatible = "mediatek,mt8173-mipi-tx"; > + reg = <0 0x10216000 0 0x1000>; > + clocks = <&clk26m>; > + clock-output-names = "mipi_tx1_pll"; > + #clock-cells = <0>; > + #phy-cells = <0>; > + status = "disabled"; > + }; > + > gic: interrupt-controller@10221000 { > compatible = "arm,gic-400"; > #interrupt-cells = <3>; > @@ -690,6 +730,211 @@ mmsys: syscon@14000000 { > mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; > }; > > + ovl0: ovl@1400c000 { > + compatible = "mediatek,mt6795-disp-ovl", "mediatek,mt8173-disp-ovl"; > + reg = <0 0x1400c000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; > + clocks = <&mmsys CLK_MM_DISP_OVL0>; > + iommus = <&iommu M4U_PORT_DISP_OVL0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; > + }; > + > + ovl1: ovl@1400d000 { > + compatible = "mediatek,mt6795-disp-ovl", "mediatek,mt8173-disp-ovl"; > + reg = <0 0x1400d000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; > + clocks = <&mmsys CLK_MM_DISP_OVL1>; > + iommus = <&iommu M4U_PORT_DISP_OVL1>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; > + }; > + > + rdma0: rdma@1400e000 { > + compatible = "mediatek,mt6795-disp-rdma", "mediatek,mt8173-disp-rdma"; > + reg = <0 0x1400e000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; > + clocks = <&mmsys CLK_MM_DISP_RDMA0>; > + iommus = <&iommu M4U_PORT_DISP_RDMA0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; > + }; > + > + rdma1: rdma@1400f000 { > + compatible = "mediatek,mt6795-disp-rdma", "mediatek,mt8173-disp-rdma"; > + reg = <0 0x1400f000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; > + clocks = <&mmsys CLK_MM_DISP_RDMA1>; > + iommus = <&iommu M4U_PORT_DISP_RDMA1>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; > + }; > + > + rdma2: rdma@14010000 { > + compatible = "mediatek,mt6795-disp-rdma", "mediatek,mt8173-disp-rdma"; > + reg = <0 0x14010000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; > + clocks = <&mmsys CLK_MM_DISP_RDMA2>; > + iommus = <&iommu M4U_PORT_DISP_RDMA2>; > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; > + }; > + > + wdma0: wdma@14011000 { > + compatible = "mediatek,mt6795-disp-wdma", "mediatek,mt8173-disp-wdma"; > + reg = <0 0x14011000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; > + clocks = <&mmsys CLK_MM_DISP_WDMA0>; > + iommus = <&iommu M4U_PORT_DISP_WDMA0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; > + }; > + > + wdma1: wdma@14012000 { > + compatible = "mediatek,mt6795-disp-wdma", "mediatek,mt8173-disp-wdma"; > + reg = <0 0x14012000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; > + clocks = <&mmsys CLK_MM_DISP_WDMA1>; > + iommus = <&iommu M4U_PORT_DISP_WDMA1>; > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; > + }; > + > + color0: color@14013000 { > + compatible = "mediatek,mt6795-disp-color", "mediatek,mt8173-disp-color"; > + reg = <0 0x14013000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; > + clocks = <&mmsys CLK_MM_DISP_COLOR0>; > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>; > + }; > + > + color1: color@14014000 { > + compatible = "mediatek,mt6795-disp-color", "mediatek,mt8173-disp-color"; > + reg = <0 0x14014000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; > + clocks = <&mmsys CLK_MM_DISP_COLOR1>; > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; > + }; > + > + aal@14015000 { > + compatible = "mediatek,mt6795-disp-aal", "mediatek,mt8173-disp-aal"; > + reg = <0 0x14015000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; > + clocks = <&mmsys CLK_MM_DISP_AAL>; > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; > + }; > + > + gamma@14016000 { > + compatible = "mediatek,mt6795-disp-gamma", "mediatek,mt8173-disp-gamma"; > + reg = <0 0x14016000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; > + clocks = <&mmsys CLK_MM_DISP_GAMMA>; > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; > + }; > + > + merge@14017000 { > + compatible = "mediatek,mt6795-disp-merge", "mediatek,mt8173-disp-merge"; > + reg = <0 0x14017000 0 0x1000>; > + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; > + clocks = <&mmsys CLK_MM_DISP_MERGE>; > + }; > + > + split0: split@14018000 { > + compatible = "mediatek,mt6795-disp-split", "mediatek,mt8173-disp-split"; > + reg = <0 0x14018000 0 0x1000>; > + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; > + clocks = <&mmsys CLK_MM_DISP_SPLIT0>; > + }; > + > + split1: split@14019000 { > + compatible = "mediatek,mt6795-disp-split", "mediatek,mt8173-disp-split"; > + reg = <0 0x14019000 0 0x1000>; > + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; > + clocks = <&mmsys CLK_MM_DISP_SPLIT1>; > + }; > + > + ufoe@1401a000 { > + compatible = "mediatek,mt6795-disp-ufoe", "mediatek,mt8173-disp-ufoe"; > + reg = <0 0x1401a000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; > + clocks = <&mmsys CLK_MM_DISP_UFOE>; > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>; > + }; > + > + dsi0: dsi@1401b000 { > + compatible = "mediatek,mt6795-dsi", "mediatek,mt8173-dsi"; > + reg = <0 0x1401b000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; > + clocks = <&mmsys CLK_MM_DSI0_ENGINE>, > + <&mmsys CLK_MM_DSI0_DIGITAL>, > + <&mipi_tx0>; > + clock-names = "engine", "digital", "hs"; > + phys = <&mipi_tx0>; > + phy-names = "dphy"; > + status = "disabled"; > + }; > + > + dsi1: dsi@1401c000 { > + compatible = "mediatek,mt6795-dsi", "mediatek,mt8173-dsi"; > + reg = <0 0x1401c000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; > + clocks = <&mmsys CLK_MM_DSI1_ENGINE>, > + <&mmsys CLK_MM_DSI1_DIGITAL>, > + <&mipi_tx1>; > + clock-names = "engine", "digital", "hs"; > + phys = <&mipi_tx1>; > + phy-names = "dphy"; > + status = "disabled"; > + }; > + > + dpi0: dpi@1401d000 { > + compatible = "mediatek,mt6795-dpi", "mediatek,mt8183-dpi"; > + reg = <0 0x1401d000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; > + clocks = <&mmsys CLK_MM_DPI_PIXEL>, > + <&mmsys CLK_MM_DPI_ENGINE>, > + <&apmixedsys CLK_APMIXED_TVDPLL>; > + clock-names = "pixel", "engine", "pll"; > + status = "disabled"; > + }; > + > + pwm0: pwm@1401e000 { > + compatible = "mediatek,mt6795-disp-pwm", "mediatek,mt8173-disp-pwm"; > + reg = <0 0x1401e000 0 0x1000>; > + #pwm-cells = <2>; > + clocks = <&mmsys CLK_MM_DISP_PWM026M>, <&mmsys CLK_MM_DISP_PWM0MM>; > + clock-names = "main", "mm"; > + status = "disabled"; > + }; > + > + pwm1: pwm@1401f000 { > + compatible = "mediatek,mt6795-disp-pwm", "mediatek,mt8173-disp-pwm"; > + reg = <0 0x1401f000 0 0x1000>; > + #pwm-cells = <2>; > + clocks = <&mmsys CLK_MM_DISP_PWM126M>, <&mmsys CLK_MM_DISP_PWM1MM>; > + clock-names = "main", "mm"; > + status = "disabled"; > + }; > + > + mutex: mutex@14020000 { > + compatible = "mediatek,mt8173-disp-mutex"; > + reg = <0 0x14020000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; > + clocks = <&mmsys CLK_MM_MUTEX_32K>; > + mediatek,gce-events = , > + ; > + mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>; > + }; > + > larb0: larb@14021000 { > compatible = "mediatek,mt6795-smi-larb"; > reg = <0 0x14021000 0 0x1000>; > @@ -708,6 +953,13 @@ smi_common: smi@14022000 { > clock-names = "apb", "smi"; > }; > > + od@14023000 { > + compatible = "mediatek,mt6795-disp-od", "mediatek,mt8173-disp-od"; > + reg = <0 0x14023000 0 0x1000>; > + clocks = <&mmsys CLK_MM_DISP_OD>; > + mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>; > + }; > + > larb2: larb@15001000 { > compatible = "mediatek,mt6795-smi-larb"; > reg = <0 0x15001000 0 0x1000>; Reviewed-by: Alexandre Mergnat -- Regards, Alexandre _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel