Re: [PATCH v6 3/5] dt-bindings: memory: Add bindings for imx8m ddr controller

Chanwoo Choi
2019-11-15T05:17:52Z

Hi Leonard,

On 11/15/19 3:33 AM, Leonard Crestez wrote:
> Add devicetree bindings for the i.MX DDR Controller on imx8m series
> chips. It supports dynamic frequency switching between multiple data
> rates and this is exposed to Linux via the devfreq subsystem.
>
> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
> ---
> .../memory-controllers/fsl/imx8m-ddrc.yaml | 72 +++++++++++++++++++
> 1 file changed, 72 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml
>
> diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml
> new file mode 100644
> index 000000000000..c9e6c22cb5be
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml
> @@ -0,0 +1,72 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: https://protect2.fireeye.com/url?k=7d43eac6-20dfeba6-7d426189-0cc47a31307c-fcd69516893e0615&u=http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
> +$schema: https://protect2.fireeye.com/url?k=b9d87e43-e4447f23-b9d9f50c-0cc47a31307c-9fbd3b55b25cfa6d&u=http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: i.MX8M DDR Controller
> +
> +maintainers:
> + - Leonard Crestez <leonard.crestez@nxp.com>
> +
> +description:
> + The DDRC block is integrated in i.MX8M for interfacing with DDR based
> + memories.
> +
> + It supports switching between different frequencies at runtime but during
> + this process RAM itself becomes briefly inaccessible so actual frequency
> + switching is implemented by TF-A code which runs from a SRAM area.
> +
> + The Linux driver for the DDRC doesn't even map registers (they're included
> + for the sake of "describing hardware"), it mostly just exposes firmware
> + capabilities through standard Linux mechanism like devfreq and OPP tables.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - fsl,imx8mn-ddrc
> + - fsl,imx8mm-ddrc
> + - fsl,imx8mq-ddrc
> + - const: fsl,imx8m-ddrc
> +
> + reg:
> + maxItems: 1
> + description:
> + Base address and size of DDRC CTL area.
> + This is not currently mapped by the imx8m-ddrc driver.
> +
> + clocks:
> + maxItems: 4
> +
> + clock-names:
> + items:
> + - const: core
> + - const: pll
> + - const: alt
> + - const: apb
> +
> + operating-points-v2: true
> + opp-table: true
> +
> +required:
> + - reg
> + - compatible
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/imx8mm-clock.h>
> + ddrc: memory-controller@3d400000 {
> + compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
> + reg = <0x3d400000 0x400000>;
> + clock-names = "core", "pll", "alt", "apb";
> + clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
> + <&clk IMX8MM_DRAM_PLL>,
> + <&clk IMX8MM_CLK_DRAM_ALT>,
> + <&clk IMX8MM_CLK_DRAM_APB>;
> + operating-points-v2 = <&ddrc_opp_table>;
> + };
>

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

--
Best Regards,
Chanwoo Choi
Samsung Electronics