From: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
To: Peter Chen <peter.chen@cixtech.com>
Cc: arnd@arndb.de, geert+renesas@glider.be,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
cix-kernel-upstream@cixtech.com, Yunseong Kim <ysk@kzalloc.com>
Subject: Re: [PATCH v2 1/1] arm64: defconfig: Enable pinctrl/gpio/pcie for CIX Sky1 SoC
Date: Fri, 27 Mar 2026 12:21:04 +0100 [thread overview]
Message-ID: <08c8cd49-5fc2-4efb-9611-92d7d3c7c7dc@oss.qualcomm.com> (raw)
In-Reply-To: <acZmPUIHwJhJNT4x@nchen-desktop>
On 27/03/2026 12:13, Peter Chen wrote:
> On 26-03-27 11:22:33, Krzysztof Kozlowski wrote:
>
> Krzysztof, thanks for reviewing.
>
>>> Pinctrl, PCIe, and GPIO device are used at Radxa Orion O6 board.
>>> - Pinctrl is the base for peripheral IP and peripheral device.
>>> - PCIe NVMe is needed for Debian boot.
>>
>> I don't see NVMe there, only PCI controller.
>>
>>> - GPIO is added due to Debian bug report[1].
>>
>> Rationale must be here, not in external references - this explicitly
>> requested in submitting patches.
>>
>> This entire Debian reference does not really matter. It is enough to
>> explain what hardware you are enabling it for, so the board, its
>> contents, and SoC.
>>
>> This is as simple as - does board use it or not? Does SoC with this
>> board has it or not?
>
>
> So, I just only keep the below summary, is it right?
>
> Pinctrl, PCIe, and GPIO device are used at Radxa Orion O6 board which Sky1
> SoC is on it.
Which pinctrl? Which PCIe? Which GPIO device? Read it again and follow
its meaning and tell me if following understanding is correct:
"Pinctrl is used on Radxa Orion O6 board which Sky1 therefore I enable
Pinctrl Samsung".
Did you look at existing history for this type of changes? This is
triviality so I don't understand why we keep bugging for that simple
answer to describe WHY you are doing something.
Best regards,
Krzysztof
prev parent reply other threads:[~2026-03-27 11:21 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-27 9:56 [PATCH v2 1/1] arm64: defconfig: Enable pinctrl/gpio/pcie for CIX Sky1 SoC Peter Chen
2026-03-27 10:22 ` Krzysztof Kozlowski
2026-03-27 11:13 ` Peter Chen
2026-03-27 11:21 ` Krzysztof Kozlowski [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=08c8cd49-5fc2-4efb-9611-92d7d3c7c7dc@oss.qualcomm.com \
--to=krzysztof.kozlowski@oss.qualcomm.com \
--cc=arnd@arndb.de \
--cc=cix-kernel-upstream@cixtech.com \
--cc=geert+renesas@glider.be \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=peter.chen@cixtech.com \
--cc=ysk@kzalloc.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox