From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D533BCD68E3 for ; Tue, 10 Oct 2023 02:28:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=jA1Npvpc8Bh8yVBsLcnZk3zu5rRPQdXs2813S7yng5U=; b=BcqIbfdN4zN94w 4BJeQPOXrldmzc7A2MreBcZLuGWMM7DgekbrzA/GtzxcHVGWDY/BaSZ0rslhETfgC8yVPSGKaVo7O bFA497VSEN4Zjwa+KSOo9zr9tFVodDvC2l7Gc52zaMrtHzq7urQkMM4AV3iDCBxwCf6ZhImvLt54K xm6VvfSzo+Rb/4M3t6W97x73cBXZFFsOMeog0Keg0ImHlKPE2cb72vNn5LrFc+gNjNfC7GDA7Op5b L6w++qe4Esr+CCNaznmpsF4pco1v457RURgAHodJ2IHvr05cMycarh/znWHKwTjB48v+lIthXQTwh FSkDYDvoPlfpF5IMfaCQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qq2TW-00C6o8-2H; Tue, 10 Oct 2023 02:27:58 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qq2TT-00C6mw-0e for linux-arm-kernel@lists.infradead.org; Tue, 10 Oct 2023 02:27:57 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D172B1FB; Mon, 9 Oct 2023 19:28:30 -0700 (PDT) Received: from [10.163.61.202] (unknown [10.163.61.202]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BEF673F7A6; Mon, 9 Oct 2023 19:27:47 -0700 (PDT) Message-ID: <09877594-7d03-4f30-aec8-a0573bf295b8@arm.com> Date: Tue, 10 Oct 2023 07:57:45 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] driver: perf: arm_pmuv3: Read PMMIR_EL1 unconditionally To: James Clark , linux-arm-kernel@lists.infradead.org, zhangshaokun@hisilicon.com Cc: Will Deacon , Mark Rutland , linux-kernel@vger.kernel.org References: <20231009075631.193208-1-anshuman.khandual@arm.com> Content-Language: en-US From: Anshuman Khandual In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231009_192755_328005_2BACE136 X-CRM114-Status: GOOD ( 20.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi James, On 10/9/23 14:29, James Clark wrote: > > > On 09/10/2023 08:56, Anshuman Khandual wrote: >> PMMIR_EL1 needs to be captured in 'armpmu->reg_pmmir', for all appropriate >> PMU version implementations where the register is available and reading it >> is valid . Hence checking for bus slot event presence is redundant and can >> be dropped. >> >> Cc: Will Deacon >> Cc: Mark Rutland >> Cc: linux-arm-kernel@lists.infradead.org >> Cc: linux-kernel@vger.kernel.org >> Signed-off-by: Anshuman Khandual >> --- >> This applies on v6.6-rc5. >> >> drivers/perf/arm_pmuv3.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c >> index 1e72b486c033..9fc1b6da5106 100644 >> --- a/drivers/perf/arm_pmuv3.c >> +++ b/drivers/perf/arm_pmuv3.c >> @@ -1129,7 +1129,7 @@ static void __armv8pmu_probe_pmu(void *info) >> pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS); >> >> /* store PMMIR register for sysfs */ >> - if (is_pmuv3p4(pmuver) && (pmceid_raw[1] & BIT(31))) >> + if (is_pmuv3p4(pmuver)) >> cpu_pmu->reg_pmmir = read_pmmir(); >> else >> cpu_pmu->reg_pmmir = 0; > > > This does have the side effect of showing non-zero values in caps/slots > even when the STALL_SLOT event isn't implemented. I think that's the > scenario that the original commit (f5be3a61fd) was trying to avoid: But the the sysfs interface is supposed to show all the PMMIR_EL1 based HW attributes as captured irrespective of bus slots event's presence as the register could be read on ARMv8.4-PMU without additional conditions imposed upon from the architecture. > > /sys/bus/event_source/devices/armv8_pmuv3_0/caps/slots is exposed > under sysfs. [If] Both ARMv8.4-PMU and STALL_SLOT event are > implemented, it returns the slots from PMMIR_EL1, otherwise it will > return 0. But that additional requirement of STALL_SLOT event is just SW mandated without any architectural backing. > > I can't really think of a scenario where that would be an issue, and the > availability of the STALL_SLOT event is already discoverable from > userspace through the events folder, so it's probably fine. Absolutely. > > Adding the original author just in case. But otherwise: > > Reviewed-by: James Clark Thanks ! _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel