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([2a02:2f05:1204:e000:2cf7:c250:64a9:ae77]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49fcd090f0csm106078635e9.15.2026.09.19.07.14.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 19 Sep 2026 07:14:21 -0700 (PDT) Message-ID: <09c057fe-bcaa-4e57-bedc-40dc1fcc770c@tuxon.dev> Date: Sat, 19 Sep 2026 17:14:18 +0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/6] arm64: dts: microchip: lan969x: add SDMMC nodes To: Robert Marko , ulfh@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, adrian.hunter@intel.com, aubin.constans@microchip.com, ehristev@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: luka.perkov@sartura.hr References: <20260907132617.1198548-1-robert.marko@sartura.hr> <20260907132617.1198548-5-robert.marko@sartura.hr> Content-Language: en-US From: claudiu beznea In-Reply-To: <20260907132617.1198548-5-robert.marko@sartura.hr> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260919_071424_522009_F0F1822F X-CRM114-Status: GOOD ( 15.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, Roberto, On 9/7/26 16:25, Robert Marko wrote: > Add nodes for both SDMMC controllers. Connect their bus interface clock to > the fabric clock and their core clock to the corresponding generated clock. > > Configure SDMMC0 with a 100 MHz generated clock for 50 MHz eMMC DDR > operation. Configure SDMMC1 with an exact 50 MHz generated clock so the > integer base clock encoded in the SDHCI capabilities remains accurate and > the identification clock does not exceed 400 kHz. > > Keep both nodes ordered by unit address. > > Signed-off-by: Robert Marko > --- > Changes in v2: > * Use the fabric clock for the SDMMC bus interface clock. > * Configure SDMMC1 with an exact 50 MHz generated clock. > * Move the SDMMC1 node to preserve unit-address ordering. > * Explain the selected clock rates in the commit description. > > arch/arm64/boot/dts/microchip/lan9691.dtsi | 24 ++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/arch/arm64/boot/dts/microchip/lan9691.dtsi b/arch/arm64/boot/dts/microchip/lan9691.dtsi > index a8541c6a098d..5e330d5fab50 100644 > --- a/arch/arm64/boot/dts/microchip/lan9691.dtsi > +++ b/arch/arm64/boot/dts/microchip/lan9691.dtsi > @@ -414,6 +414,18 @@ qspi0: spi@e0804000 { > status = "disabled"; > }; > > + sdmmc0: mmc@e0830000 { > + compatible = "microchip,lan9691-sdhci", > + "microchip,sam9x60-sdhci"; > + reg = <0xe0830000 0x00000300>; s/0x00000300/0x300 > + interrupts = ; > + clocks = <&fabric_clk>, <&clks GCK_ID_SDMMC0>; > + clock-names = "hclock", "multclk"; > + assigned-clocks = <&clks GCK_ID_SDMMC0>; > + assigned-clock-rates = <100000000>; > + status = "disabled"; > + }; > + > qspi2: spi@e0834000 { > compatible = "microchip,lan9691-qspi"; > reg = <0xe0834000 0x00000100>, > @@ -429,6 +441,18 @@ qspi2: spi@e0834000 { > status = "disabled"; > }; > > + sdmmc1: mmc@e0838000 { > + compatible = "microchip,lan9691-sdhci", > + "microchip,sam9x60-sdhci"; > + reg = <0xe0838000 0x00000300>; Same here. I can adjust it while applying. With that addressed: Reviewed-by: Claudiu Beznea