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Wed, 11 Feb 2026 11:06:21 -0800 (PST) Received: from luca-vm.lan ([154.61.61.58]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4378e122df9sm211223f8f.15.2026.02.11.11.06.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Feb 2026 11:06:21 -0800 (PST) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Luca Leonardo Scorcia , Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/7] soc: mediatek: mtk-mmsys: Add resets for mt8167 Date: Wed, 11 Feb 2026 19:03:22 +0000 Message-ID: <0ab331c556d76ddfc7f287d6288c4f60f4ef90c8.1770836190.git.l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260211_110623_845475_08284B50 X-CRM114-Status: GOOD ( 11.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The mt8167 SoC has 64 MMSYS resets, split in two contiguous 32-bits registers, MMSYS_SW0_RST_B (0x140) and MMSYS_SW1_RST_B (0x144), as also stated in the downstream kernel for the Lenovo Smart Clock in the ddp_reg.h header. Signed-off-by: Luca Leonardo Scorcia --- drivers/soc/mediatek/mt8167-mmsys.h | 3 +++ drivers/soc/mediatek/mtk-mmsys.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/drivers/soc/mediatek/mt8167-mmsys.h b/drivers/soc/mediatek/mt8167-mmsys.h index eef14083c47b..2d20b21fb0ea 100644 --- a/drivers/soc/mediatek/mt8167-mmsys.h +++ b/drivers/soc/mediatek/mt8167-mmsys.h @@ -18,6 +18,9 @@ #define MT8167_DSI0_SEL_IN_RDMA0 0x1 #define MT8167_DSI0_SEL_IN_MASK 0x3 +#define MT8167_MMSYS_SW0_RST_B 0x140 +#define MT8167_MMSYS_SW1_RST_B 0x144 + static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = { MMSYS_ROUTE(OVL0, COLOR0, MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0, diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index bb4639ca0b8c..03cbc393f978 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -57,6 +57,8 @@ static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { .clk_driver = "clk-mt8167-mm", .routes = mt8167_mmsys_routing_table, .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table), + .sw0_rst_offset = MT8167_MMSYS_SW0_RST_B, + .num_resets = 64, }; static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { -- 2.43.0