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[188.141.3.146]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45df16b11b6sm26494715e9.6.2025.09.10.04.09.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 10 Sep 2025 04:09:21 -0700 (PDT) Message-ID: <0ac2c3f4-d71d-48eb-ac0f-8e736e7acace@linaro.org> Date: Wed, 10 Sep 2025 12:09:20 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3.1] media: dt-bindings: Add qcom,qcs8300-camss compatible To: Vikram Sharma , mchehab@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, hverkuil-cisco@xs4all.nl, cros-qcom-dts-watchers@chromium.org, catalin.marinas@arm.com, will@kernel.org Cc: linux-arm-kernel@lists.infradead.org, quic_svankada@quicinc.com, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Nihal Kumar Gupta References: <20250813053724.232494-2-quic_vikramsa@quicinc.com> <20250910104915.1444669-1-quic_vikramsa@quicinc.com> From: Bryan O'Donoghue Content-Language: en-US In-Reply-To: <20250910104915.1444669-1-quic_vikramsa@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250910_040924_486063_A927E577 X-CRM114-Status: GOOD ( 16.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 10/09/2025 11:49, Vikram Sharma wrote: > Add the compatible string "qcom,qcs8300-camss" to support the > Camera Subsystem (CAMSS) on the Qualcomm QCS8300 platform. > > The QCS8300 platform provides: > - 2 x VFE (version 690), each with 3 RDI > - 5 x VFE Lite (version 690), each with 6 RDI > - 2 x CSID (version 690) > - 5 x CSID Lite (version 690) > - 3 x CSIPHY (version 690) > - 3 x TPG > > Co-developed-by: Nihal Kumar Gupta > Signed-off-by: Nihal Kumar Gupta > Signed-off-by: Vikram Sharma > --- > changes since v3: > - Adding supplies to enable camera sensor imx577 on monaco-evk. > link for camera sensor enablement chagges: > https://lore.kernel.org/all/20250909114241.840842-1-quic_vikramsa@quicinc.com/ > - Dropped RB from Bryan and Krzysztof to review again. > --- > .../bindings/media/qcom,qcs8300-camss.yaml | 349 ++++++++++++++++++ > 1 file changed, 349 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml > > diff --git a/Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml b/Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml > new file mode 100644 > index 000000000000..559db6d67f06 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml > @@ -0,0 +1,349 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/qcom,qcs8300-camss.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm QCS8300 CAMSS ISP > + > +maintainers: > + - Vikram Sharma > + > +description: > + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. > + > +properties: > + compatible: > + const: qcom,qcs8300-camss > + > + reg: > + maxItems: 21 > + > + reg-names: > + items: > + - const: csid_wrapper > + - const: csid0 > + - const: csid1 > + - const: csid_lite0 > + - const: csid_lite1 > + - const: csid_lite2 > + - const: csid_lite3 > + - const: csid_lite4 > + - const: csiphy0 > + - const: csiphy1 > + - const: csiphy2 > + - const: tpg0 > + - const: tpg1 > + - const: tpg2 > + - const: vfe0 > + - const: vfe1 > + - const: vfe_lite0 > + - const: vfe_lite1 > + - const: vfe_lite2 > + - const: vfe_lite3 > + - const: vfe_lite4 > + > + clocks: > + maxItems: 26 > + > + clock-names: > + items: > + - const: camnoc_axi > + - const: core_ahb > + - const: cpas_ahb > + - const: cpas_fast_ahb_clk > + - const: cpas_vfe_lite > + - const: cpas_vfe0 > + - const: cpas_vfe1 > + - const: csid > + - const: csiphy0 > + - const: csiphy0_timer > + - const: csiphy1 > + - const: csiphy1_timer > + - const: csiphy2 > + - const: csiphy2_timer > + - const: csiphy_rx > + - const: gcc_axi_hf > + - const: gcc_axi_sf > + - const: icp_ahb > + - const: vfe0 > + - const: vfe0_fast_ahb > + - const: vfe1 > + - const: vfe1_fast_ahb > + - const: vfe_lite > + - const: vfe_lite_ahb > + - const: vfe_lite_cphy_rx > + - const: vfe_lite_csid > + > + interrupts: > + maxItems: 20 > + > + interrupt-names: > + items: > + - const: csid0 > + - const: csid1 > + - const: csid_lite0 > + - const: csid_lite1 > + - const: csid_lite2 > + - const: csid_lite3 > + - const: csid_lite4 > + - const: csiphy0 > + - const: csiphy1 > + - const: csiphy2 > + - const: tpg0 > + - const: tpg1 > + - const: tpg2 > + - const: vfe0 > + - const: vfe1 > + - const: vfe_lite0 > + - const: vfe_lite1 > + - const: vfe_lite2 > + - const: vfe_lite3 > + - const: vfe_lite4 > + > + interconnects: > + maxItems: 2 > + > + interconnect-names: > + items: > + - const: ahb > + - const: hf_0 > + > + iommus: > + maxItems: 1 > + > + power-domains: > + items: > + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. > + > + power-domain-names: > + items: > + - const: top > + > + vdda-phy-supply: > + description: > + Phandle to a regulator supply to PHY core block. > + > + vdda-pll-supply: > + description: > + Phandle to 1.8V regulator supply to PHY refclk pll block. > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + description: > + CSI input ports. > + > + patternProperties: > + "^port@[0-2]+$": > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port for receiving CSI data on CSIPHY 0-2. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + required: > + - data-lanes > + > +required: > + - compatible > + - reg > + - reg-names > + - clocks > + - clock-names > + - interrupts > + - interrupt-names > + - interconnects > + - interconnect-names > + - iommus > + - power-domains > + - vdda-phy-supply > + - vdda-pll-supply > + - power-domain-names > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + #include > + #include > + #include > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + isp@ac78000 { > + compatible = "qcom,qcs8300-camss"; > + > + reg = <0x0 0xac78000 0x0 0x1000>, > + <0x0 0xac7a000 0x0 0x0f00>, > + <0x0 0xac7c000 0x0 0x0f00>, > + <0x0 0xac84000 0x0 0x0f00>, > + <0x0 0xac88000 0x0 0x0f00>, > + <0x0 0xac8c000 0x0 0x0f00>, > + <0x0 0xac90000 0x0 0x0f00>, > + <0x0 0xac94000 0x0 0x0f00>, > + <0x0 0xac9c000 0x0 0x2000>, > + <0x0 0xac9e000 0x0 0x2000>, > + <0x0 0xaca0000 0x0 0x2000>, > + <0x0 0xacac000 0x0 0x0400>, > + <0x0 0xacad000 0x0 0x0400>, > + <0x0 0xacae000 0x0 0x0400>, > + <0x0 0xac4d000 0x0 0xd000>, > + <0x0 0xac60000 0x0 0xd000>, > + <0x0 0xac85000 0x0 0x0d00>, > + <0x0 0xac89000 0x0 0x0d00>, > + <0x0 0xac8d000 0x0 0x0d00>, > + <0x0 0xac91000 0x0 0x0d00>, > + <0x0 0xac95000 0x0 0x0d00>; > + reg-names = "csid_wrapper", > + "csid0", > + "csid1", > + "csid_lite0", > + "csid_lite1", > + "csid_lite2", > + "csid_lite3", > + "csid_lite4", > + "csiphy0", > + "csiphy1", > + "csiphy2", > + "tpg0", > + "tpg1", > + "tpg2", > + "vfe0", > + "vfe1", > + "vfe_lite0", > + "vfe_lite1", > + "vfe_lite2", > + "vfe_lite3", > + "vfe_lite4"; > + > + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, > + <&camcc CAM_CC_CORE_AHB_CLK>, > + <&camcc CAM_CC_CPAS_AHB_CLK>, > + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, > + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, > + <&camcc CAM_CC_CPAS_IFE_0_CLK>, > + <&camcc CAM_CC_CPAS_IFE_1_CLK>, > + <&camcc CAM_CC_CSID_CLK>, > + <&camcc CAM_CC_CSIPHY0_CLK>, > + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY1_CLK>, > + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY2_CLK>, > + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, > + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, > + <&gcc GCC_CAMERA_HF_AXI_CLK>, > + <&gcc GCC_CAMERA_SF_AXI_CLK>, > + <&camcc CAM_CC_ICP_AHB_CLK>, > + <&camcc CAM_CC_IFE_0_CLK>, > + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, > + <&camcc CAM_CC_IFE_1_CLK>, > + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, > + <&camcc CAM_CC_IFE_LITE_CLK>, > + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, > + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, > + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; > + clock-names = "camnoc_axi", > + "core_ahb", > + "cpas_ahb", > + "cpas_fast_ahb_clk", > + "cpas_vfe_lite", > + "cpas_vfe0", > + "cpas_vfe1", > + "csid", > + "csiphy0", > + "csiphy0_timer", > + "csiphy1", > + "csiphy1_timer", > + "csiphy2", > + "csiphy2_timer", > + "csiphy_rx", > + "gcc_axi_hf", > + "gcc_axi_sf", > + "icp_ahb", > + "vfe0", > + "vfe0_fast_ahb", > + "vfe1", > + "vfe1_fast_ahb", > + "vfe_lite", > + "vfe_lite_ahb", > + "vfe_lite_cphy_rx", > + "vfe_lite_csid"; > + > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + interrupt-names = "csid0", > + "csid1", > + "csid_lite0", > + "csid_lite1", > + "csid_lite2", > + "csid_lite3", > + "csid_lite4", > + "csiphy0", > + "csiphy1", > + "csiphy2", > + "tpg0", > + "tpg1", > + "tpg2", > + "vfe0", > + "vfe1", > + "vfe_lite0", > + "vfe_lite1", > + "vfe_lite2", > + "vfe_lite3", > + "vfe_lite4"; > + > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY > + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, > + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "ahb", > + "hf_0"; > + > + iommus = <&apps_smmu 0x2400 0x20>; > + > + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; > + power-domain-names = "top"; > + > + vdda-phy-supply = <&vreg_l4a_0p88>; > + vdda-pll-supply = <&vreg_l1c_1p2>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + }; OK LGTM thanks for your update. Reviewed-by: Bryan O'Donoghue