[PATCH 21/22] arm64: dts: apple: t8010: Add cpufreq nodes

Nick Chan
2024-09-11T09:12:22Z

Add cpufreq nodes for the A10 SoC.

The Apple iPod touch 7 can only go up to 1.64 GHz, so the higher operating
points are in t8010-fast.dtsi.

A10 consists of logical cores that switches between E-mode and P-mode
depending on the current p-state. Each mode have different capacities so
the E-mode frequencies are adjusted to make performance scale linearly
with clock speed.

Signed-off-by: Nick Chan <towinchenmi@gmail.com>
---
arch/arm64/boot/dts/apple/t8010-fast.dtsi | 19 +++++++
arch/arm64/boot/dts/apple/t8010.dtsi | 60 +++++++++++++++++++++++
2 files changed, 79 insertions(+)

diff --git a/arch/arm64/boot/dts/apple/t8010-fast.dtsi b/arch/arm64/boot/dts/apple/t8010-fast.dtsi
index 4bdf1c3eccfe..9a263eadc776 100644
--- a/arch/arm64/boot/dts/apple/t8010-fast.dtsi
+++ b/arch/arm64/boot/dts/apple/t8010-fast.dtsi
@@ -6,3 +6,22 @@
*/

#include "t8010.dtsi"
+
+/ {
+ opp: opp-table-0 {
+ opp08 {
+ opp-hz = /bits/ 64 <1944000000>;
+ opp-level = <8>;
+ };
+
+ opp09 {
+ opp-hz = /bits/ 64 <2244000000>;
+ opp-level = <9>;
+ };
+
+ opp10 {
+ opp-hz = /bits/ 64 <2340000000>;
+ opp-level = <10>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/apple/t8010.dtsi b/arch/arm64/boot/dts/apple/t8010.dtsi
index 926a0f501477..e7d7194b412c 100644
--- a/arch/arm64/boot/dts/apple/t8010.dtsi
+++ b/arch/arm64/boot/dts/apple/t8010.dtsi
@@ -50,6 +50,8 @@ cpu0: cpu@0 {
compatible = "apple,hurricane-zephyr";
reg = <0x0 0x0>;
cpu-release-addr = <0 0>; /* To be filled by loader */
+ operating-points-v2 = <&opp>;
+ performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
};
@@ -58,11 +60,63 @@ cpu1: cpu@1 {
compatible = "apple,hurricane-zephyr";
reg = <0x0 0x1>;
cpu-release-addr = <0 0>; /* To be filled by loader */
+ operating-points-v2 = <&opp>;
+ performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
};
};

+ opp: opp-table-0 {
+ compatible = "operating-points-v2";
+
+ /*
+ * The E-core frequencies are adjusted so performance scales
+ * linearly with reported clock speed.
+ */
+
+ opp01 {
+ opp-hz = /bits/ 64 <149000000>; /* 396 MHz, E-core */
+ opp-level = <1>;
+ };
+
+ opp02 {
+ opp-hz = /bits/ 64 <275000000>; /* 732 MHz, E-core */
+ opp-level = <2>;
+ };
+
+ opp03 {
+ opp-hz = /bits/ 64 <410000000>; /* 1092 MHz, E-core */
+ opp-level = <3>;
+ };
+
+ /* The following operating points are handled by the P-cores */
+ opp04 {
+ opp-hz = /bits/ 64 <756000000>;
+ opp-level = <4>;
+ };
+
+ opp05 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-level = <5>;
+ };
+
+ opp06 {
+ opp-hz = /bits/ 64 <1356000000>;
+ opp-level = <6>;
+ };
+
+ opp07 {
+ opp-hz = /bits/ 64 <1644000000>;
+ opp-level = <7>;
+ };
+
+ /*
+ * The iPod Touch 7 supports up to 1.6 GHz, faster operating
+ * points for other devices are in t8010-fast.dtsi
+ */
+ };
+
memory@800000000 {
device_type = "memory";
reg = <0x8 0 0 0>; /* To be filled by loader */
@@ -86,6 +140,12 @@ soc {
nonposted-mmio;
ranges;

+ cpufreq: performance-controller@202f20000 {
+ compatible = "apple,t8010-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
+ reg = <0x2 0x2f20000 0 0x1000>;
+ #performance-domain-cells = <0>;
+ };
+
serial0: serial@20a0c0000 {
compatible = "apple,s5l-uart";
reg = <0x2 0x0a0c0000 0x0 0x4000>;
--
2.46.0